599 results on '"Horiguchi, N."'
Search Results
202. Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors
203. Low frequency noise performance of gate-first and replacement metal gate CMOS technologies
204. Impact of oxide trap passivation by fluorine on the low-frequency noise behavior of gate-last pMOSFETs
205. Kinetic Monte Carlo simulations for dopant diffusion and defects in Si and SiGe: Analysis of dopants in SiGe-channel Quantum Well
206. (Invited) Stress Simulations of Si- and Ge-Channel FinFETs for the 14 nm-Node and Beyond
207. Femtosecond laser induced periodic nanostructures on titanium dioxide film for improving biocompatibility
208. Development of visible-light activated titanium dioxide films with femtosecond laser
209. Integration Challenges and Options of Replacement High- /Metal Gate Technology for (Sub-)22nm Technology Nodes
210. Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry
211. Standard cell level parasitics assessment in 20nm BPL and 14nm BFF
212. Stress simulations for optimal mobility group IV p- and nMOS FinFETs for the 14 nm node and beyond
213. Analysis of dopant diffusion and defects in SiGe-channel Implant Free Quantum Well (IFQW) devices using an atomistic kinetic Monte Carlo approach
214. Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs
215. W vs. Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22nm Tech. Nodes
216. Si1-yGey or Ge1-zSnz Source/Drain Stressors on Strained Si1-xGex-Channel PFETS: A TCAD Study
217. RMG Tech. Integration in FinFET Devices
218. Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.
219. 2D and 3D Fully-Depleted Extension-less Devices for Advanced Logic and Memory Applications
220. Device Architectures and Their Integration Challenges for 1x nm node: FinFETs with High Mobility Channel
221. Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs
222. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks
223. Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements
224. Atom Probe Tomography for 3D-dopant analysis in FinFET devices
225. 85nm-wide 1.5mA/µm-ION IFQW SiGe-pFET: Raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study
226. Process control & integration options of RMG technology for aggressively scaled devices
227. Scanning spreading resistance microscopy for carrier profiling beyond 32nm node
228. Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications
229. Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs
230. Impact of fin height variations on SRAM yield
231. On the rseries extraction techniques for sub-22nm CMOS finfet and SiGe technologies
232. High performance n-MOS finFET by damage-free, conformal extension doping
233. Analysis of dopant diffusion and defects in SiGe channel Quantum Well for Laser annealed device using an atomistic kinetic Monte Carlo approach
234. Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
235. High performance Si.45Ge.55 Implant Free Quantum Well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation
236. Superior NBTI reliability of SiGe channel pMOSFETs: Replacement gate, FinFETs, and impact of Body Bias
237. 3D-carrier profiling in FinFETs using scanning spreading resistance microscopy
238. Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO2 VS Si-cap
239. Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability
240. Response of a single trap to AC negative Bias Temperature stress
241. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
242. Novel Approach to Conformal FINFET Extension Doping
243. FinFETs Junctions Optimization by Conventional Ion Implantation for (Sub-)22nm Technology Nodes Circuit Applications
244. ChemInform Abstract: Stereodivergent Diels-Alder Reactions Employing Cyclitols as Chiral Auxiliaries.
245. Dopant and carrier profiling in FinFET-based devices with sub-nanometer resolution
246. Ion-implantation-based low-cost Hk/MG process for CMOS low-power application
247. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout
248. A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
249. Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell
250. Correlation Between the $V_{\rm th}$ Adjustment of nMOSFETs With HfSiO Gate Oxide and the Energy Profile of the Bulk Trap Density
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