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Owing to miniaturization and low-power electronics, mobile, implanted, and wearable devices have become the main trends of electronics during the past decade. There has been much research regarding energy harvesting to achieve battery-free or self-powered devices. The optimal design problems of a double-pendulum kinetic-energy harvester from human motion are studied in this paper. For the given form factor, the weight of the harvester, and the known human excitation, the optimal design problem is solved using a dynamic non-linear double-pendulum model and an electric generator. The average electrical power was selected as the performance index for the given time period. A double-pendulum harvester was proven to be more efficient than a single-pendulum harvester when the appropriate parameters were used.

The conventional infrared (IR) proximity-based three-directional (3D) motion gesture sensors (MGSs) detect hand motion by using either a single IR LED and multiple photosensors or multiple IR LEDs and a single photosensor. Since an IR LED is the most power hungry component, MGSs with a single IR LED and multiple photosensors are preferred for low-power applications. In this configuration, the recognition rate of an MGS is the function of the space between each photosensor. In order to achieve a high recognition rate, external photosensors resulting in a large form factor are inevitable. In this paper, a 3D MGS for low-power portable applications is proposed. The proposed optical blocks allow for a small form factor and ultra-low profile packaging by integrating photosensors in a single chip.

System security is currently a main focus area for all IT infrastructure providers. New system features like pervasive encryption, the transition to cloud-based offerings, and the demand for quantum-safe platforms demand increased cryptographic performance as well as more cryptographic agility. The new IBM 4769 Cryptographic Coprocessor addresses these trends. It brings performance improvements that match the requirements of the new IBM z15. A combination of newly available features allows IBM z15 to scale to greater than 5,000 Virtual Hardware secure modules per system and makes it suitable to support virtualized client environments such as cloud-scale datacenters. To meet the dense packaging and energy requirements of those data centers, the form factor and power consumption of the card were reduced significantly. The card also offers an expanded set of algorithms to support state-of-the-art as well as future workloads. For the first time, the user interface provides access to a selected set of quantum-safe algorithms. Infrastructure extensions add hardware-embedded, attestation-friendly trusted boot services, which improve system resiliency by providing hardware enabled measurements of the secure and trusted boot process. These extensions simultaneously simplify the security certifications built on them. This article provides an overview of the IBM 4769 cryptographic coprocessor, highlighting security characteristics, internal hardware, form factor, and enhanced firmware.

Mobile device has been the most important personal computational platform. Researches increasingly focus on glasses-free 3D display that features thin form factor and low power consumption. Once glasses-free 3D display is applied in the mobile devices, it will affect or even change the observation habit and thinking manner of human being. In this paper, the solutions that were compatible with flat display were introduced. Parallax barrier, lenticular lens array, spatio-temporal multiplexing 3D display, integral 3D display, compressive lightfield display, and vector 3D display were successively introduced in detail. Furthermore, the limitations that currently prevent these technologies from commercialization were discussed in depth. Finally, the potential research trends were highlighted.

A miniaturized class of satellites called SmallSats, whose weight are typically under 500 kg, has recently garnered significant attention to exploit space for many applications. A key member of the SmallSat family are CubeSats. CubeSats can weigh as little as 1.33 kg with a volume as small as 10 x 10 x 10 cm3. Realizing the potential of CubeSats, the scientific community is revisiting existing spacecraft technologies to enable their integration with the small CubeSat form factor [1,2]. This chapter particularly focuses on the antenna research and development. We review the general constraints that antenna engineers face while designing antenna systems for CubeSats. An extensive literature collection is presented to survey the current state of the art in antenna systems for CubeSats. We also discuss recent antenna research that enables many exciting missions in the future.

International audience; In this paper, we explore the interaction space of MobiLimb, a small 5-DOF serial robotic manipulator attached to a mobile device. It (1) overcomes some limitations of mobile devices (static, passive, motionless); (2) preserves their form factor and I/O capabilities; (3) can be easily attached to or removed from the device; (4) offers additional I/O capabilities such as physical deformation and (5) can support various modular elements such as sensors, lights or shells. We illustrate its potential through three classes of applications: As a tool, MobiLimb offers tangible affordances and an expressive controller that can be manipulated to control virtual and physical objects. As a partner, it reacts expressively to users' actions to foster curiosity and engagement or assist users. As a medium, it provides rich haptic feedback such as strokes, pat and other tactile stimuli on the hand or the wrist to convey emotions during mediated multimodal communications.

Wide scale interest and adoption of Internet of Things (IoT) technologies is fuelling innovation in the way individuals and even machines can interact to exchange knowledge. One area of particular interest is that of analytics. Ever decreasing form factor hardware is enabling computation and data storage to be embedded into many different devices. The combination of network connectivity and emerging distributed models of service orchestration is allowing the creation of new ways of measuring, monitoring and analysing performance. Using an approach inspired by the NIST seven layer model of cloud computing, we propose a model of connectivity that enables analytics services to be consumed across individual system components that are distributed, such as those found in the IoT and Industrial IoT (IIoT) domains.

FOWLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduces the total form factor all in a cost-effectiveness format. FOWLP volumes have largely been driven by mobile and consumer applications (RF, BB, connectivity, NFC, PMIC, audio codec, MCU etc) and are now moving to 5G communication, mmWave, automotive, MEMS/Sensor and IoT/WE applications. Advanced embedded Wafer Level Ball Grid Array (eWLB) provides a versatile platform for the semiconductor industry’s technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. WLP (wafer level packaging) has already been adopted in the automotive market for cabin or infotainment applications as well as 77GHz radar sensors utilizing FO-WLP.This study focuses on the development of eWLB for mmWave applications above 60GHz with CMOS IC technology. Additionally the case study of 77GHz ADAS automotive radar is discussed. Package design optimization of single-die and multi-die, electrical performance characterization and component level reliability tests are presented.

Always ON always sensing small form factor edge systems for internet of things (IOT) are becoming ubiquitous. Many applications require these tiny devices to be self-powered and maintenance-free. Hence, they should be able to harvest energy from available ambient sources and should have low manufacturing cost. Millimeter-scale form factor systems have been developed in academia for the past few years. Small form factor edge systems are becoming commercially available. These systems are essential in today’s cyber physical world. We will introduce the available market and the trends driving this growth in IOT system deployments. That will be followed by typical system requirements for a typical self-powered IOT system. Challenges to realize such a dream IOT system will be discussed. We will present two approaches to system design, namely bottom-up and top-down. An X86-based tiny microcontroller unit (MCU) was designed to enable multiple IOT usages. This MCU followed a bottom-up approach – ultra-low power low cost MCU was designed first and then applied to IOT systems such as smart sensor tag for package tracking. The discussion will introduce another IOT system that followed a top-down usage-driven approach. In this case, an agricultural usage was chosen that required energy harvesting, X86-class edge computing, visual recognition on the edge, secure storage, secure wireless communication and ultra-low power maintenance free operation. An IOT system was architected for this usage and later demonstrated. We will conclude the presentation with comparison of these two distinct approaches to IOT system design.

The sheer complexity of systems at various abstraction levels makes the design a tedious and time consuming process. Post that to ratify the design whether it is working as per the expected requirements makes validation and verification even more time consuming and expensive process. When it comes to platform level validation; there are various nuisances that are to be looked at and the list increases, starting from silicon continuing to all the way till software. And if at all there are bugs that manifest at platform level narrowing down onto the bug cause and fixing it post debugging is a big challenge. In this paper we try to introduce a methodology for validation and debug that could be put forth for across the systems blurring the lines of form factor and other dependencies like having new features tested completely & rapidly, and would shorten the life span of test plan creation and bug fixing which would result in lots of dollars being saved, and also providing a unification methodology for upcoming systems across the wide range of products ranging from IoTs till servers.

How can we design digital artefacts to help young adults with low self-esteem feel happier? To gain new insights into young adult’s self-esteem problems and how we might help support them with interactive technologies, we conducted a mixed method user-centred study. We used a 6-week cultural probe study with 11 young adults, including a focus group, to understand current practices in managing self-esteem with everyday technologies. We then co-designed interactive digital artefacts for helping improve self-esteem, to deploy as technology probes with 6 young adults for four weeks.Our contribution is two-fold. Firstly, we present the Self- Esteem Technology Support (SETS) framework for informing design of interactive technologies supporting young adults in managing low self-esteem. Secondly, we propose that interactive technologies designed to help young people feel happier need to be flexible, adaptable, private, available, personalisable, and have an engaging form factor to inspire feelings of fondness toward having the device as part of their daily routines.

One of the most common pieces of opto-mechanical hardware is the one inch, tip-tilt, mirror mount. Though there are numerous manufacturers of these mounts the majority of the designs follow the familiar theme of a corner pivot point and two adjustable actuators located orthogonally. This type of mount (often referred to as simply a “kinematic” mirror mount) can be found in many sizes and has been tailored for many different applications. While the simple and robust design has proven effective in many circumstances there are times when it isn’t ideal. Common issues with these mounts include long term stability, temperature dependent pointing and sensitivity to external shock and vibration. These shortcomings have led many to develop alternatives, which is especially true when designing for OEM applications. Though many alternatives have been devised and implemented they often lack the convenience and simplicity of the well-known form and are never broadly adopted. This paper details an alternative design that has the potential to meet the needs of laboratory use while being equally well suited for demanding OEM applications. The design explored, addresses the common shortcomings listed while keeping to a compact and convenient form factor. The mirror mount has a virtual pivot point centered on the front surface of the mounted mirror and is fully lockable. The resulting approach is compared directly to the features and function of the familiar “kinematic” mirror mount form.

Since the first demonstration of an integrated circuit in 1958, the ambitious semiconductor technology has been racing for almost six decades to change the face of the Earth. Moore’s Law and the ‘virtuous cycle’ of investment, scaling and market growth have fueled the sweeping influence that the semiconductor industry now has on every aspect of our everyday lives and the global economic system. Thanks to the striking drop in the cost of computing power, from 5.52 US dollars for a single transistor in 1954 to a billionth of a dollar in 2016, countless human dreams have been realized; from the Apollo missions to the AI and social networking era. While the continued scaling of traditional complementary metal–oxide–semiconductor (CMOS) devices took over the market with its impressive progress, another paradigm of electronics has taken shape: flexible electronics. Instead of focusing on shrinking critical dimensions and reducing power consumption, the growing field of flexible electronics rather aims to leverage compliant form factors and lightweight designs to usher radically novel electronic devices into our lives. Flexible displays, electronic textiles, bio-inspired sensors, and wearable or implantable medical devices, just to name a few, are out-of-reach applications for the rigid form factor of conventional wafer-based electronics. Flexible electronics is more than just a fill-in or an alternative for where conventional electronics fall short. If the integrated circuit was the game changer of the twentieth century, then flexible electronics is the catalyst for the paradigm shift of the twenty-first century.

Subscriber Identity Module (SIM) is an integrated circuit card on the mobile phone used for identifying and authenticating subscribers on mobile networks and for establishing a connection with the mobile network. Over the years, we have witnessed considerable change in the size of SIM card. SIM card size has reduced from 1FF (Form Factor) to 4FF (nano SIM), which is currently being used in smart phones. Apart from the size of the SIM getting smaller, the amount of storage a SIM could provide, the number of operator profiles a SIM could support and the file systems included in a SIM card have all improved over time. Virtual SIM or eSIM is a new technology to replace the traditional SIM and with remote provisioning it allows user to change the SIM profile remotely over the air. An eSIM that allows interoperability of operator profiles can handle Machine-to-Machine communication in a better way. This paper presents a study of the evolution of SIM with various usage scenarios of eSIM. In addition, it proposes a design for next generation SIM along with the implementation of a security algorithm between a SIM card and Service Provider.

Over the past few years, the use of 18650 form factor lithium-ion (Li-ion) cells have transitioned from primarily commercial applications to consumer/residential use. An evaluation of eight commercially available, circuit protected, 18650 form factor Li-ion cells were performed, with analysis focusing on a residential consumer evaluation of performance. As typical consumer cell usage occurs at a relatively low discharge rate, cells were evaluated between 4.2 V and 2.7 V at C/10, C/5, and C/2 discharge rates. The evaluated cells ranged from &ldquo, high-cost&rdquo, Panasonic, Hixon, Orbtronic, and EastValley cells to &ldquo, low-cost&rdquo, UltraFire (UF) and Eilong cells. Initial discharge comparisons revealed that no cells delivered their nameplate capacity, with a large overstatement of cell capacity occurring for low-cost cells. On average, high-cost cells delivered 92.5% of their advertised capacity, with low-cost cells delivering 20.6% at a C/10 rate. Basing consumer evaluation on a cost per unit capacity and/or cost per unit energy, even with this large overstatement in capacity, low-cost cells still offer an advantage over higher-cost alternatives. The average cost per amp-hour for each cell group ranged from $1.65 to $3.38 for the low-cost and high-cost cell groupings, respectively. Analysis of voltage profiles highlighted two chemistries used in cell production, coinciding with each cell grouping.

Novel concepts in power electronics rely heavily on the availability and processability of new materials and packaging technologies to meet the requirements of increasing performance and reliability at lower form factor, weight and cost. Today’s main technological route for converter modules is still the power die soldered and wire-bonded to a DCB substrate. New applications or semiconductor technologies like e.g. SiC, however, require enhanced thermal management using standard commercial casings within the same, usually very limited thermal budget. This paper is the final of a series of publications dealing with a novel thermal management concept for power electronics enabled by the use of advanced packaging technologies as well as smart handling of power transients, making use of a TEC and a thermal buffer using a low melting BiSn eutectic as phase change material to store excess heat temporarily exploiting the PCM’s enthalpy of fusion. This concept is exemplified on a typical six-pack converter module for industrial applications (4 kW, 1200 Volts) to be integrated into a standard easyPIM casing while being able to cope with overload power pulses. This paper summarises the whole system approach, references back to literature for details finishes the series of papers with the reliability analysis of the buffer technology. Thus, all stages of product development covering design, technology and performance are finally highlighted.

This paper reports on the status of a comprehensive ten-year research and development effort towards Hybrid System-in-Foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion attached on or laminated in a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity or form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave and energy supply components are discussed.

Hardware security plays an important role in the information security field and has gained significant interests from both industry and academic communities. 3D integration technology, which enables ICs to be stacked in the vertical dimension and provides smaller form factor and higher performance, has been extensively researched in the past. From the security and reliability perspectives, 3D integration technology also provides a unique perspective to cope with the security threats occurred in different phases of an IC’s life cycle. In this paper, the advantages and challenges of 3D integration technology have been analyzed from security and reliability perspectives. Furthermore, a novel low cost wet etching based interposer structure was introduced to realize high security packaging of ICs, which owns package level metal shielding network to prevent side channel information leakage and to detect reverse-engineering attack in real time. The thermal and electromagnetic properties of the designed package structure were examined by finite element method and the fabrication process was also systematically discussed.

Deformable inputs offer users the ability to physically manipulate a device for system interaction. We combine flexible electronic technologies with human computer interaction to study how changing the form factor of digital devices can offer new interaction techniques to users. We introduce our research on deformable user interfaces by discussing bend gestures as a source of input, presenting our process to rapidly prototype flexible devices, and demonstrate three deformable user interfaces: bend passwords, bend for mobile games, and bend for vision impaired users. We show how flexible devices and deformable interactions can improve how we interact with our devices.

Wearable technology has great potential in improving the work routines of medical professionals such as nurses and orderlies in the healthcare domain. Although wearable technology such as smartwatches can have a positive impact on the life of both patients and medical professionals, its usage is often not possible due to strict hygiene regulations. In this paper, we investigate the design space for a wearable device to support medical professionals in a hospital context that meets the requirements of the 'Bare Below the Elbows' hygiene policy. We conducted two workshops with eleven medical professionals to elicit requirements and to co-design such a wearable device. Specifically, we aimed to answer questions related to the form factor, mounting options as well as must-have functionalities and features.

Yarn-shaped supercapacitors (YSCs) once integrated into fabrics provide promising energy storage solutions to the increasing demand of wearable and portable electronics. In such device format, however, it is a challenge to achieve outstanding electrochemical performance without compromising flexibility. Here, MXene-based YSCs that exhibit both flexibility and superior energy storage performance by employing a biscrolling approach to create flexible yarns from highly delaminated and pseudocapacitive MXene sheets that are trapped within helical yarn corridors are reported. With specific capacitance and energy and power densities values exceeding those reported for any YSCs, this work illustrates that biscrolled MXene yarns can potentially provide the conformal energy solution for powering electronics beyond just the form factor of flexible YSCs.

In this work, the inkjet printing process is refined to push the capabilities of additive manufacturing up to the W-band (75–110 GHz). The idiosyncrasies of inkjet printing on polymer dielectric materials are fully taken into account, to mitigate the effect of excessive ink spreading which results in RF circuit detuning and performance deterioration. The developed process enables the fabrication of the very first inkjet-printed 90 GHz array on a flexible substrate, featuring 5 elements and a 11.3 dBi gain. High fabrication accuracy has been achieved without using any specialized surface treatment equipment, effectively reducing the baseline equipment for mmWave system fabrication to a single inkjet printer and a convection oven. The proof-of-concept array's form factor will allow integration with beam-forming networks; as an example, a miniaturized 4 × 4 Butler matrix is designed with the achieved fabrication space constraints which opens the way for the first fully-printed beamforming arrays operating in W-band with significant fabrication cost savings.

A smart glass augmented reality (AR) display system is designed with a streamlined form factor featuring an off-axis mirror design. The main component of the combiner optics is in the shape of a regular pair of eyeglasses or sunglasses, with no diffractive gratings, waveguides (lightguides), prisms or Fresnel surfaces involved. High quality see-through performance is achieved with a low-cost combiner that consists of only highly manufacturable reflective surfaces. The 20-degree full field of view of the AR display is centered at about 30 degrees with respect to the center of the ocular vision. Such a design allows the user to have a clear unobscured central field of view. At the same time, the projected image is accessible by moving the eyeball off the central vision. The system is designed with a circular eye box with more than 10 mm in diameter.

We live in an age where enormous amount of data is being collected constantly because of smart phones, ubiquitous presence of sensors and the wide-spread use of social media. Useful and cost-effective analysis of this data is the biggest economic driver for the IT industry. Such analyses are often done in data centers or on cluster of machines because they involve applying sophisticated algorithms to terabyte-size graphs, which are extremely irregular and sparse. We will show how low-power appliances for such analyses can be built using flash storage and hardware accelerators. Such appliances are likely to be 10X cheaper than 16-32 node server clusters and will come in the form factor of an SSD to be plugged into your laptop. This work has been done by Sang-Woo Jun and Andy Wright under my supervision

OSHA reports that in 2016 there were 154 fatalities and 1640 non-fatal injuries from electrical exposure.1 These incidents occurred even at sites with state-of-the art electrical safety programs. Such programs emphasize shutting off sources of electrical energy before exposure, which often occurs during maintenance, installation or other service activities. Nevertheless, exposures still occur, and GE’s research team has been investigating ways of alerting employees to unidentified energized sources. One means of reducing these exposure risks is the use of wearable electronics that would alert the user to energized sources. GE’s Global Research is actively pursuing projects to enhance worker safety with wire-free, lightweight, comfortable devices, and a voltage sensing wristband was developed to provide notification to service and repair workers of the presence of live alternating current circuits. The monitors are not a substitute for personal protective equipment (PPE), but are instead designed to supplement existing training, protocols as a last line and layer of defense. While non-contact voltage sensing devices exist, they do not have the desired sensitivity, comfort, form factor, or "wear and forget" operational mode that is desired for the service workforce. The research team worked closely with the field in specification development and refinement, and in rapidly creating and evaluating prototypes. Flexible circuit, sensor, and band were developed, iterated and field tested in several quick iterative turns. Flexible Hybrid Electronic (FHE) technology elements were used to integrate sensing, communication and computational elements together to create a conformable, bendable wristband. Important lessons were learned about the operating environment, user interface, wearability requirements, sensitivity and repeatability of the devices that drove further design iterations. This band may also serve as a modular platform for further development and enhancement of both the base capabilities and the addition of more diverse sensing capabilities.

As artificial intelligence technologies has been rapidly applied for mobile devices, the demand is increasing to improve the performance of neural network inference at smart phones. However, conventional package-on-package (PoP) for application processors (AP) and DRAM in smart phones is becoming very difficult to deliver high performance due to heat dissipation issues, and limited memory bandwidth. In this paper, we present thermal, electrical performance and form factor comparison of various mobile package structures such as interposer PoP(i-PoP), fan-out PoP(FO-PoP), and fan-out SiP(FOSiP) side-by-side (SbS). In conclusion, fan-out PoP was suitable for form factor-driven mobile sets and fan-out SiP side-by-side was appropriate for performance-driven mobile sets.

Technologies are focusing on empowering consumers with more functionalities into compact assemblies such as ball-grid array (BGA) and Chip Scale Packaging (CSP), offering small form factors to enable high-density semiconductor applications. Reliable performance under drop test conditions is of paramount importance for components targeted for some hand-held applications. Drop testing per JESD22-B111, prescribed by the Joint Electronic Device Engineering Council (JEDEC), is an industrial standard to characterize mechanical reliability of solder joints subject to drop impact under the specified test conditions. This specification was recently revised to JESD22-B111A version, with intent to provide homogenous stress distribution for all components mounted on the newly prescribed PCB layout. The objective of this paper is to assess the impact of these test board changes on drop test performance of solder interconnects and failure modes generated. It is carried out by recording the board dynamic response upon drop impact for test boards with three different form factors. It is complemented well with the Finite Element Modelling (FEM) developed for the studied drop test settings. The investigation is supported by targeted experiments on some prominent package styles. The drop test results show increased characteristic lifetime of solder joints when dropped using the square shaped test board defined by JESD22-B111A as compared to the outstanding studied specifications. This observation is linked to the impact of changing drop impact pulse, PCB form factor and build-up construction on the board dynamics such as resonance frequency modes and PCB deformation.

With a growing call for an increased emphasis on computing in school curricula, there is a need to make computing accessible to a diversity of learners. One potential approach is to extend the use of physical toolkits, which have been found to encourage collaboration, sustained engagement and effective learning in classrooms in general. However, little is known as to whether and how these benefits can be leveraged in special needs schools, where learners have a spectrum of distinct cognitive and social needs. Here, we investigate how introducing a physical toolkit can support learning about computing concepts for special education needs (SEN) students in their classroom. By tracing how the students' interactions-both with the physical toolkit and with each other-unfolded over time, we demonstrate how the design of both the form factor and the learning tasks embedded in a physical toolkit contribute to collaboration, comprehension and engagement when learning in mixed SEN classrooms.

Wearable technologies are increasingly popular, but often abandoned. Given their highly personal nature, aesthetics and form factor play a key role in adoption and continued use, but thus far little work has focused on this. This paper presents a three-part study to better understand the role of aesthetics and personalisation within wearables. We provided 15 participants with customised, low-fidelity, non-functional "activity trackers", based on their own designs, for in the wild evaluation. Our participants' use of these prototypes provided us with insights into their feelings towards their existing commercial devices and their own designs alike. We found that aesthetics plays an important, and currently underappreciated, role in use and continued engagement, particularly when the context of use is considered. We suggest that manufacturers should embrace adaptability and DIY cultures, allowing end-users to customise their wearables and support them in appropriately choosing, and creating their own designs.

In the future electronics, all device components will be connected wirelessly to displays that serve as information input and/or output ports. There is a growing demand of flexible and wearable displays, therefore, for information input/output of the next-generation consumer electronics. Among many kinds of light-emitting devices for these next-generation displays, quantum dot light-emitting diodes (QLEDs) exhibit unique advantages, such as wide color gamut, high color purity, high brightness with low turn-on voltage, and ultrathin form factor. Here, we review the recent progress on flexible QLEDs for the next-generation displays. First, the recent technological advances in device structure engineering, quantum-dot synthesis, and high-resolution full-color patterning are summarized. Then, the various device applications based on cutting-edge quantum dot technologies are described, including flexible white QLEDs, wearable QLEDs, and flexible transparent QLEDs. Finally, we showcase the integration of flexible QLEDs with wearable sensors, micro-controllers, and wireless communication units for the next-generation wearable electronics.

The Extremely Low-Resource Optical Identifier (ELROI) beacon is a concept for a milliwatt optical "license plate" that can provide unique ID numbers for everything that goes into space. Using photon counting to enable extreme background rejection in real time, the ID number can be uniquely identified from the ground in a few minutes, even if the ground station detects only a few photons per second. The ELROI concept has been validated in long-range ground tests, and orbital prototypes are scheduled for launch in 2018 and beyond. We discuss the design and signal characteristics of these prototypes, including a PC-104 form factor unit which was integrated into a CubeSat and is currently scheduled to launch in May 2018, and basic requirements on ground stations for observing them. We encourage others to consider observing our test flights., Submitted to SPIE Defense and Commercial Sensing 2018

Therabot is a robotic therapy support system designed to supplement a therapist and to provide support to patients diagnosed with conditions associated with trauma and adverse events. The system takes on the form factor of a floppy-eared dog which fits in a person»s lap and is designed for patients to provide support and encouragement for home therapy exercises and in counseling.

This paper highlights the packaging related reliability issues in various advanced packaging schemes such as 3-D stacking, interposers, fan-out packaging, and the more recently developed silicon interconnect fabric integration. The need for heterogeneous integration, superior electrical and thermal performance, reduction of form factor and overall system-footprint, and integration of high-density interconnects are the main driving forces behind the development of these advanced packaging techniques. As the packaging and system integration is becoming more complex, the emphasis is mainly on improving the reliability of system-level packaging rather than the individually packaged devices.

Semiconductor oxide-based capacitors may offer a packaging form factor advantage over more convectional discrete capacitors for some systems integration approaches. To show that the technology meets the system-level reliability requirements, a methodology was developed that ties the results of the physics of failure with realistic test requirements in order to demonstrate a high degree of confidence that the final tested assemblies meet those requirements. The work done to develop this approach is reviewed in this paper.

Wearable sensors are widely utilized in human activity monitoring and recognition systems. Not only do these sensors come in different form factors but the software that comes bundled with them also varies from device to device and is constantly evolving. Also, multiple types of sensors on these devices are used to recognize human activity. Owing to the flexible form factor, these devices can also be mounted on a plethora of different positions on the human body. With all the aforementioned variables, it becomes imperative that the quality of data provided by wearable sensors needs to be evaluated. This paper describes an empirical study resulting in evaluating the accuracy of human activity recognition by wearable sensors based on the type of sensor, the physical mounting position of the sensor on the human body, their type of activity being monitored and the type of device being used. The paper further delves into assessing the results of this study. It provides guidelines for designing better wearable sensor systems for human activity recognition.

Heterogeneous integration of different devices by using 3D architectures allows the realization of application specific System in Packages (SiP) with a high functionality in a cost effective way. Enabling building blocks technologies are substrate-, interconnect-, assembly- and device integration technologies to integrate sensors, ASICs, transceiver, memories and passive elements. SiPs based on interposer architectures are very attractive due to system performance improvements and due to optimized form factor achievements on wafer level.

The recent surge in demand for system-in-package (SiP) applications is driven by the rapid development of connected “smart” devices. The versatility and capability of heterogeneous integration for SiP have made it a popular choice of packaging solutions for increased functionality in a smaller package form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller component and greater density. Soldering materials, such as solder paste and flip-chip fluxes, will need to be chosen appropriately in order to form reliable solder joints and maximize production yields for complicated SiP applications. Fine feature solder paste printing for passive component sizes, down to 008004 (0.25 × 0.125mm) and smaller, or wafer level CSP (WLCSP) with small pad designs of less than 100μm in diameter, has become more challenging in SiP assembly. The appropriate choice of solder powder size, rheology of solder paste, and stencil design are crucial to achieve consistency in solder paste printing performance, which includes good printing transfer efficiency, minimal bridging down to 50 μm gap between neighboring pads and at least 8 hours stencil life. Good wetting, graping resistance, and minimal voiding are some of the key attributes of solder paste to consider as well. On the other hand, as technology drives toward finer pitch components, combined with reduced bondline thickness or standoff of flip-chip or other IC packages, makes cleaning flux residue more challenging. The shift towards using semiconductor-grade ultra-low residue no-clean flip-chip fluxes or solder pastes, which eliminates the cleaning process, is therefore the solution for overcoming these challenges. The flux residue left behind after the soldering process is minimal and compatible with the underfill or molding material used in the subsequent process. This paper will address the challenges and discuss basic guidelines in detail with testing results, for selecting appropriate solder pastes and flip-chip fluxes based on different SiP designs and requirements in the packaging industry.

The chapter titled “Vertical GaN Transistors for Power Electronics” takes the reader through the research and development cycle of GaN vertical-device technology, detailing out the three-terminal devices developed over the last decade. Power converters rely on solid state devices featuring diodes and transistors as their basic building blocks. GaN technology is an ever-expanding topic for R&D, proving its potential to solve several challenges in power conversion that cannot be addressed by Si. Medium-voltage (650–900 V) devices using the HEMT configuration have been able to reduce form factor at the system level by driving circuits at higher frequencies (100KHz–1 MHz) and eliminating heat sinks or reducing cooling requirements. Such potentials sparked the interest in GaN device research to address power conversion needs. However, in power conversion the demand of high current (50A and higher) from a single chip for a rated voltage (1KV and higher) is a standard requirement. Particularly when the market is favorable toward electrification of cars and other means of transportations, GaN must expand its scope to provide high power solutions with higher power density compared to Si and even SiC. Vertical devices have been the choice of power device engineers for economic use of the material and maximum use of its physical properties (which allow highest possible blocking field, field mobility, etc.). In this chapter, we discuss vertical transistors first in its normally on form (CAVETs) and then in its normally off design (MOSFET). The advantages and disadvantages are discussed for each type besides describing their operation principles. We have tried to make this chapter scholastic and informative by use of modeling and experimental data for each device we describe. The chapter will help the reader to realize the most recent status of GaN vertical transistors and appreciate its potential in power conversion.

Purpose The purpose of this paper is to demonstrate a novel 3D system-in-package (SiP) approach. This new packaging approach is based on stacked silicon submount technology. As demonstrators, a smart lighting module and a sensor systems were successfully developed by using the fabrication and assembly process described in this paper. Design/methodology/approach The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. This platform consists of silicon submount design and fabrication, module packaging, system assembling and testing and analyzing. Findings In this paper, a smart light emitting diode system and sensor system will be described based on stacked silicon submount and 3D SiP technology. The integrated smart lighting module meets the optical requirements of general lighting applications. The developed SiP design is also implemented into the miniaturization of particular matter sensors and gas sensor detection system. Originality/value SiP has great potential of integrating multiple components into a single compact package, which has potential implementation in intelligent applications.

Optical transceiver needs of hyper-scale data centers have increasing influence on the choice of optical signaling and form factor. Review is made of the industry response to these needs, including standards setting organization (SSO) specifications.

This paper introduces Tacttoo, a feel-through interface for electro-tactile output on the user's skin. Integrated in a temporary tattoo with a thin and conformal form factor, it can be applied on complex body geometries, including the fingertip, and is scalable to various body locations. At less than 35µm in thickness, it is the thinnest tactile interface for wearable computing to date. Our results show that Tacttoo retains the natural tactile acuity similar to bare skin while delivering high-density tactile output. We present the fabrication of customized Tacttoo tattoos using DIY tools and contribute a mechanism for consistent electro-tactile operation on the skin. Moreover, we explore new interactive scenarios that are enabled by Tacttoo. Applications in tactile augmented reality and on-skin interaction benefit from a seamless augmentation of real-world tactile cues with computer-generated stimuli. Applications in virtual reality and private notifications benefit from high-density output in an ergonomic form factor. Results from two psychophysical studies and a technical evaluation demonstrate Tacttoo's functionality, feel-through properties and durability.

This article presents a case study of the user experience of Google Glass when it was initially introduced in 2013. By applying the combined methods of on-line data research, semantic network analysis and field research, it is argued that awkwardness of form factor and use, and failures of Google Glass’s user interface explain the low acceptability of the device. From a methodological perspective that combines big data analysis and qualitative research, this article discusses the user needs and preferences that should inform development of new tech.

With the growing need to pack more functionality into a smaller form factor while providing significant power-performance benefits, future electronics will need fairly disruptive solutions to overcome the mounting limits of Si CMOS scaling. At the core of the hardware innovations will be new process technologies that allow for not only more power-efficient CMOS transistors but also specialized devices to enable new on-chip functionality, for example, sensors, high-speed I/O, optoelectronics, power management, and RF.

Indoor Real-Time Location Systems (RTLS) research identifies Bluetooth Low Energy as one of the technologies that promise an acceptable response to the requirements of the Healthcare environment. In this context, we investigate the latest improvements with Bluetooth 5.0 especially with regards its range when the signal penetrates through different types of multiple partitions. The improvements in Bluetooth technology especially with regards form factor, low energy consumption, and higher speeds make this a viable technology for use in indoor RTLS. Several different venues are used at the University to mimic the Healthcare environment to conduct the experiment. The results indicated an acceptable range through obstacles such glass, drywall partitions and solid brick wall. Future research will investigate methods to determine the position of Bluetooth Low Energy devices for the possible location of patients and assets.

Integrated Fan-Out (InFO) is developed with greater simplicity, based on subtraction in structure, process flow and supply chain management than industry proposed solutions. It achieved un-precedent results compared to others using “additional” structure for functional or yield enhancement. The results include electrical performance, power consumption, thermal resistance, form factor/thickness and cost effectiveness. Greater simplicity continues play critical role for advanced packaging to achieve system PPAC goals.

Data workloads generate heavy IOPS and operate on large amounts of data typically stored in a distributed storage system. Traditionally, storage has been the slowest component of a data intensive system, far slower than the CPU and the network. Though with the arrival of faster, persistent storage in the form of NVMe based solid state drives, the I/O performance has increased dramatically, yet the I/O is still slower than the other components in the system. But with the upcoming byte-addressable, non-volatile memory available in DIMM form factor (NVDIMM), this is no longer true; the CPU and the network might soon become bottlenecks. In this paper, we study the effect of using NVDIMM in a representative distributed storage system, Ceph. Through experiments, we demonstrate drastic increase in CPU and network usage, by adding persistent memory to existing storage software.

With regard to the development trend of smartphone, the smartphone is equipped with high definition display, and a thin and light dimension. The mobile phone is continued to decrease body thickness, and most components should follow the trend, including display panel module, covering panel glass, phone case, battery, camera module, PCB, IC package…etc. In this paper, the fan-out wafer level package (FOWLP) is investigated in mobile application, and compared with traditional package solutions, including package design, structure and electrical performance, and the IC package of application processor (AP) is as the importance of this study. For the application processor (AP) investigation, the thickness of fan-out package on package (FOPoP) is about 35% less than traditional package on package (MAPPoP), and the signal/power integrity of FOPoP is about 15–85% better than MAPPoP. The fan-out wafer level package (FOWLP) is a better solution to be applied in mobile phones, which introduces the advantages of package form factor, high density integration and good performance [1].

Since the inception of optical coherence tomography (OCT), advancements in imaging system design and handheld probes have allowed for numerous advancements in disease diagnostics and characterization of the structural and optical properties of tissue. OCT system developers continue to reduce form factor and cost, while improving imaging performance (speed, resolution, etc.) and flexibility for applicability in a broad range of fields, and nearly every clinical specialty. An extensive array of components to construct customized systems has also become available, with a range of commercial entities that produce high-quality products, from single components to full systems, for clinical and research use. Many advancements in the development of these miniaturized and portable systems can be linked back to a specific challenge in academic research, or a clinical need in medicine or surgery. Handheld OCT systems are discussed and explored for various applications. Handheld systems are discussed in terms of their relative level of portability and form factor, with mention of the supporting technologies and surrounding ecosystem that bolstered their development. Additional insight from our efforts to implement systems in several clinical environments is provided. The trend toward well-designed, efficient, and compact handheld systems paves the way for more widespread adoption of OCT into point-of-care or point-of-procedure applications in both clinical and commercial settings.

Advanced three dimensional (3D) packaging is a key enabler in driving form factor reduction, performance benefits, and package cost reduction, especially in the fast paced mobility and ultraportable consumer electronics segments. The high level of functional integration and the complex package architecture pose a significant challenge for conventional fault isolation (FI) and failure analysis (FA) methods. Innovative FI/FA tools and techniques are required to tackle the technical and throughput challenges. In this paper, the applications of FI and FA techniques such as Electro Optic Terahertz Pulse Reflectometry, 3D x-ray computed tomography, lock-in thermography, and novel physical sample preparation methods to 3D packages with package on package and stacked die with through silicon via configurations are reviewed, along with the key FI and FA challenges.

The energy performance of a building is strongly influenced by its level of solar exposure, in turn affected by the climate, built context, and building morphological characteristics. Since these are typically fixed at the early- design phase, performance assessment methods based on solar considerations at the urban scale are essential to support early decision-making. As the adaptation of the well-developed building performance simulation methods to the urban scale lead to complexity issues, it is of interest to verify whether simpler metrics can act as performance indicators, as is often done at the building level with quantities such as form factor. This paper first presents a review of existing methods that aim at evaluating aspects such as passive heating and photovoltaic potential. We classify each evaluation metric based on its level of complexity, before choosing a representative subset to be further examined. The goal is to test whether simple metrics fulfill their role as performance indicators when applied to neighborhoods. To do so, the selected metrics, including geometrical parameters (e.g. compactness) and solar exposure levels (e.g. annual irradiation), are compared with simulation results (e.g. heating need), taken as reference values. This is done for two sets of designs: six distinct typologies and a large number of variants from a base case typology. Results, which show various levels of correlation between simple metrics and the reference values, highlight the limitations of using any one metric and indicate a need to revise the definition and evaluation metrics of various performance criteria for neighborhood designs.