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Stress transducers play essential roles in diagnostic testing, monitoring, and nondestructive evaluation of many infrastructures. Particularly, 3-D piezoresistive (PR)-based stress sensors would tool up these applications with a high gauge sensing platform. In this article, strain engineering is utilized to develop a 3-D stress sensor where the microfabrication complexity and cost are reduced. Three types of prestrain are exploited for generating three different groups of PR coefficients; thus, a set of linear independent equations is obtained. The independency of these generated equations is verified both analytically and experimentally. A four-point testing is conducted on both chip wafer and flip chip on printed circuit board (PCB) structure to assess experimentally the capability of the strain approach to build a 3-D single polarity rosette. Both the analytical and experimental evaluations show the ability of the developed chip to extract the six stress components in a fully temperature compensation manner.

Purpose This paper aims to assess precise correlations between intermetallic compounds (IMCs) microstructure evolutions and the reliability of micro-joints with a Cu/SAC305solder/Ni structure using thermal shock (TS) tests. Design/methodology/approach This paper uses 200-µm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 60 µm, assembled on substrates with copper (Cu) pads. After assembly, the samples were subjected to air-to-air thermal shock testing from 55 to 125 per cent. The transfer time was less than 5 s, and the dwell time at each temperature extreme was 15 min. To investigate the microstructure evolution and crack growth, two samples were removed from the thermal shock chamber at 0, 400, 1,200, 2,000, 5,800 and 7,000 cycles. Findings The results showed that one (Cu, Ni)6Sn5/(Ni, Cu)3Sn4 dual-layer structure formed at the Ni pad interface of chip side dominates the micro-joints failure. This is because substantial (Ni, Cu)3Sn4 grain boundaries provide a preferential pathway for the catastrophic crack growth. Other IMCs microstructure evolutions that cause the prevalent joints failure as previously reported, i.e. thickened interfacial (Cu, Ni)6Sn5 and Ni3P layer, and coarsened IMCs inside the solder matrix, only contributed to the occurrence of fine cracks. Moreover, the typical interfacial IMCs spalling triggered by thermally induced stress did not take place in this study, showing a positive impact in the micro-joint reliability. Originality/value As sustained trends toward multi-functionality and miniaturization of microelectronic devices, the joints size is required to be constantly scaled down in advanced packages. This arises a fact that the reliability of small-size joints is more sensitive to the IMCs because of their high volume proportion and greatly complicated microstructure evolutions. This paper evaluated precise correlations between IMCs microstructure evolutions and the reliability of micro-joints with a Cu/SAC305solder/Ni structure using TS tests. It found that one (Cu, Ni)6Sn5/(Ni, Cu)3Sn4 dual-layer structure formed at the Ni pad interface dominate the micro-joints failure, whereas other IMCs microstructure evolutions that cause the prevalent joints failure exhibited nearly negligible effects.

Purpose The purpose of this study is to investigate the effect of the adhesive force and density ratio using lattice Boltzmann method (LBM) during underfill process. Design/methodology/approach To deal with complex flow in underfill process, a framework is proposed to improve the lattice Boltzmann equation. The fluid flows with different density ratio and bump arrangement in underfill are simulated by the incorporated Carnahan–Starling (CS) equation of state (EOS). The numerical study conducted by finite volume method (FVM) and experimental results are also presented in each case at the different filling percentage for verification and validation purpose. Findings The numerical result is compared well with those acquired experimentally. Small discrepancy is detected in their flow profile. It was found that the adhesive force between fluid and solid was affected by the density ratio of the fluids and solder bump configuration. LBM has shown better adhesive force effect phenomenon on underfill process compared to FVM. LBM also demonstrated as a better tool to study the fluid flow in the underfill process. Practical implications This study provides a basis and insights into the impact of adhesive force and density ratio to the underfill process that will be advancing the future design of flip chip package. This study also provides superior guidelines, and the knowledge of how adhesive force is affected by flip chip package structure. Originality/value This study proposes the method to predict the adhesive force and density ratio effect for underfill flow in flip chip package. In addition, the proposed method has a good performance in representing the adhesive force during the underfill simulation for its natural physical basic. This study develops understanding of flow problems to attain high reliability for electronic assemblies.

Purpose In line with the recent development of flip-chip reliability and underfill process, this paper aims to comprehensively investigate the effect of different hourglass shape solder joint on underfill encapsulation process by mean of experimental and numerical method. Design/methodology/approach Lattice Boltzmann method (LBM) numerical was used for the three-dimensional simulation of underfill process. The effects of ball grid arrays (BGA) encapsulation process in terms of filling time of the fluid were investigated. Experiments were then carried out to validate the simulation results. Findings Hourglass shape solder joint has shown the shortest filling time for underfill process compared to truncated sphere. The underfill flow obtained from both simulation and experimental results are found to be in good agreement for the BGA model studied. The findings have also shown that the filling time of Hourglass 2 with parabolic shape gives faster filling time compared to the Hourglass 1 with hemisphere angle due to bigger cross-sectional area of void between the solder joints. Practical implications This paper provides reliable insights to the effect of hourglass shape BGA on the encapsulation process that will benefit future development of BGA packages. Originality/value LBM numerical method was implemented in this research to study the flow behaviour of an encapsulation process in term of filling time of hourglass shape BGA. To date, no research has been found to simulate the hourglass shape BGA using LBM.

The coupled thermo-mechanical field analysis of three-dimensional (3D) stacked integrated circuits (ICs) is evaluated by an efficient and accurate simulation strategy that combines equivalent homogenization modeling methodology and sub-modeling technique. The thermal field is first investigated using the proposed approach, and based on which the structural field is also examined through the calculation of warpage. The utilization of sub-modeling method reveals the local temperature and warpage distributions, which is lost or ignored by the conventional homogenization method. To validate the proposed method, the simulation results of a five-layer stacked integrated circuits are compared against true 3D results of the detailed model, where the maximum deviation for temperature and warpage is as low as 1.62% and 4.89%, respectively, which are greatly improved compared to 8.23% and 7.83% using traditional homogenization method. In addition, the total computation time is reduced by 76.7% in contrast to true 3D finite element analysis (FEA) simulation. Furthermore, the impacts of through-silicon-via (TSV) geometries, underfill and μ -bump parameters on the temperature and warpage distributions are also studied to guide the design of 3D ICs with high performance and reliability.

Internet of Things (IoT) accelerated by the rapid progress of 5G is bringing a lot of challenges to semiconductor packaging technologies. In particular, flip-chip bonding technology is strongly required to realize ultrafine-pitch products, such as network, graphic, and artificial intelligence (AI) processors. Thermal compression bonding (TCB) with pre-applied underfill materials, such as nonconductive paste or nonconductive film (NCF), has been expected as one of the effective solutions for these applications for a long time. Nevertheless, the actual availability is still limited due to its high process cost. In other words, innovative breakthrough to achieve reasonable TCB cost is necessary to support the expansion of IoT. So far, some kinds of multiple die bonding processes represented by collective bonding have been proposed and demonstrated with conventional NCFs. However, it is becoming clear that the conventional NCFs optimized as fast cure type are very difficult to have enough processability for the multiple bonding processes due to mismatch between reactivities of the materials and bonding process conditions. That is why the new NCF dedicated to the multiple die bonding processes has been developed in this article. The developed NCF was designed to survive long-time thermal exposure on a bonding stage so that the collective bonding could be completed with reasonable process margin. To achieve target specifications, this article has started with the design of a new resin composition applied to the developed NCF. Then, basic properties required for NCFs, such as thermal stability and electrical insulation, were investigated in feasibility studies. Finally, TCB was demonstrated, and reliable solder joints were formed without any abnormality even after extended thermal exposure on the bonding stage. Moreover, it was found that the developed NCF might have the potential to achieve void-free encapsulation by pressure curing.

The control of thermally induced warpage on electronic packages is an important issue during their fabrication process and assembly. Apart from a commonly used finite-element method and experimental methods for thermally induced warpage analysis of the packages, it still needs a fundamental theory to provide an insight of mechanics to assist and further check the finite-element and experiment-obtained results, especially for critical parameter identification. This article aims to take a close look into the well-known, closed-form Suhir theory for calculating thermally induced deformation of die–substrate assembly and correlate it with a finite-element analysis and further to propose a new Suhir-solution-based theory for predicting the thermal deformation of flip-chip packages. Through this article, the shear-effect region has been found, and its effect on curvature distribution over entire package length and corresponding warpage has been examined in terms of elastic modulus and thickness of underfills. The other parameters such as extended substrate and fillets of underfill are also studied. The limitation and feasibility of the theoretical solution to thermal deformation (warpage) prediction of flip-chip packages are discussed in detail by comparing with the finite-element and moire experimental results in this article.

Defects can result in a failed part and are costly in terms of time and material. This cost is even greater in the context of large-scale additive manufacturing where the objects can be very large. As a result, a great deal of research has focused on defect identification and mitigation. To address defects during object construction, researchers at Oak Ridge National Laboratory’s Manufacturing Demonstration Facility investigated an in-situ control system comprised of two sensors: a thermal camera and laser profilometer. This control system adjusted material flow and build speed to mitigate three types of defects: low layer times, underfill, and overfill. Several test objects were constructed. The control system was found to adjust build parameters to handle low layer times of approximately 15 seconds and height deviations from -100% underfill (the absence of a layer) to 50% overfill. Within two layers, height deviations could be returned to within 10% of the expected layer height. Further, preliminary results suggest the system can compensate for uneven build surfaces.

RF and millimeter-wave designers continue to use wire bonds and flip chip in their designs when bonding chips or multichip systems. Due to electrical and mechanical constraints of wire bonding and flip chip, designers are forced to compensate for mismatched impedances, high loss, or mechanically unreliable interconnects. In this article, we propose microcoaxial cables (MCCs) as an alternative interconnect, specifically, 30–75- $\Omega $ MCCs for signals, and low-inductance MCCs for bias and supply. In addition, each shielded interconnect provides sufficient isolation to prevent electromagnetic interference (EMI) and crosstalk. The in situ fabrication method presented here utilizes only conventional wire bonding and microfabrication techniques, providing a high-feasibility path toward a new interconnect paradigm based on MCCs. Each cable measured consists of a 25.4- $\mu \text{m}$ gold bond wire coated first with a dielectric and then with a 5.0- $\mu \text{m}$ -thick gold shield. MCCs appropriate for signals have a 38- $\mu \text{m}$ -thick Parylene C dielectric and a characteristic impedance of 39– $68~\Omega $ . For the first time, to the best of our knowledge, we introduce low-inductance MCCs, where the dielectrics evaluated are 1.0- $\mu \text{m}$ -thick Parylene C dielectric and 100-nm-thick HfO2. Their inductances are measured to be no more than 140 pH/mm. For 3.5-mm-long wire with a 0.51-mm pitch, the crosstalk is −62 dB at 1 GHz for signal MCCs. Crosstalk increases to −30 dB at 26.5 GHz.

This paper presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched MEMS SiC Device. By optimizing the process, etch depth of 200μm with an etch rate of up to 2μm/min can be achieved for via etching. In addition, a Design Of Experiments (DOE) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the silicon carbide. Hereby, vertical sidewalls with low micro masking, low micro trenching and an etch rate of up to 4 μm / min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200 μm thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50 μm thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments micro electromechanical systems (MEMS) and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC.

Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so that the entire surface of the chip can be covered with bumps for the highest possible input/output (I/O) counts. The present article reviews the manufacturing processes for the fabrication of flip-chip bumps for chip–package interconnection. Various solder bumping technologies used in high-volume production include evaporation, solder paste screening and electroplating. Evaporation process produces highly reliable bumps, but it is extremely expensive and is limited to lead or lead-rich solders. Solder paste screening is cost-effective, but issues related to excessive void formation limits the process to low-end products. On the other hand, electrochemical fabrication of flip-chip bumps is an extremely selective and efficient process, which is extendible to finer pitch, larger wafers and a variety of solder compositions, including lead-free alloys. Electrochemically fabricated copper pillar bumps offer fine pitch capabilities with excellent electromigration performance. Due to these virtues, the copper pillar bumping technology is emerging as a lead-free bumping technology option for high-performance electronic packaging.

Accelerating progress in printed electronics technology transforms the future of the manufacturing process in industrial applications, consumer electronics, and healthcare products. However, real-life applications demand for circuits and systems that are robust and can stay functional under strong and frequent mechanical deformations. Herein, both empirical and analytical approaches to gain insight on the reliability of ultrathin bare dies on soft and highly stretchable printed circuits are used. To this end, a set of conductive ink and adhesive variants are used to develop a stretchable wireless temperature logger as the test device. The electromechanical performance of the conductive inks is first verified through the screening tests and the most suitable candidates are selected to use with different anisotropic conductive adhesives (ACAs) for chip bonding process. The performance of the test devices (per ink–adhesive combination) is tested through cyclic elongation of 60 samples to provide statistical results. Different failure modes are visualized through cross-sectional images using broad ion beam (BIB) milling and scanning electron microscopy (SEM). The findings, herein, recognize pad delamination, air voids at the chip-to-substrate interface, stiffness of the conductive adhesives, and bonding parameters (pressure and temperature) as the key contributors to the contact failures in the chip assembly. publishedVersion

Recent advances in the micro-electronics industry have increased the demand for smaller and more compact package devices with higher performance. This paper presents an analytical multiparametric design optimization approach for the miniaturization of flip-chip package, while considering the filling time of the subsequent underfill encapsulation process. The design optimization approach was based on the latest regional segregation-based analytical filling time model. Numerical simulation was conducted to verify the governed analytical model. The discrepancies in the filling times are less than 9.9%, and the predicted critical bump pitch has a low deviation of 4.1%, affirming that both the analytical and numerical models were in great consensus. The variation effects of bump pitch, gap height, and contact angle on the filling time were analyzed and discussed thoroughly. Both the critical bump pitch and the critical gap height were computed and fitted into respective empirical equations. Subsequently, a new multiparametric design optimization approach based on the thresholding and criticality of underfill parameters was proposed to determine the optimum parameters that yield to the most compact flip-chip package with acceptable low filling time during the encapsulation process. Lastly, this proposed optimization technique was tested on the four flip-chips used in a previously published underfill experiment.

This paper presents a new approach to formulating an analytical model for the underfill process in flip-chip packaging to predict the flow front and the filling time. The new approach is based on the concept of surface energy along with the energy conservation principle. This approach avoids the need of modeling the flow path to predict the flow front and the filling time, and thus it is suitable to different configurations of solder bumps, including different shapes and arrangements of solder bumps in flip-chip packaging. An experiment along with the computational fluid dynamics simulation was performed based on a proprietarily developed testbed to verify the effectiveness of this approach. Both the experimental and simulation results show that the proposed approach along with its model is accurate for flip-chip packages with different configurations besides the configuration of a regular triangle arrangement of solder bumps and a spherical shape of the solder bump.

This work proposes the use of integrated high-power InGaN/GaN multiple-quantum-well flip-chip blue micro light-emitting diode (μ-LED) arrays on an AlGaN/GaN-based heterojunction field-effect transistor (HFET), also known as a high electron mobility transistor (HEMT), for various applications: underwater wireless optical communication (UWOC) and smart lighting. Therefore, we demonstrate high-power μ-LED-on-HEMT arrays that consist of 32 × 32 pixelated μ-LED arrays and 32 × 32 pixelated HEMT arrays and that are interconnected by a solder bump bonding technique. Each pixel of the μ-LED arrays emits light in the HEMT on-state. The threshold voltage, the off-state leakage current, and the drain current of the HEMT arrays are −4.6 V, &lt, ~1.1 × 10−9 A at gate-to-source voltage (VGS) = −10 V, and 21 mA at VGS = 4 V, respectively. At 12 mA, the forward voltage and the light output power (LOP) of μ-LED arrays are ~4.05 V and ~3.5 mW, respectively. The LOP of the integrated μ-LED-on-HEMT arrays increases from 0 to ~4 mW as the VGS increases from −6 to 4 V at VDD = 10 V. Each pixel of the integrated μ-LEDs exhibits a modulated high LOP at a peak wavelength of ~450 nm, showing their potential as candidates for use in UWOC.

This presentation covers the basic physics needed to effectively apply backside IC analysis techniques to flip-chip packaged die. It describes the principles of light transmission through silicon and the factors that influence optical image formation from the backside of the wafer or die. It also provides information on the tools and techniques used to expose surfaces, regions, and features of interest for analysis. It describes the steps involved in CNC milling, mechanical grinding and polishing, reactive ion etching (RIE), laser microchemical (LMC) etching, and milling and etching by focused ion beam (FIB). It explains where and how each technique is used and quantifies the capabilities of different combinations of methods.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

Epoxy die attach is widely used in microcircuit assembly and enjoys advantages such as ease of deposition, fast curing, reworkability, and non-toxicity. These qualities also make it suitable for automated mass production. However, this method falls short when high placement accuracy is desired as the die can shift on uncured epoxy leading to die displacement from its original location. Gold to gold face-up bonding is another method utilized in microelectronics packaging given its proven bonding reliability and high placement accuracy for small devices. Nevertheless, it is difficult to achieve a reliable bond using this method for relatively larger devices. The nonplanarity of the bonding collet or the variation in the height of the gold bumps results in a tilted die attach and/or a weak bond between the die and the substrate. Moreover, CTE (Coefficient of Thermal Expansion) mismatch between the die, the gold bumps, and/or the substrate leads to bond failure due to temperature fatigue. This paper discusses a hybrid method to take advantage of the strengths of both methods mentioned above, culminating in a reliable process with high XYZ placement accuracy. To apply this method, epoxy is first dispensed on a gold-plated substrate. Using a flip chip machine, samples with plated gold bumps on their ground side are then placed on the substrate. The gold bumps are mainly used as targets and stand-offs to improve the placement accuracy and to control epoxy glue-line thickness. The force applied on the die, the time the force is applied, and the substrate temperature are controlled for optimum die attach. Moreover, along with the force applied by the vacuum tip, epoxy is partially cured on the flip chip machine heated stage before it is moved to an oven to complete the cure process. Die shear test results before and after temperature conditioning are compared with standard epoxy die attach and gold to gold face-up bonding for identical samples and the advantages are discussed.

This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.

Integration of InP laser sources is a key enabling technology for Silicon Photonics and requires customised InP chips that meet the mechanical and optical requirements of a diverse range of Si Photonics architectures. The Sivers Photonics InP100 Platform is a common design and manufacturing framework for InP photonics devices that uses established process modules to produce a broad range of device types on 100mm wafers. This approach reduces cycle times for the development of customised device designs, has proven reliability, and is scalable to high volume manufacturing. The InP100 platform enables integration of customised InP chips with Si Photonics chips (e.g. via flip chip bonding), for applications for applications such as LIDAR, sensing and communications.

Cancer cell–immune cell hybrids and cancer immunotherapy have attracted much attention in recent years. The design of efficient cell pairing and fusion chips for hybridoma generation has been, subsequently, a subject of great interest. Here, we report a three-layered integrated Microfluidic Flip-Chip (MFC) consisting of a thin through-hole membrane sandwiched between a mirrored array of microfluidic channels and saw-tooth shaped titanium electrodes on the glass. We discuss the design and operation of MFC and show its applicability for cell fusion. The proposed device combines passive hydrodynamic phenomenon and gravitational sedimentation, which allows the transportation and trapping of homotypic and heterotypic cells in large numbers with pairing efficiencies of 75~78% and fusion efficiencies of 73%. Additionally, we also report properties of fused cells from cell biology perspectives, including combined fluorescence-labeled intracellular materials from THP1 and A549, mixed cell morphology, and cell viability. The MFC can be tuned for pairing and fusion of cells with a similar protocol for different cell types. The MFC can be easily disconnected from the test setup for further analysis.

How to effectively and accurately evaluate the reliability of the design, structure, material and process of flip-chip packaging devices in mass production has always been a hot topic in the industry. Currently, the destructive physical analysis (DPA) on high-reliability conventional packaging devices worldwide is carried out mainly based on the Methods of Destructive Physical Analysis for Military Electronic Components (GJB4027) or the Destructive Physical Analysis for Electronic, Electromagnetic, and Electromechanical Parts (MIL-STD-1580). However, the structure and process of flip-chip packaging devices are significantly different from those of traditional packaging devices, so traditional evaluation items are unable to effectively evaluate the reliability of flip-chip packaging devices. In this paper, typical ceramic and plastic encapsulated flip-chip packaging devices are chosen for study. The structural feature and the reliability weaknesses of flip-chip packaging devices are identified. Moreover, highly comprehensive DPA methods for flip-chip packaged devices with high applicability and efficiency are proposed by combining the typical failure modes of flip-chip packaging devices, which were verified by the examples. Herein, the reliability of key structural units such as flip-chip covers, bumps, underfill, substrates and solder balls can be effectively assessed by the new DPA method, providing a basis and assistance for revisions of advanced packaging device standards and destructive physical analysis.

Underfill voids have been one of the major reliability concerns in flip-chip packaging specially in a fine pitch. Therefore, monitoring of process based root causes of the void formation is significantly important. In this study, 7.5×7.5 Si die was bonded on two 17 mm *17 mm2 substrates viz. S1 and S2 to prepare a-ISO µm pitch flip chip package. Effect of two process parameters such as plasma and staging time was observed on void formations. Plasma cleaning of both substrate was done for 1 minute. Before underfill dispensing, staging of units was performed for 4, 6 and 8 hours, and void formation was observed using confocal scanning acoustic microscopy (C-SAM). Differences in void formations among S1 and S2 are related to the change in surface of solder mask. Therefore, optical pro filer was used to detect the changes in surface roughness of solder mask with plasma and staging time. Whereas, formation of different chemical bonds before and after plasma was analyzed using x-ray photoelectron spectroscopy (XPS). Also, water contact angle on S1 and S2 was evaluated before and after plasma cleaning. As a result of this study, percentage unit failure was increased with increasing staging time. This is attributed to changes in surface roughness, and amount of O-C=O, C-O, C-C bonds on solder mask. Contact angle on secondary non-bump area may or may not be representative of underfill wettability due to surface roughness difference with bump area on one substrate supplier but similar surface roughness between bump and non-bump area on another substrate supplier.

In this study, three kinds of underfill materials were used to investigate the enhancement of silane coupling agents on the adhesive strength of the underfill and the silicon substrate undergoing boiling water soaking. Adhesion properties between the underfill and the silicon were evaluated by shearing test. The fracture interfaces of the shearing tests are observed by SEM. The results show that the adhesive strength between the silicon and the underfill decreases significantly without silanes, and the bonding between the resin and the filler becomes loose by hydrothermal aging. Underfill containing aminosilane has higher water resistance, which can improve the adhesive strength of underfill, and can help to strengthen the bonding between underfill and filler after hydrothermal aging.

In this work, finite element analysis and failure analysis are performed to analyze the crack failure in flip chip quad flat no-lead (Flip Chip QFN). Although a QFN is a traditional package, the reliability requirements of Flip Chip QFN in power applications have become strict and more and more challenging to meet. This paper elaborates the thermomechanical reliability challenges of Flip Chip QFN associated with its unique package construction features, and investigate the failure mechanisms of package cracking issue found in thermal cycling test. Parametric analysis is conducted to determine the optimal design in the Flip Chip QFN to combat crack failure. This investigation can help improve the product reliability by preventing crack failures in the Flip Chip QFN package.

In large size package, high temperature affects the stability, reliability and service life of electronic components. The thermal interface material (TIM) plays an important role of effectively enhancing the heat transfer in Flip Chip Ball Grid Array (FCBGA) package; therefore reliability of TIM is indispensable especially when the package device needs to withstand wide high and low temperature periods. In this paper, we conduct a detailed analysis of TIM's reliability in large-size FCBGA package by simulating the stress and strain of TIM layer with the finite element software ABAQUS. The stress of TIM in the package is complex and can be affected by multiple factors such as device structure, material parameters, etc. It is necessary to check the model structure and material parameters to correctly understand the stress of TIM in FCBGA. The statistics method is adopted for analyzing the influence of various parameters.

The continuous demand for high-speed, low-power consumption and multi-functionality of new generation electronic products has led to an exponential increase for high-yield and high-reliability packaging technologies, which has promoted the application of the 7nm node process technology to promote higher I/Os and smaller bump pitches. The advantages of copper pillar bump, which was widely used in high-density packaging, include fine pitch, high strength, low interconnection resistance, excellent electromigration performance, and lead-free packaging solutions. The low-k/ultra-low-k (LK/ULK) material medium used in back-end of the line (BEOL) can effectively reduce the parasitic capacitance without reducing the wiring density. Therefore, to improve thermomechanical and electrical performance, chips with a 42nm node and beyond usually integrate LK/ULK structure and metal line in BEOL. However, the encapsulation of the chip exceeding the 28nm node would lead to a sharp increment in the number of BEOL interconnection layers (vertical) and high-density copper traces (horizontal). The thermomechanical stress caused by the mismatch of the CTE of wafer and packaging material may cause LK/ULK delamination, bump cracks, and UBM peeling failures. Therefore, the accurate analysis and calculation of the thermomechanical stress in the film structure has always been the focus of engineering and academia. The integrity of the bumps and microstructure of BEOL can be evaluated effectively by shear test method, which was suitable for structural inspection. In this work, the shear test simulation was applied for single bump to characterize the failures of BEOL structures, e.g., fractures of ULK/LK. Owing to the fragile characteristics of LK/ULK, BEOL was susceptible to external loads. When the copper pillar bumps above BEOL were subjected to shearing forces caused by thermal mismatch, the failure would occur in some microstructures within BEOL, especially in ULK/LK interfaces. Because the bumps near die corner suffered a critical shear load, so the single bump of the aforementioned area was investigated by a shear simulation model. Studies had shown that the shear rate had less effect on the maximum shear stress, but the increment of the shear height brought about more fractures of LK, which showed that reducing the bump height helps to reduce the risk of BEOL damage under thermomechanical loads. Generally, the shear test of copper pillar bumps could effectively evaluate the strength and adhesion of the BEOL film interfaces. As an early evaluation under extreme conditions, this simulation was designed to check the integrity of ULK/LK stack film and the strength of the bump structure through the chip package interaction without underfill protection and finally find the optimal packaging solution.

Chiplet becomes a key technology to continue Moore's law, but the interconnection between dies is one of its difficulties. Bumpless interconnects technology reduces the impedance of the TSV interconnects with no bumps and Ultra-thinning of wafers enables maintain total height while supporting more layer counts. Instead of bump, small TSV passes through substrate and underfill whose thickness are comparable. Considering this structural feature, the equivalent-circuit model of bumpless TSV is proposed and the analytical expressions of proposed model are studied. Up to 100 GHz, the maximum error of S11 and S21 between proposed model and the physical model built in HFSS less than 3% and 9%, which demonstrates the accuracy of equivalent-circuit model. For the structural feature of bumpless TSV, the effect of thickness of underfill and silicon substrate that varies with TSV s height are analyzed respectively. The two conditions are studied in the frequency domain analysis and the electrical behavior differing from traditional TSV is found while scalability is verified.

Compared with continuous node scaling in a two-dimensional (2D) plane, advanced three-dimensional (3D) integration finds a new pathway to expand Moore's Law in the vertical direction. The essence of advanced 3D integration technology relies on the dense vertical interconnection, and state-of-the-art metal/oxide hybrid bonding provides such an ideal fine-pitch structure (≤ 1 µm) by eliminating microbump and underfill. Of the various hybrid bonding platform, Cu/SiO 2 hybrid bonding structure is the most promising candidate due to the excellent electrical and mechanical properties of Cu and SiO 2 , respectively. However, the feasible Cu/SiO 2 hybrid bonding technology often requires high temperature (-400°C) currently, which is not desirable for temperature-sensitive chips. Here, we develop a novel two-step cooperative surface activation method to overcome this bottleneck. Based on the combination of plasma activation and acid treatment of this cooperative surface activation, the atomic smooth Cu and SiO 2 surface with hydrophilic layers were obtained, and the strong homogeneous bonding of Cu-Cu and SiO 2 -SiO 2 was realized at 200°C. Eventually, the Cu/SiO 2 hybrid bonding device was successfully achieved, which void-free and atomically interconnected Cu-Cu, SiO 2 -SiO 2 , and even Cu-SiO 2 interfaces were obtained simultaneously. This hybrid bonding structure realized by cooperative surface activation brings unprecedented 3D integration feasibility and flexibility.

Silicon interposer is an effective way to realize the various kinds of chips integration. This study is based on the characteristics of traditional underfill, by designing a reasonable bump structure, the coplanarity difference in assembly process can be effectively contained. And the key parameters are analyzed, the optimized aseembly scheme is obtained. The product reliability verification results meet the requirement.

With the advent of the 5G era, power devices and telecom equipment require small form factor and excellent thermal performance. Flip-chip Land Grid Array (FC-LGA) is rapidly becoming the package choice for those devices, because of its low RDS (ON) and high frequency operation. However, it also brings great challenges to reliability design. Large number of flip chip solder joints between die and substrate lead to a more rigid package body, which will accumulate strong thermomechanical stress under alternating temperature and so inevitably trigger package reliability issues. Excessive warpage and body crack will occur if without appropriate package design consideration. In this study, the thermo-mechanical behaviors of FC-LGA were investigated by finite element simulation under different TCC conditions. Due to the complexity of the LGA substrate, the simulation with detail substrate model in use will incur expensive computation. This work proposed a simplification method considering a substrate of complicated structure as an equivalent anisotropic volume. With simulation models simplified, DoE study was performed to investigate the influence of packaging materials and geometry on the thermo-mechanical reliability of FC-LGA packages in high efficiency. A higher die-to-EMC thickness ratio will result in a more severe package convex warpage, while using a thinner die and a thicker EMC layer can prevent package body from cracking during heating or cooling processes. Besides packaging geometry, the influence of substrate layouts and EMC mechanical properties were also studied to find the optimal packaging design to mitigate the risks of excessive package warpage and body crack.

With the development of microelectronics packaging technology, the interconnection size of chip packaging has gradually decreased to 10μm.ACA (anisotropic conductive adhesive) packaging technology has become one of the key technologies to realize this trend. In this paper, we analyze how to minimize the failure probability of ACA in the case of narrow-pitch chip packaging. The failure mode of ACA can be divided into two kinds: opening failure in the conductivity direction and bridging failure in the insulation direction. Before the bond, it is assumed that the conductive particles obey the Poisson distribution. After the bond, considering the volume curing rate of ACA, the failure probability was calculated by using the probability theory and the improved box model. The prediction model of overall failure for the ACA interconnection of narrow-spacing chips was established. When the pitch is constant, the overall failure probability of pad is evaluated as a function of the optimal diameter and volume fraction of the particles, as well as how the distance between pad and the length of pad should be distributed. This will be useful to optimize the size of the bumps and to choose more suitable ACA material.

Force sensing and control functions are very important for flip chip bonding systems for the reason of purchasing high-quality chip interconnection. But it is regrettable that, using the existing commercial technology and equipment, the bonding interconnection procedure is hard to be performed perfectly, specifically in the aspects of efficiency, accuracy and quality. There are many processes involved in the bonding interconnection procedure, so as to say, we need to take as far as possible every step and aspect into consideration. This paper proposed a highspeed flip-chip bonding system with force control, which can make the chips after alignment be bonded on substrate well as soon as possible. In the first place, benefited from the work of our predecessors, the active soft-landing (ASL) interconnection is realized by using the advantages of the monolithic force integrated flexible bonding device. However, the adopted flexure bonder is not enough to satisfy the high-efficiency flip-chip bonding requirement. Because the lightly-damping second-order spring system characteristic caused by the force detective part of the adopted flexure bonder. Secondly, based on the flip-chip bonding process, a flexure-based switch is designed to change the unidirectional stiffness of the bonder with the property of force detection for the purpose of reducing the vibration caused by the linear motor braking in the process. Thirdly, a novel closed-loop control strategy which can accommodate the requirements of position and force, namely hybrid position/force closed-loop (HPFC) control, with integrator composed of inertial filter (ICIF) is proposed to realize the high-efficiency force control under high-dynamic working conditions. By adopting these methods above, the bonding system can go through each step of chip bonding after alignment fleetest, and provide high-quality chip interconnection at the same time.

This paper presents a new 3D heterogeneous integration scheme for inertial Micro-system, where a TSV interposer with a cavity is used to separate two aligned TSV interposers that are mounted with inertial MEMS (Micro Electro-Mechanical System) devices, ASIC (Application Specific Integrated Circuit) chips, and passive components receptively. A finite element simulation method that uses equivalent elements and sub-model methods is developed to do design for reliability in Thermal Cycling Test (TCT). Comparing with the normal simulation method, an agreement is obtained in the stress distribution in the MEMS chips, TSVs and micro bumps. In the meantime, the simplified simulation method provides a competitive accuracy, the difference is 0.88% in the maximum deformation of the whole model between the two methods, the difference is 0.41% in the maximum deformation of the TSV and 0.65% in the micro bump at the most dangerous position. Base on this simplified simulation method, a 3D heterogeneous inertial micro-system is analyzed and optimized. The design of ladder TSV with the usage of underfill and gold balls is selected. The simulation results also showed that RDL (Redistribution Layer) can make significant influence on the stress distribution in the systems. If considering RDL, the maximum stress inside the micro bump at the most dangerous location increases by 62.79% while the max stress in TSV decreases by 14.03%, which means that stress optimization should also be carried out after designing the RDL layout.

As the filler between the flip chip and lid, thermal interface material (TIM1) plays a role in heat dissipation to maintain the good performance of chips, lower power during operation. However, as the performance of the device itself continues to improve, in order to maintain reliability, the design demands for packaging materials such as TIM1 are increasing accordingly. Through the observation and analysis of TIM1 after working for a long time, the failure of the material is often due to the separation between the TIM1 and the chip or lid, which indicates that the interface interaction of the designed TIM1, that is, the adhesion is weak. Such problems can lead to a huge thermal resistance so that the thermal performance of TIM1 will be affected. In addition to the thermal resistance resulted from material failure, the contact thermal resistance of TIMl also can defeat its ability of thermal transport. Herein, the adhesion and contact thermal resistance of TIM1 are studied. In order to learn the term of contact thermal resistance, two types thermal testing method, laser flash and photo-thermal radiation are proposed. The research result shows that the adhesion has negative correlation with contact thermal resistance, two proposed method can work for the contact thermal resistance measurement. A method is probably to be used to improve the quality of TIM1 that is introducing adhesion promoter into it to enhance the adhesion at interface and defeat contact thermal resistance simultaneously.

This paper discusses some of the challenges encountered when moving from a SIP package to Hybrid package technology with combination of flip Chip (controller die) and wire bonding (NAND die) inside one package, where one design has a Hybrid-side by side (Hybrid-SBS) SIP package structure. Due to controller and NAND die size growth with more IOs and capacity, Hybrid-SBS SIP package requires a form-factor change. Thus, Hybrid-Embedded SIP Package structure maybe more suitable for next generation SIP package. In this paper, Hybrid-Embedded SIP Package structure is introduced and challenges of this package structure and package routing are discussed.

With the continuous and rapid development of microelectronics technology, the power consumption of microelectronic device increased with the improvement of performance. The increasing power consumption may cause thermal-induced failures and greatly affect the reliability of the device. To avoid this problem, heat sinks and thermal interface materials (TIMs) are used for effective thermal management. The TIM1 is used inside the device between the chip and the metal lid to eliminate the interstitial air gaps from the interface by conforming to the topography of the surfaces in contact. However, in practical application, TIM1might be affected by thermal-induced deformation, resulting in the change of bond line thickness (BLT), loss of corner areas, and increase of interface thermal resistance, which may have a significant impact on the heat dissipation in return. In this paper, the effect of TIM1 on the junction temperature of chip in a flip-chip structure with heat sink and fan are systematically investigated using computational fluid dynamics (CFD) method. The temperature profile is obtained and the heat transfer in the out-of-plane and in-plane directions are analyzed. The effect of reduced in TIM1 coverage, warpage-induced change in bond-line-thickness (BLT) and contact resistance are discussed in detail.