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In the last few decades, technology advancements have paved the way for the creation of intelligent and autonomous systems that utilize complex calculations which are both time‐consuming and central processing unit intensive. As a consequence, parallel processing systems are gaining popularity to enhance overall computer performance. Programmers should be able to efficiently utilize available hardware resources with parallelization in an ideal world. Through the automatic parallelization of sequential code, multithreading can be executed without extra supervision. However, a wide range of software dependencies prevents this from being feasible. An architectural framework for speculative parallelization along with an efficient memory analysis and computational algorithms for the code generation are proposed that can provide optimal performance. Furthermore, a suitable support of hardware design as a runtime library to the proposed architectural framework is presented which can be used to recover misspeculated results during execution to minimize speculative parallelism overhead. The implementation makes use of the Low‐Level Virtual Machine compiler infrastructure and is tested on numerous benchmarks, thus making it highly scalable in terms of programming languages and architectures. According to our experimental results, there is significant potential for speedup increase. In comparison to the overall function speedup, that is, geomean speedup of 5.2× approximately when using the proposed architecture without hardware support, the proposed architectural framework and algorithm with hardware support give an average geomean speedup of 7.0× approximately on the given benchmark which is written in C/C++. [ABSTRACT FROM AUTHOR]

Surface rupturing data from the historical earthquakes is used for obtaining empirical regression parameters for fault displacement hazard assessment. This paper represents an additional compilation and analysis effort, extending the first version of the SUrface Ruptures due to Earthquake (SURE) database. This new release contains slip measurements and mapped surface rupture traces of 50 surface rupturing earthquakes of reverse, normal, and strike-slip kinematics occurred all over the world between 1872 and 2019. As a novelty, a ranking scheme of the rupture features is applied to all the traces and slip measurements in the database. Fault ranking introduces geology as a primary analysis tool and allows the end user to obtain regression parameters suitable for the specific geological conditions at the site of interest. SURE 2.0 dataset consists of a table containing the background information about each earthquake, a table containing the slip measurement data of each event, and a joint shapefile containing all the surface rupture traces of the events in the database. Measurement(s) Surface rupturing due to earthquakes Technology Type(s) georeferencing field observation data [ABSTRACT FROM AUTHOR]

Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems-on-Chip integrate many different hardware components which require a reliable and scalable verification environment. The effort to set up such environments has increased as well and plays a significant role in digital design projects, taking more than 50% of the total project time. Several solutions have been developed with the goal of automating this task, integrating various steps of the Very Large Scale Integration design flow, but without addressing the exploration of the design space on both the software and hardware sides. Early in the co-design phase, designers break down the system into hardware and software parts taking into account different choices to explore the design space. This work describes the use of a framework for automating the verification of such choices, considering both hardware and software development flows. The framework automates compilation of software, cycle-true simulations and analyses on synthesised netlists. It accelerates the design space exploration exploiting the GNU Make tool, and we focus on ensuring consistency of results and providing a mechanism to obtain reproducibility of the design flow. In design teams, the last feature increases cooperation and knowledge sharing from single expert to the whole team. Using flow recipes, designers can configure various third-party tools integrated into the modular structure of the framework, and make workflow execution customisable. We demonstrate how the developed framework can be used to speed up the setup of the evaluation flow of an Elliptic-Curve-Cryptography accelerator, performing post-synthesis analyses. The framework can be easily configured taking approximately 30 min, instead of few days, to build up an environment to assess the accelerator performance and its resistance to simple power analysis side-channel attacks. [ABSTRACT FROM AUTHOR]

Compiler optimizations can be functionally correct but not secure. In this work, we attempt to quantify the information leakage in a program for the security verification of compiler optimizations. Our work has the following contributions. We demonstrate that static taint analysis is applicable for security verification of compile optimizations. We develop a completely automated approach for quantifying the information leak in a program in the context of compiler optimizations. Our method avoids many false-positives scenarios due to implicit flow. It can handle leaks in a loop and propagates leaks over paths using the leak propagation vector. With our quantification parameters, we verify the relative security of source and transformed programs considering the optimizations phase of a compiler as a black box. Our experimental evaluations on benchmarks for various compiler optimizations in SPARK show that the SPARK compiler is actually leaky. [ABSTRACT FROM AUTHOR]

Modern reduced instruction set computer processors are based on a load/store architecture, where all computations are performed on register operands. Compilers therefore allocate registers based on demand, and when occupancy is at maximum, register contents are spilled onto the stack and then retrieved later as data is needed. This phenomenon has security implications that cannot be ignored, as data on the stack is subject to well-known memory corruption attacks. Moreover, works presented so far are mainly targeting protection of pointers to code (e.g., return addresses), but are ineffective for protecting other context data in the stack. This article presents a security solution for spilled registers, generalizing the use of ARM pointer authentication (PA) for this purpose. The protection is enforced by the LLVM compiler via additional compiler passes and modifications. The solution provides guarantees for both integrity and confidentiality protection, and also addressing reuse attack problems associated with PA usage. Experimental data collected demonstrates the effectiveness of the solution against corruption and eavesdropping. We test our solution using SPEC CPU 2017, which confirms the functional viability of our solution. Additionally, we expose real-world performance overhead metrics of our protection design on a ARM-PA-enabled processor. [ABSTRACT FROM AUTHOR]

Motivation: The subdivision of the Earth's terrestrial surface into different biomes, ecozones, bio‐climatic realms or other large ecological land units is an essential reference for global biogeographical and ecological studies. Various classification schemes exist. These differ significantly in terms of the considered criteria for classification and the underlying methodology of class assignments. Evident divergences between global biome concepts are elusive, weakening hereon based analyses and assumptions. Compilation and standardization are essential for obtaining a framework that enables the comparison of different products. To address this need, we created a catalogue of standardized categorial biome maps comprising 31 different global products based on various methodological approaches. These products were processed individually to facilitate their use in large‐scale biogeographical and ecological analyses. Main types of variables contained: We provide a unified RasterStack containing 31 terrestrial biome and land‐cover classifications in different layers. Additional ancillary and processing information is allocated. Spatial location and grain: Global, 10 km × 10 km grain size in equal‐area Mollweide projection. Major taxa and level of measurement: Biomes, ecozones, bio‐climatic zones, and ecological land units. Software format: GeoTiff. [ABSTRACT FROM AUTHOR]

Dental morphology (DM) is the first introduction of dental graduates towards the identification of tooth; hence it is an important component of the dental curriculum. Traditionally, it is taught by manual carving of wax blocks, but the limitations of this method have been highlighted. There is a need to adopt innovative teaching methodologies to invigorate the concepts of dental anatomy (DA) and reduce the stress in teaching and learning with a proposal in standardization of training methodologies worldwide. Methods: A three-phased project was designed with an aim to collect global data related to teaching dental morphology within the dental curriculum. One dental professional actively involved in university teaching of DM subject was invited from 11 countries. The present study involved compilation of data from phase 1 questionnaire responses, followed by its discussion and analysis, and generation of preliminary report. Results: It is universally acknowledged that acquiring dental morphology knowledge by dentists is a prerequisite before they commence clinical practice. Our data points that no uniformity in DA course modules exists throughout the world and globally the subject requires curriculum redesigning. Conclusions: Consensus should be achieved amongst academicians in DM teaching and learning context. Innovative and standardized DM modules with component of computer-based and remote learning techniques should also be introduced. [ABSTRACT FROM AUTHOR]

Deep neural networks (DNNs) are increasingly deployed in various image recognition and natural language processing applications. The continuous demand for accuracy and high performance has led to innovations in DNN design and a proliferation of new operators. However, existing DNN training frameworks such as PyTorch and TensorFlow only support a limited range of operators and rely on hand-optimized libraries to provide efficient implementations for these operators. To evaluate novel neural networks with new operators, the programmers have to either replace the holistic new operators with existing operators or provide low-level implementations manually. Therefore, a critical requirement for DNN training frameworks is to provide high-performance implementations for the neural networks containing new operators automatically in the absence of efficient library support. In this article, we introduce NeoFlow, which is a flexible framework for enabling efficient compilation for high-performance DNN training. NeoFlow allows the programmers to directly write customized expressions as new operators to be mapped to graph representation and low-level implementations automatically, providing both high programming productivity and high performance. First, NeoFlow provides expression-based automatic differentiation to support customized model definitions with new operators. Then, NeoFlow proposes an efficient compilation system that partitions the neural network graph into subgraphs, explores optimized schedules, and generates high-performance libraries for subgraphs automatically. Finally, NeoFlow develops an efficient runtime system to combine the compilation and training as a whole by overlapping their execution. In the experiments, we examine the numerical accuracy and performance of NeoFlow. The results show that NeoFlow can achieve similar or even better performance at the operator and whole graph level for DNNs compared to deep learning frameworks. Especially, for novel networks training, the geometric mean speedups of NeoFlow to PyTorch, TensorFlow, and CuDNN are 3.16X, 2.43X, and 1.92X, respectively. [ABSTRACT FROM AUTHOR]

Compiler frameworks are crucial for the widespread use of FPGA-based deep learning accelerators. They allow researchers and developers, who are not familiar with hardware engineering, to harness the performance attained by domain-specific logic. There exists a variety of frameworks for conventional artificial neural networks. However, not much research effort has been put into the creation of frameworks optimized for spiking neural networks (SNNs). This new generation of neural networks becomes increasingly interesting for the deployment of AI on edge devices, which have tight power and resource constraints. Our end-to-end framework E3NE automates the generation of efficient SNN inference logic for FPGAs. Based on a PyTorch model and user parameters, it applies various optimizations and assesses trade-offs inherent to spike-based accelerators. Multiple levels of parallelism and the use of an emerging neural encoding scheme result in an efficiency superior to previous SNN hardware implementations. For a similar model, E3NE uses less than 50% of hardware resources and 20% less power, while reducing the latency by an order of magnitude. Furthermore, scalability and generality allowed the deployment of the large-scale SNN models AlexNet and VGG. [ABSTRACT FROM AUTHOR]

Big data technology has gained attention in all fields, particularly with regard to research and financial institutions. This technology has changed the world tremendously. Researchers and data scientists are currently working on its applicability in different domains such as health care, medicine, and the stock market, among others. The data being generated at an unexpected pace from multiple sources like social media, health care contexts, and Internet of things have given rise to big data. Management and processing of big data represent a challenge for researchers and data scientists, as there is heterogeneity and ambiguity. Heterogeneity is considered to be an important characteristic of big data. The analysis of heterogeneous data is a very complex task as it involves the compilation, storage, and processing of varied data based on diverse patterns and rules. The proposed research has focused on the heterogeneity problem in big data. This research introduces the hybrid support vector machine (H-SVM) classifier, which uses the support vector machine as a base. In the proposed algorithm, the heterogeneous Euclidean overlap metric (HEOM) and Euclidean distance are introduced to form clusters and classify the data on the basis of ordinal and nominal values. The performance of the proposed learning classifier is compared with linear SVM, random forest, and k-nearest neighbor. The proposed algorithm attained the highest accuracy as compared to other classifiers. [ABSTRACT FROM AUTHOR]

Over the past decade, neurorobotics-integrated machine learning has emerged as a new methodology to investigate and address related problems. The combined use of machine learning and neurorobotics allows us to solve problems and find explanatory models that would not be possible with traditional techniques, which are basic within the principles of symmetry. Hence, neuro-robotics has become a new research field. Accordingly, this study aimed to classify existing publications on neurorobotics via content analysis and knowledge mapping. The study also aimed to effectively understand the development trend of neurorobotics-integrated machine learning. Based on data collected from the Web of Science, 46 references were obtained, and bibliometric data from 2013 to 2021 were analyzed to identify the most productive countries, universities, authors, journals, and prolific publications in neurorobotics. CiteSpace was used to visualize the analysis based on co-citations, bibliographic coupling, and co-occurrence. The study also used keyword network analysis to discuss the current status of research in this field and determine the primary core topic network based on cluster analysis. Through the compilation and content analysis of specific bibliometric analyses, this study provides a specific explanation for the knowledge structure of the relevant subject area. Finally, the implications and future research context are discussed as references for future research. [ABSTRACT FROM AUTHOR]

With noisy intermediate scale quantum computers (NISQ) becoming larger in scale and more reliable, quantum circuits are growing in size and complexity. In order to face the challenge of achieving optimal circuits, design automation approaches for improving and mapping quantum circuits on different architectures have been proposed, each one characterized by a specific optimization strategy. In this article, the use of a template-based approach for quantum circuits optimization purposes is explored, and the proposal of a modular compilation toolchain, which supports three quantum technologies (nuclear magnetic resonance, trapped ions and superconducting qubits), is presented. The toolchain tackles the task of implementing logic synthesis for single-qubit and multi-qubit gates in the compilation process and it is structured with multiple steps and modular libraries. The toolchain was tested through a benchmarking procedure, and the results for a subset of complex quantum circuits as inputs are here reported, alongside a comparison with those provided by the compilers of IBM's Qiskit and Cambridge Quantum Computing's t | ket . The current toolchain prototype was crafted to be an easily expandable and reliable core for future developments, which could lead it to support even more quantum technologies and a fully fledged layout synthesis. Nonetheless, the obtained results are quite encouraging, and they prove that in certain conditions the Toolchain can be competitive in quantum circuits optimization, especially when dealing with single-qubit gates. [ABSTRACT FROM AUTHOR]

Modern compilers can be useful, not only in detecting programming errors but also by suggesting several repairs and solutions for those errors using error repair techniques. Error repair refers to the process of finding a repair for an error that happens as a result of compiling a piece of code written by computer programmers. However, a repair is not always consistent with the purpose of programmers. This means a compiler suggests a repair which is different from what the programmer wanted to write. Many compilers fail to suggest the correct repair when programming errors occur as a result of misspelling errors. The aim of this paper is to enhance the error repair process in compilers using spelling correction algorithms. A typical compiler does not provide solutions for the most common syntax programming errors which occur as a result of misspelling. Such errors are easy to detect by compilers but difficult to suggest a fix that is the correct form. Therefore, a novel error correction mechanism which is called CoEdit approach is developed to help compilers to suggest the most suitable repair for programming errors occurred as a result of mistyping errors. Four-Way and Editex algorithms are well known spelling correction algorithms are also extended and employed to be compatible to work with programming languages. CoEdit approach employs these algorithms in order to find repairs to misspelling errors. CoEdit is a generic approach to enhance error repair in any compilers for any language because it targets misspelling compiler errors. This paper concludes that using the Editex algorithm with CoEdit is the best choice in the case of finding repairs to programming errors that occur as a result of spelling errors. [ABSTRACT FROM AUTHOR]

Using ICTs in education allows the effective integration of new technologies into the educational process. Developing information and communication technologies also require timely changes in knowledge evaluation and use. As a result, methods, techniques, and technologies used in learning are being updated. In this study, a method for developing an automated educational and methodical complex based on a semantic network is described. Requirements for such educational and methodological complex have been formulated. Structural and formal models of tools based on a semantic network have been presented. The purpose of developing the model is to make it easier for students to perceive the various educational and methodological complexes through its compilation on the basis of a holistic view of the subject area, as well as to optimize the work of the teacher. [ABSTRACT FROM AUTHOR]

We present an ultrahigh-resolution Energy Exascale Earth System Model Land Model (uELM) for high-fidelity land simulations targeting new exascale computers. After considering modeling infrastructure compatibility and ELM software features, we designed a parallel model for the uELM development targeting the hybrid architectures of new U.S. exascale computers. We also described a function unit test framework to expedite the piecewise code porting (with compiler directives), verification, and global variable management. Furthermore, in this study, we report the development of an early uELM model using OpenACC within a function unit test framework on a pre-exascale computer, demonstrate the performance of a uLEM submodel with three-times speedup, and summarize the code-porting experience regarding global variable handling, deepcopy, memory reduction, and parallel loop reconstruction. [ABSTRACT FROM AUTHOR]

Despite their small spatial extent, fluvial ecosystems play a significant role in processing and transporting carbon in aquatic networks, which results in substantial emission of methane (CH4) to the atmosphere. For this reason, considerable effort has been put into identifying patterns and drivers of CH4 concentrations in streams and rivers and estimating fluxes to the atmosphere across broad spatial scales. Yet progress toward these ends has been slow because of pronounced spatial and temporal variability of lotic CH4 concentrations and fluxes and by limited data availability across diverse habitats and physicochemical conditions. To address these challenges, we present the first comprehensive database of CH4 concentrations and fluxes for fluvial ecosystems along with broadly relevant and concurrent physical and chemical data. The Global River Methane database (GriMeDB; https://doi.org/10.6073/pasta/b7d1fba4f9a3e365c9861ac3b58b4a90) includes 24,024 records of CH4 concentration and 8,205 flux measurements from 5,037 unique sites that were extracted from publications, reports, data repositories, and other outlets published between 1973 and 2021. GriMeDB also includes 17,655 and 8,409 concurrent measurements of concentrations and 4,444 and 1,521 of fluxes for CO2 and nitrous oxide (N2O) respectively. Most observations are date-specific (i.e., not site averages) and many are supported by data for 12 physicochemical variables and 6 site variables. Site variables include codes to characterize marginal channel types (e.g., springs, ditches) and/or presence of human disturbance (e.g., point source inputs, upstream dams). Overall, observations in GRiMeDB encompass a broad range of the climatic, biological, and physical conditions that occur among world river basins, although some geographic gaps remain (e.g., arid regions, tropical regions, high latitudes and altitude systems). The global median CH4 concentration (0.20 μmol L-1) and diffusive flux (0.44 mmol m-2 d-1) in GRiMeDB are lower than estimates from past, site-averaged compilations, although ranges and standard deviations are greater from this larger and more temporally-resolved database. Available flux data are dominated by diffusive measurements despite the recognized importance of ebullitive and plant-mediated CH4 fluxes. Despite these limitations, GriMeDB provides a comprehensive and cohesive resource for examining relationships between CH4 and environmental drivers, estimating the contribution of fluvial ecosystems to CH4 emissions, and to contextualize site-based investigations. [ABSTRACT FROM AUTHOR]

With the evolution of the renewal concept and protection mode of dwellings in ancient city in the new era, the guidelines for the renovation of dwellings compiled in the past have shown obvious limitations of the times. Its compilation form is too simple, and the content is slightly insufficient, and it is difficult to scientifically guide the high-standard renovation of traditional dwellings in the new era. In the compilation of the Technical Guidelines for Renovation of Yangzhou Traditional Dwellings, the core concept is "continuing the style and texture of the ancient city, inheriting the construction technology of private houses, and integrating innovative renovation techniques", and an overall framework for integrating the technical guidelines for renovation of traditional dwellings in "new era and new concept" is proposed. The classification guidance standards for different types of traditional dwellings and their surrounding ancillary environment are formulated, and the corresponding renovation plans of traditional dwellings are systematically drawn as supplementary guidance documents for the relevant classification guidance standards. [ABSTRACT FROM AUTHOR]

Coarse-grained reconfigurable array (CGRA) has emerged as a promising hardware accelerator due to the excellent balance between reconfigurability, performance, and energy efficiency. The performance of a CGRA strongly depends on the existence of a high-quality compiler to map the application kernels on the architecture. Unfortunately, the state-of-the-art compiler technology falls short in generating high-performance mapping within an acceptable compilation time, especially with increasing CGRA size. We propose HiMap—a fast and scalable CGRA mapping approach—that is also adept at producing close-to-optimal solutions for regular computational kernels prevalent in existing and emerging application domains. The key strategy behind HiMap’s efficiency and scalability is to exploit the regularity in the computation by employing a virtual systolic array (VSA) as an intermediate abstraction layer in a hierarchical mapping. HiMap first maps the loop iterations of the kernel onto a VSA and then distills out the unique patterns in the mapping. These unique patterns are subsequently mapped onto subspaces of the physical CGRA. They are arranged together according to the systolic array mapping to create a complete mapping of the kernel. Experimental results confirm that HiMap can generate application mappings that hit the performance envelope of the CGRA. HiMap offers $17.3\times $ and $5\times $ improvement in performance and energy efficiency of the mappings compared to the state of the art. The compilation time of HiMap for near-optimal mappings is less than 15 min for 64 $\times $ 64 CGRA while existing approaches take days to generate inferior mappings. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) processing units, or DPUs, are one of the most energy-efficient platforms for DNN applications. However, designing new DPUs for every DNN model is very costly and time consuming. In this article, we propose an alternative approach: to specialize coarse-grained reconfigurable architectures (CGRAs), which are already quite capable of delivering high performance and high energy efficiency for compute-intensive kernels. We identify a small set of architectural features on a baseline CGRA to enable high-performance mapping of depthwise convolution (DWC) and pointwise convolution (PWC) kernels, which are the most important building block in recent light-weight DNN models. Our experimental results using MobileNets demonstrate that our proposed CGRA enhancement can deliver $8\sim 18\times $ improvement in area-delay product (ADP) depending on layer type, over a baseline CGRA with a state-of-the-art CGRA compiler. Moreover, our proposed CGRA architecture can also speed up 3-D convolution with similar efficiency as previous work, demonstrating the effectiveness of our architectural features beyond depthwise separable convolution (DSC) layers. [ABSTRACT FROM AUTHOR]

It is appealing but challenging to achieve real-time deep neural network (DNN) inference on mobile devices, because even the powerful modern mobile devices are considered as “resource-constrained” when executing large-scale DNNs. It necessitates the sparse model inference via weight pruning, i.e., DNN weight sparsity, and it is desirable to design a new DNN weight sparsity scheme that can facilitate real-time inference on mobile devices while preserving a high sparse model accuracy. This paper designs a novel mobile inference acceleration framework GRIM that is General to both convolutional neural networks (CNNs) and recurrent neural networks (RNNs) and that achieves Real-time execution and high accuracy, leveraging fine-grained structured sparse model Inference and compiler optimizations for Mobiles. We start by proposing a new fine-grained structured sparsity scheme through the Block-based Column-Row (BCR) pruning. Based on this new fine-grained structured sparsity, our GRIM framework consists of two parts: (a) the compiler optimization and code generation for real-time mobile inference; and (b) the BCR pruning optimizations for determining pruning hyperparameters and performing weight pruning. We compare GRIM with Alibaba MNN, TVM, TensorFlow-Lite, a sparse implementation based on CSR, PatDNN, and ESE (a representative FPGA inference acceleration framework for RNNs), and achieve up to $14.08\times$ 14. 08 × speedup. [ABSTRACT FROM AUTHOR]

Cluster assignment is a compiler optimization that plays an important role in performance of programs. However, the existing algorithms only work on straight-line program area, and is difficult to be optimal. Aiming at these problems, this paper proposed a unified cluster assignment and instruction scheduling method based on integer linear programming. This method used zero-one decision variables to represent cluster assignment, local instruction scheduling and global scheduling of inter-cluster transfer instructions, and formulated dependency and processor resources competition between instructions into linear constraints, eventually got an integer linear programming model whose objective is to minimize the estimated execution time of the function. Experimental results show that the cluster assignment and scheduling scheme from solving the model significantly outperforms the existing algorithms on accelerating programs, and the time required to solve the model is acceptable. [ABSTRACT FROM AUTHOR]

From a security view, Multi-variant Execution (MVX) is widely used in network security defense, but there is a common problem in multi-variant execution: When each executive body returns content to the arbiter, it is difficult to solve the false alarm caused by the combination. Excluding objective factors such as the machine environment, false alarms are generated because the voter starts to make security judgments on non-consistent variables after receiving the combined information. In addition to non-consistent variables caused by real attacks, there are also non-consistent variables generated by normal system operation. (such as memory descriptors, port numbers, random numbers, codes, and the calling sequence of threads in the process), voted normal operation of the multi-variant system made misjudgment. If reduced the false alarm rate of multi-variant execution, the system efficiency and defense capability would improved effectively. This paper classifies the types of multi-variant execution in recent years, summarizes the false alarms caused by multi-variant execution and the solutions, Analyze the causes of false alarms caused by multi-variant execution, select the Pina algorithm for synchronization, the compiler module instrumentation strategy, and the strategy for narrowing the voting boundary, analyzed the three schemes in specific application scenarios, and analyzed each method. Then pointed the functions and performance of each strategy, pointed the advantages and disadvantages of each strategy. Finally, discussed the unsolved difficulties and future research directions of the existing multi-variant implementation. [ABSTRACT FROM AUTHOR]

Hardware acceleration of Artificial Intelligence (AI) workloads has gained widespread popularity with its potential to deliver unprecedented performance and efficiency. An important challenge remains in how AI accelerators are programmed to sustain high utilization without impacting end-user productivity. Prior software optimizations start with an input graph and focus on node-level optimizations, viz. dataflows and hierarchical tiling, and graph-level optimizations such as operation fusion. However, little effort has been devoted to inter-node on-chip scratchpad memory (SPM) management in Deep Learning (DL) accelerators, whose significance is bolstered by the recent trends in complex network topologies and the emergence of eager execution in DL frameworks. We characterize and show that there exists up to a 5.2× performance gap in DL inference to be bridged using SPM management and propose OnSRAM, a novel SPM management framework integrated with the compiler runtime of a DL accelerator. We develop two variants, viz. OnSRAM-Static, which works on static graphs to identify data structures that can be lucratively held on-chip based on their size, liveness and significance, and OnSRAM-Eager, which targets an eager execution model (no graph) and uses a history-based speculative scheme to hold/discard data structures. We integrate OnSRAM with TensorFlow and analyze it on multiple accelerator configurations. Across a suite of 12 images, objects, and language networks, on a 3 TFLOP system with a 2 MB SPM and 32 GBps external memory bandwidth, OnSRAM-Static and OnSRAMEager achieve 1.02-4.8× and 1.02-3.1× reduction in inference latency (batch size of 1), over a baseline with no SPM management. In terms of energy savings, we observe average reductions of 1.51× (up to 4.1×) and 1.23× (up to 2.9×) for the static and eager execution scenarios, respectively. [ABSTRACT FROM AUTHOR]

Compilers are a kind of important software, and similar to the quality assurance of other software, compiler testing is one of the most widely-used ways of guaranteeing their quality. Compiler bugs tend to occur in compiler optimizations. Detecting optimization bugs needs to consider two main factors: (1) the optimization flags controlling the accessability of the compiler buggy code should be turned on; and (2) the test program should be able to trigger the buggy code. However, existing compiler testing approaches only consider the latter to generate effective test programs, but just run them under several pre-defined optimization levels (e.g., -0θ, -O1, -02, -03, -0s in GCC). To better understand the influence of compiler optimizations on compiler testing, we conduct the first empirical study, and find that (1) all the bugs detected under the widely-used optimization levels are also detected under the explored optimization settings (we call a combination of optimization flags turned on for compilation an optimization setting), while 83.54% of bugs are only detected under the latter; (2) there exist both inhibition effect and promotion effect among optimization flags for compiler testing, indicating the necessity and challenges of considering the factor of compiler optimizations in compiler testing. We then propose the first approach, called COTest, by considering both factors to test compilers. Specifically, COTest first adopts machine-learning (the XGBoost algorithm) to model the relationship between test programs and optimization settings, to predict the bug-triggering probability of a test program under an optimization setting. Then, it designs a diversity augmentation strategy to select a set of diverse candidate optimization settings for prediction for a test program. Finally, Top-K optimization settings are selected for compiler testing according to the predicted bug-triggering probabilities. The experiments on GCC and LLVM demonstrate its effectiveness, especially COTest detects 17 previously unknown bugs, 11 of which have been fixed or confirmed by developers. [ABSTRACT FROM AUTHOR]

Smart contracts are programs deployed on a blockchain. They are executed for a monetary fee paid in gas— a clear optimization target for smart contract compilers. Because smart contracts are a young, fast-moving field without (manually) fine-tuned compilers, they highly benefit from automated and adaptable approaches, especially as smart contracts are effectively immutable, and as such need a high level of assurance. This makes them an ideal domain for applying formal methods. Super-optimization is a technique to find the best translation of a block of instructions by trying all possible sequences of instructions that produce the same result. We present a framework for super-optimizing smart contracts based on Max-SMT with two main ingredients: (1) a stack functional specification extracted from the basic blocks of a smart contract, which is simplified using rules capturing the semantics of arithmetic, bit-wise, and relational operations, and (2) the synthesis of optimized blocks, which finds—by means of an efficient SMT encoding—basic blocks with minimal gas cost whose stack functional specification is equal (modulo commutativity) to the extracted one. We implemented our framework in the tool syrup 2.0. Through large-scale experiments on real-world smart contracts, we analyze performance improvements for different SMT encodings, as well as tradeoffs between quality of optimizations and required optimization time. [ABSTRACT FROM AUTHOR]

Instruction reordering and interleavings in program execution under relaxed memory semantics result in non-intuitive behaviors, making it difficult to provide assurances about program correctness. Studies have shown that up to 90% of the concurrency bugs reported by state-of-the-art static analyzers are false alarms. As a result, filtering false alarms and detecting real concurrency bugs is a challenging problem. Unsurprisingly, this problem has attracted the interest of the research community over the past few decades. Nonetheless, many of the existing techniques rely on analyzing source code, rarely consider the effects introduced by compilers, and assume a sequentially consistent memory model. In a practical setting, however, developers often do not have access to the source code, and even commodity architectures such as x86 and ARM are not sequentially consistent. In this work, we present Bird, a prototype tool, to dynamically detect harmful data races in x86 binaries under relaxed memory models, TSO and PSO. Bird employs source-DPOR to explore all distinct feasible interleavings for a multithreaded application. Our evaluation of Bird on 42 publicly available benchmarks and its comparison with the state-of-the-art tools indicate Bird’s potential in effectively detecting data races in software binaries. [ABSTRACT FROM AUTHOR]

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The commercial off-the-shelf (COTS) component-based ecosystem provides an attractive system design paradigm due to the drastic reduction in development time and cost compared to custom solutions. However, it brings in a growing concern of trustworthiness arising from the possibility of malicious embedded logic or hardware Trojans in COTS components. Existing hardware Trojan countermeasures are typically not applicable to COTS hardware due to the need for zero trust consideration for all supply chain entities, absence of golden models, and lack of observability of internal signals within the component. In this work, we propose a novel approach for runtime Trojan detection and resilience in untrusted COTS processors through judicious modifications in the software. The proposed approach does not rely on any hardware redundancy or architectural modification and hence seamlessly integrates with the COTS-based system design process. Trojan resilience is achieved through the execution of multiple functionally equivalent software variants. We have developed and implemented a solution for compiler-based automatic generation of program variants, metric-guided selection of variants, and their integration in a single executable. To evaluate the proposed approach, we first analyzed the effectiveness of program variants in avoiding the activation of a random pool of Trojans. Then, by implementing several Trojans in an OpenRISC 1000 processor, we analyzed the detectability and resilience under Trojan activation in both single and multiple variants. We also present delay and code size overhead for the automatically generated variants for several programs and discuss future research directions. [ABSTRACT FROM AUTHOR]

We develop a ytopt autotuning framework that leverages Bayesian optimization to explore the parameter space search and compare four different supervised learning methods within Bayesian optimization and evaluate their effectiveness. We select six of the most complex PolyBench benchmarks and apply the newly developed LLVM Clang/Polly loop optimization pragmas to the benchmarks to optimize them. We then use the autotuning framework to optimize the pragma parameters to improve their performance. The experimental results show that our autotuning approach outperforms the other compiling methods to provide the smallest execution time for the benchmarks syr2k, 3mm, heat‐3d, lu, and covariance with two large datasets in 200 code evaluations for effectively searching the parameter spaces with up to 170,368 different configurations. We find that the Floyd–Warshall benchmark did not benefit from autotuning. To cope with this issue, we provide some compiler option solutions to improve the performance. Then we present loop autotuning without a user's knowledge using a simple mctree autotuning framework to further improve the performance of the Floyd–Warshall benchmark. We also extend the ytopt autotuning framework to tune a deep learning application. [ABSTRACT FROM AUTHOR]

Machine Learning Computers (MLCs) with tensor functional units (e.g., NVIDIA’s Tensor Core, Google’s TPU and Habana’s Tensor Processor Core) have emerged significantly over recent years. The broad diversity of MLCs makes it hard to deploy machine learning workloads with optimized performance. Though deep learning compilers (e.g., TVM) are effective to produce optimized code for different hardware back-ends, when deploying to a new MLC, it is tedious to implement platform-specific compilation optimizations by thoroughly understanding system/architectural details. To address this problem, we propose a holistic approach to achieve one-size-fits-all compilation optimization for inference across different MLCs. The key observation is that diverse MLCs share multiple key architectural characteristics (e.g., tensor primitives and on-chip scratchpad memory) for tensor processing, which can be generalized for conducting cross-platform compilation optimizations. Concretely, we propose the Tensor Abstract Machine (TAM), which features such common architectural characteristics, as the abstraction of a broad range of MLCs. To leverage architectural characteristics of the TAM, we propose the Tensor Scheduling Language (TSL) consisting of tensor computation description and tensor scheduling primitives for implementing operations with portable optimization. By implementing tensor operations with TSL, the related optimized code for different MLCs can be automatically generated. To validate our proposal, we conduct experiments on 3 commodity MLCs including GPU with Tensor Cores, VTA (on FPGA), and Cloud TPU. Experimental results demonstrate that the code generated from the same optimization schedule achieves 1.05x to 2.05x better performance than hand-tuned libraries and deep learning compilers across different platforms. [ABSTRACT FROM AUTHOR]