843 results on '"Chung-Kuan Cheng"'
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202. Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
203. On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.
204. Prediction and Comparison of High-Performance On-Chip Global Interconnection.
205. RLC interconnect delay estimation via moments of amplitude and phase response.
206. A Performance-Driven I/O Pin Routing Algorithm.
207. An O-Tree Representation of Non-Slicing Floorplan and Its Applications.
208. Efficient Power Network Analysis with Modeling of Inductive Effects.
209. Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.
210. Efficient Power Network Analysis Considering Multidomain Clock Gating.
211. Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.
212. Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design.
213. Energy and switch area optimizations for FPGA global routing architectures.
214. Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards.
215. Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules
216. Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation
217. Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs
218. Rectilinear block placement using sequence-pair.
219. Extending Moment Computation to 2-Port Circuit Representations.
220. Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
221. Analyzing High-Density ECG Signals Using ICA.
222. A building block placement tool.
223. A new layout-driven timing model for incremental layout optimization.
224. A Network Flow Approach for Hierarchical Tree Partitioning.
225. Cluster Refinement for Block Placement.
226. Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion.
227. Two-Stage Newton-Raphson Method for Transistor-Level Simulation.
228. Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
229. Efficient Timing Analysis With Known False Paths Using Biclique Covering.
230. Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
231. MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks.
232. ePlace-3D: Electrostatics based Placement for 3D-ICs.
233. Simultaneous Routing and Buffer Insertion for High Performance Interconnect.
234. Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.
235. New Spectral Linear Placement and Clustering Approach.
236. New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.
237. Network Partitioning into Tree Hierarchies.
238. Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
239. VLSI Block Placement With Alignment Constraints.
240. General Floorplans with L/T-Shaped Blocks Using Corner Block List.
241. On the construction of zero-deficiency parallel prefix circuits with minimum depth.
242. Buffer allocation algorithm with consideration of routing congestion.
243. Optimization of power dissipation and skew sensitivity in clock buffer synthesis.
244. Linear decomposition algorithm for VLSI design applications.
245. Optimal wire sizing and buffer insertion for low power and a generalized delay model.
246. A gradient method on the initial partition of Fiduccia-Mattheyses algorithm.
247. Finite State Machine Decomposition for I/O Minimization.
248. Routability improvement using dynamic interconnect architecture.
249. Simple tree-construction heuristics for the fanout problem .
250. Performance-Driven Partitioning Using a Replication Graph Approach.
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