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In this work, we propose a new Network-on-Chip (NoC) architecture for implementing the hierarchical parallel genetic algorithm (HPGA) on a multi-core System-on-Chip (SoC) platform. We first derive the speedup metric of an NoC architecture which directly maps the HPGA onto NoC in order to identify the main sources of performance bottlenecks. Specifically, it is observed that the speedup is mostly affected by the fixed bandwidth that a master processor can use and the low utilization of slave processor cores. Motivated by the theoretical analysis, we propose a new architecture with two multiplexing schemes, namely dynamic injection bandwidth multiplexing (DIBM) and time-division based island multiplexing (TDIM), to improve the speedup and reduce the hardware requirements. Moreover, a task-aware adaptive routing algorithm is designed for the proposed architecture, which can take advantage of the proposed multiplexing schemes to further reduce the hardware overhead. We demonstrate the benefits of our approach using the problem of protein folding prediction, which is a process of importance in biology. Our experimental results show that the proposed NoC architecture achieves up to 240X speedup compared to a single island design. The hardware cost is also reduced by 50% compared to a direct NoC-based HPGA implementation. © 2014 IEEE.

Protein folding is critical for many biological processes. In this work, we propose an NoC-based multi-core platform for protein folding computation. We first identify the speedup bottleneck for applying conventional genetic algorithm on a mesh-based multi-core platform. Then, we address this computation-and communication-intensive problem while taking into account both hardware and software aspects. Specifically, we group the processing cores into islands and propose an NoC-based multicore architecture for intra-and inter-island communication. The high scalability of the proposed platform allows us to integrate from 100 to 1200 cores for the folding computation. We then propose a genetic migration algorithm to take advantage of the massive parallel platform. Our simulation results show that the proposed platform offers near-linear speedup as the number of cores increases. We also report the hardware cost in area and power based on a 100-core FPGA prototype. Copyright 2014 ACM.

In this work, we propose a new, accurate, and comprehensive analytical model for Network-on-Chip (NoC) performance analysis. Given the application communication graph, the NoC architecture, and the routing algorithm, the proposed framework analyzes the links dependency and then determines the ordering of queuing analysis for performance modeling. The channel waiting times in the links are estimated using a generalized G/G/1/K queuing model, which can tackle bursty traffic and dependent arrival times with general service time distributions. The proposed model is general and can be used to analyze various traffic scenarios for NoC platforms with arbitrary buffer and packet lengths. Experimental results on both synthetic and real applications demonstrate the accuracy and scalability of the newly proposed model. © 2014 IEEE.

With discovery of the insulin, Type-1 diabetes converted from a fatal and acute to a chronic disease which includes micro-vascular complications which range from Kidney disease to stroke and micro-vascular complications such as retinopathy, nephropathy and neuropathy. Artificial pancreas is a solution to improve the quality of life for people with this very fast growing disease in the world and to reduce the costs. Despite technological advances e.g., in subcutaneous sensors and actuators for insulin injection, modeling of blood glucose dynamics and control algorithms still need significant improvement. In this paper, we investigate challenges and opportunities for development of efficient algorithm for designing robust artificial pancreas. We discuss the state of the art and summarize clinical and in silico assessment results. We contrast conventional integer order system approach with a newly proposed fractal control and summarize its benefits.

As technology scaling down allows multiple processing components to be integrated on a single chip, the modern computing systems led to the advent of Multiprocessor System-on-Chip (MPSoC) and Chip Multiprocessor (CMP) design. Network-on-Chips (NoCs) have been proposed as a promising solution to tackle the complex on-chip communication problems on these multicore platforms. In order to optimize the NoC-based multicore system design, it is essential to evaluate the NoC performance with respect to numerous configurations in a large design space. Taking the traffic characteristics into account and using an appropriate latency model become crucially important to provide an accurate and fast evaluation. In this tutorial, we survey the current progresses in these aspects. We first review the NoC workload modeling and traffic analysis techniques. Then, we discuss the mathematical formalisms of evaluating the performance under a given traffic model, for both the average and worst-case latency predictions. Finally, the advantages of combining the analytical and simulation-based techniques are discussed and new attempts for bridging these two approaches are reviewed. © 2013 IEEE.

In this paper, we propose a flexible NoC architecture and a dynamic distributed routing algorithm which can enhance the NoC communication performance with minimal energy overhead. In particular, our proposed NoC architecture exploits the following two features: i) self-reconfigurable bidirectional channels to increase the effective bandwidth and ii) express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at runtime in the network. A deadlock-free and traffic-aware dynamic routing algorithm is further developed for the proposed architecture, which can take advantage of the increased flexibility in the proposed architecture. Both the channels self-reconfiguration and routing decisions are made in a distributed fashion, based on a function of the localized traffic conditions, in order to maximize the performance and minimize the energy costs at the macroscopic level. Our simulation results show that the proposed approach can reduce the network latency by 30%-80% in most cases compared to a conventional unidirectional mesh topology, while incurring less than 15% power overhead.