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In this work, we demonstrate vertically stacked multilayer sub-1-nm In2O3 field-effect transistors (FETs) with surrounding gate in a back-end-of-line (BEOL) compatible low-temperature fabrication process. A typical bottom-gated single layer In2O3 FET with maximum on-state current (ION) of 890 μA/μm at VDS = 0.8 V and an on/off ratio over 106 is achieved with a channel length (Lch) of 100 nm. The effects of HfO2 capping and O2 annealing are systematically studied, which is critical to realizing the multilayer FETs. Each atomically thin In2O3 channel layer with a thickness (TIO) of 0.9 nm is realized by atomic layer deposition (ALD) at 225 °C. Multilayer FETs with a number of In2O3 layers up to 4 and 1.2 nm-thick HfO2 between each individual layer are fabricated. An enhancement of on-state current (ION) from 183 μA in a single layer In2O3 FET to 339 μA in a 4 layer device with an on/off ratio of 3.4 × 104 is achieved, demonstrating the key advantage of the multilayer FETs to improve the current. Several critical features, such as large-area growth, high uniformity, high reproducibility, ultrathin body, flexibility, and BEOL compatibility, have turned ALD In2O3 into a noteworthy candidate for next-generation oxide semiconductor channel materials. [ABSTRACT FROM AUTHOR]

Nano-membrane tri-gate β -gallium oxide (β -Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between β -Ga2O3 and gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (Al2O3) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV decâˆ'1, high drain current (I DS) ON/OFF ratio of 1.5 × 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with currentâ€"voltage (I â€" V) characteristics measured at temperatures up to 400 °C. [ABSTRACT FROM AUTHOR]

The role of a HfO2 or ZrO2 interlayer as a thermal bridge between a $\beta $ -Ga2O3 channel and a sapphire substrate was investigated using a $\beta $ -Ga2O3 nano-membrane FET as a test vehicle. A 35% less channel temperature increase was observed when a thin HfO2 or ZrO2 interlayer was inserted between the $\beta $ -Ga2O3 channel and the sapphire substrate compared to devices without interlayers. Phonon density of states (PDOS) mismatch can explain the improvement of the thermal boundary conductance (TBC). In the acoustic region, the PDOS of HfO2 or ZrO2 has about a 700% larger overlap area with the PDOS of $\beta $ -Ga2O3 compared to the PDOS of sapphire. This suggests that the insertion of a thermal bridge interlayer can provide a potential solution to the low thermal conductivity of $\beta $ -Ga2O3 and the self-heating effect of $\beta $ -Ga2O3-based FETs. [ABSTRACT FROM AUTHOR]

Recently, back-end-of-line (BEOL) compatible indium oxide (In2O3) thin-film transistors (TFTs), grown by atomic layer deposition (ALD) with channel thickness of ~1 nm and channel length down to 40 nm, have achieved a record high drain current of 2.2 A/mm at ${V}_{\textit {DS}}$ of 0.7 V. A systematic characterization of the reliability issues, such as positive bias temperature stress (PBTS) and hot carrier degradation (HCD), would allow its immediate integration into innovative ICs, such as 3D-stacked SRAM or on-chip bridge for mixed-voltage systems. Surprisingly, PBTS and HCD are both characterized by a universal two-stage threshold voltage shift ($\Delta \!{V}_{\textit {th}}$ , a positive shift followed by a temperature-activated negative shift). This is attributed respectively to electron trapping/trap-generation and hydrogen-assisted formation of donor-traps. These competing mechanisms of $\Delta ~{V}_{\textit {th}}$ depend on the stress voltages and stress temperature. Unlike traditional logic transistors, HCD in BEOL-TFTs is strongly correlated to PBTS, caused by the much stronger vertical field in an ultra-thin device. Overall, this high-performance BEOL-transistor is remarkably reliable, with a relatively small $\Delta ~{V}_{\textit {th}}$ under PBTS/HCD stress conditions at room temperature (RT). However, self- and mutual heating of BEOL interconnect levels and the resultant threshold voltage variability must be mitigated/managed for its successful integration in various neuromorphic circuits. [ABSTRACT FROM AUTHOR]

Recent advances have enabled the demonstration of record high-performance atomically thin n-type indium oxide (In2O3) field-effect transistors with low thermal budget suitable for back-end-of-line logic or memory applications. By using ultra-thin layers of In2O3, its degenerate carrier density is suppressed so that it can be modulated by conventional dielectric gating. These devices have high on-currents due to its high mobility and low contact resistance; meanwhile they can have exceptionally low off-currents due to its wide bandgap. For both low-power logic and memory, the off-state performance should be understood in more detail, although they are constrained by the limits of traditional measurement techniques. In this Letter, we systematically probe the off-current of ultra-thin In2O3 transistors by adopting a wide channel geometry with temperature-dependent electrical measurements and demonstrate the potential for record high current on/off ratios of 1017 on In2O3 transistors. [ABSTRACT FROM AUTHOR]

Understanding the role of the dielectric (DE) layer in ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) based devices (e.g., ferroelectric-field-effect-transistors, FE-FETs) is important to enable their application-driven optimizations. To that end, in this work, we systematically investigate the polarization switching mechanisms in FE–DE stacks and analyze their dependence on the dielectric layer thickness (TDE). First, we fabricate a HZO–Al2O3 (FE–DE) stack and experimentally demonstrate a decrease in remanent polarization and an increase in coercive voltage with an increase in TDE. As such dependencies are out of the scope of commonly used single domain polarization switching models, therefore, we argue that the consideration of the multi-domain model is essential for analyzing the polarization switching in HZO. Then, using phase-field simulations of the FE–DE stack, we show that an increase in TDE results in a larger number of reverse domains in the FE layer to suppress the depolarization field, which leads to a decrease in the remanent polarization and an increase in the coercive voltage. Furthermore, our analysis signifies that the polarization switching mechanism in HZO can be modulated from domain-nucleation based to domain-wall motion based by increasing the TDE and that can serve as a potential knob for application-specific optimization of FE-FETs. In addition, we show that the effective polarization–voltage characteristics of the FE layer in the FE–DE stack exhibit a negative slope region that leads to the charge enhancement effects in the FE–DE stack. While such effects are most commonly misinterpreted as either the transient effects or the stabilized single-domain negative capacitance effects, we demonstrate that the appearance of a negative slope in the hysteretic polarization–voltage characteristics is quasi-static in nature and that originates from the multi-domain polarization switching in the FE. [ABSTRACT FROM AUTHOR]

In this work, we report back-end-of-line (BEOL) compatible indium-tin-oxide (ITO) transistors with ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) as gate insulator. A tunable high-density 2-D electron gas over 0.8 × 1014/cm2 is achieved at the HZO/ITO oxide/oxide interface because of the FE polarization, which is confirmed by I – V, positive up and negative down (PUND), and Hall measurements. Such high carrier density can be completely modulated and switched on and off by FE polarization switching, enabling high mobility ITO transistor with high ON-current and high ON/OFF ratio. [ABSTRACT FROM AUTHOR]