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Reliability of an electronic device, concerning if it can function reliably over its designated lifetime in the field (such as 10 or 15 years), has become more and more important in today's safety-critical applications such as automotive electronics. Traditionally, the ageing has been performed in an offline setting where stress test has been applied to accelerate the ageing process and then a model is established to make the futuristic prediction. This kind of offline method has a drawback of not being able to take into account the factor of the unique operating condition and environment that a device could have experienced in the field. In this work, we present the first cloud-based ageing monitoring system to the best of our knowledge, for the Internet-of-Things (IoT) devices. It has many advantages. First of all, one can know of the ageing status of an IoT device remotely and continuously. Secondly, through data analysis in a cloud server, more accurate prediction can be achieved. Thirdly, an ageing hazard can be alarmed in advance before it actually strikes, and thereby pre-caution actions (such as online repair, or even call-for-maintenance request) can be taken in advance to avoid unnecessary system fatal failure. A prototype system using test chips with built-in design-for-ageing-monitoring circuitry will be demonstrated with measurement data collected through a cloud server.

In this paper, we present a cell-based delay-locked loop (DLL) with an enhanced continuous tracking range. The main contribution is a novel delay line architecture called ping-pong delay line, making it highly resilient to process and temperature variation. In such a DLL design, two cell-based delay lines are incorporated in a way that they exchange their role of command dynamically like in a ping-pong game, and therefore the joint ping-pong delay line can react to severe environmental changes over a very wide range without disruption to the system's operation. The post-layout simulation using a 90-nm complimentary metal-oxide silicon (CMOS) process technology has demonstrated its advantages. A DLL using such a feature can operate reliably even under an extremely hostile environment when the supply voltage drops from 1 to 0.9 V within a timeframe of 4us.

A Phase Detector is an indispensable component in a Delay-Locked Loop (DLL). It compares the phases of two input clock signals and then produce a binary lead/lag signal to indicate which clock signal arrives earlier. The resolution of a PD often determines the accuracy of a DLL in terms of the phase error. Unfortunately, a traditional cell-based PD is strongly susceptible to the process variation. In this paper, we propose a “Voting PD design” to alleviate this problem. First, a number of primitive phase detectors are incorporated, and then their primitive results undergo a majority voting process to produce the final lead/lag signal, and thereby enhancing the overall resolution. A statistical approximation shows that process variation can be compressed to 53% using a voting group of 5 primitive phase detectors.

Product quality control is a prerequisite for ensuring safety, effectiveness, and stability. However, because of the different strain species and fermentation processes, there was a significant difference in quality. As a result, they should be clearly distinguished in clinical use. Among them, the fermentation process is critical to achieving consistent product quality. This study aims to introduce near-infrared spectroscopy analysis technology into the production process of fermented Cordyceps powder, including strain culture, strain passage, strain fermentation, strain filtration, strain drying, strain pulverizing, and strain mixing. First, high performance liquid chromatography (HPLC) was used to measure the total nucleosides content in the production process of 30 batches of fermented Cordyceps powder, including uracil, uridine, adenine, guanosine, adenosine, and the process stability and interbatch consistency were analyzed with traditional Chinese medicine (TCM) fingerprinting, followed by the near-infrared spectroscopy (NIRS) combined with partial least squares regression (PLSR) to establish a quantitative analysis model of total nucleosides for online process monitoring of fermented Cordyceps powder preparation products. The model parameters indicate that the established model with good robustness and high measurement precision. It further clarifies that the model can be used for online process monitoring of fermented Cordyceps powder preparation products.

A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel flush test procedure to determine if a clock network has any small delay faults. This method does not require any change of the clock network, but it does require a “special test clock signal,” which can be generated on the chip by using only standard cells. Experimental results of transistor-level simulation on benchmark circuits injected with resistive open defects in the layout show that the proposed method is capable of detecting a delay fault as small as 52.8 ps.

Lead poisoning (LP) is less commonly encountered in emergency departments (ED). However, lead exposure still occurs, and new sources of poisoning have emerged. LP often goes unrecognized due to a low index of suspicion and nonspecific symptoms. We present a case of a 48-year-old man who had recurring abdominal pain with anemia that was misdiagnosed. His condition was initially diagnosed as nonspecific abdominal pain and acute porphyria. Acute porphyria-like symptoms with a positive urine porphyrin test result led to the misdiagnosis; testing for heme precursors in urine is the key to the differential diagnosis between LP and acute porphyria. The final definitive diagnosis of lead toxicity was confirmed based on high blood lead levels after detailed medical history taking. The lead poisoning was caused by traditional Chinese herbal pills. The abdominal pain disappeared after a course of chelating treatment. The triad for the diagnosis of lead poisoning should be a history of medicine intake, anemia with basophilic stippling, and recurrent abdominal pain.

The Tunable Delay Line (TDL) is the most important building block in a modern cell-based timing circuit such as Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL). In previously proposed TDLs, one dilemma exists -- they cannot be both power efficient and environmentally adaptive at the same time. In this paper, we present an effective solution for such a dilemma - a novel "ping-pong delay line" architecture. The idea is to use two small cell-based delay lines operated in a synergistic manner in the sense that they exchange the "role of command" dynamically like in a ping-pong game, and thereby jointly reacting to severe environmental changes over a very wide range. This proposed ping-pong delay line has been incorporated in a Delay-Locked Loop (DLL) design, to demonstrate its advantages by post-layout simulation.

Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case.

To explore the potential targets and mechanism of Strychni Semen in the nervous system through network pharmacology and molecular docking, in this study, TCMSP, PubChem, and Swiss Target Prediction databases were used to screen the active ingredients and targets of Strychni Semen; related targets of the nervous system were screen out through GeneCards and OMIM databases; the common targets of the two were input into the STRING online analysis platform to construct potential protein interactions (PPI) network. The Cytoscape 3.7.2 software was used to construct a “component-target” network diagram; then the Metascape platform was used to perform GO and KEGG enrichment analysis on its core targets; and the core target was verified by molecular docking with the active ingredient of Strychni semen. In the results, the screening in Strychni Semen with OB ≥ 30% and DL ≥ 0.18% as the threshold values obtained a total of 15 active ingredients and corresponding 384 potential targets; searched for diseases with “neurological” as keywords, 34769 related targets were mapped to potential drug targets, and 61 common targets were obtained; 74 nodes and 173 edges were read in the “component-target” network diagram; enriched in GO and KEGG A total of 11 signal pathways with significant differences were obtained in the analysis; molecular docking showed that the compounds in Strychni Semen have high binding energy to key proteins of the nervous system. In conclusion, the study initially explored the potential mechanism of Strychni Semen’s multi-pathway and multi-target action on the nervous system, providing scientific basis for the clinical application and in-depth research of the decoction piece.

This paper presents a radar system for extracting human respiratory features. The proposed radar chip comprises three major components: a digital-to-time converter (DTC), a transmitter, and a receiver. The all-digital standard cell-based DTC achieves a timing resolution of 10 ps on a 100-ns time scale, supporting a range-gated sensing process. The transmitter is composed of a digital pulse generator. The receiver comprises a direct-sampling passive frontend for achieving high linearity, an integrator for enhancing the signal-to-noise ratio, and a successive approximation register analog-to-digital converter for signal quantization. A fully integrated CMOS impulse radar chip was fabricated using 65-nm CMOS technology, and the total power consumption is 21 mW. In the backend, a real-time digital signal-processing platform captures human respiratory waveforms via the radar chip and processes the waveforms by applying a human respiratory feature extraction algorithm. Furthermore, a clinical trial was conducted for establishing a new diagnosis workflow for identifying respiratory diseases by the proposed wireless sensor system. The proposed system was validated by applying an adaptive network-based fuzzy inference system and support vector machine algorithm to the clinical trial results. These algorithms confirmed the effectiveness of the proposed system in diagnosing respiratory diseases.

In this work, we present a long-range delay block for a wide range DLL supporting clock rates from 10MHz to 1GHz. The main contribution is a fast-locking scheme that quickly decides the control code of the delay block using a folded scheme. Post-layout simulation using a 90nm CMOS process has demonstrated that the locking time can he slashed dramatically.

In this work, we present the first cell-based Fractional-N Phase-Locked Loop (PLL) compiler, according to the best of our knowledge. Unlike its previous integer-N PLL compiler, a target clock frequency can be generated precisely with an almost arbitrary input reference clock frequency. For example, 1 GHz output clock can be generated from a given 17.33MHz reference clock. With a search engine, such a compiler can find a small-area as well as low-power PLL configuration within minutes. We also have verified its ability for two process nodes (i.e., 90nm and 180nm) by transistor-level simulation on seven test-case PLL macros generated by this compiler. Experimental results show that they can indeed function correctly under extreme PVT conditions.

Die-to-die interconnects linking multiple functional dies in a modern 3-D or 2.5-D IC by micro-bumps could experience resistance increase after certain time of field operation due to parametric defects or aging. To cope with this reliability threat, we present an “on-line transition-time binning method” that aims to continuously detect excessive transition time occurring at a target die-to-die interconnect. Our method attaches a monitor to the termination end of each target interconnect. Any transition (rising or falling) is converted into a pulse-width first, which is then further compared to a dynamically tunable threshold for a binary pass/fail judgment. By multiple runs of transition-time monitoring while sweeping the threshold incrementally, the “transition-time bin” of each target interconnect can be derived and thereby a timing failure threat can be detected by a monitor center before it actually strikes.

For a multi-die IC, the chip-level clock synchronization problem that aims to establish a global clock signal across multiple functional dies is harder to achieve than its single-die counterpart. In this work, we investigate a process resilient solution for this problem by incorporating Delay-Locked Loops (DLLs). The basic idea is to insert a DLL (which can be generated by a DLL compiler) in each functional die so that the clock latency (from a clock source to the clock ports of a number of FFs) in different dies can be dynamically tuned and equalized. This method has a benefit that the clock network of each die can be designed independently, while the clock skew of the entire chip can still be minimized at run-time, in response to its operating environment. In a preliminary study, experimental results on a pseudo 4-die design demonstrates how the clock skew as high as 233ps initially can be reduced to 34ps after the application of the proposed method.

Reliability of an IC, concerning if an IC can function reliably over its designated lifetime in the field, has become more and more important in today's safety-critical applications. It is known that reliability can be affected by PVT effects, (Process, Voltage, Temperature). These effects not only depend on the physical locations where an IC is operated, but also vary over time. In this work, we present a cloud-based PVT monitoring system for the Internet of Things (IoT) devices, by taking advantage of its inherent internet connectivity. By doing so, one can know of the PVT status of any IoT device remotely and continually at any time and any place. With the obtained information, a potential PVT-induced failure can be alarmed in advance before it actually strikes, and thereby pre-cautious actions (such as adaptive measures, online repair, or even manual replacement) can be taken in advance to avoid unnecessary system down time.

We conducted a retrospective study to compare clinical and laboratory findings between 1) severe influenza A and mild influenza A and 2) pandemic 2009 H1N1 (pdm09 A/H1) and seasonal H3N2 (A/H3) from 2009 to 2010. A total of 526 (mean age, 13.6 years; 447 pdm09 A/H1, 79 seasonal A/H3) patients were included, 41 (7.8%) with severe influenza (mean age, 28.1 years; 26 pdm09 A/H1, 15 seasonal A/H3). Influenza-associated complications were pneumonia (75.6%), meningoencephalitis (14.6%), acute kidney injury (14.6%), and acute respiratory distress syndrome (12.2%). Patients with seasonal A/H3 were significantly less likely to experience sore throat (P < 0.001), malaise (P < 0.001), and muscle pain (P < 0.001); they were significantly more likely to have hypertension (P < 0.001), diabetes mellitus (P = 0.001), and chronic obstructive pulmonary disease (P < 0.001), delayed hospital presentation (P = 0.001), delayed oseltamivir treatment (P < 0.001), and higher in-hospital mortality (P = 0.02) than patients with pdm09 A/H1. Further comparison between severe pdm09 A/H1 and severe seasonal A/H3 revealed that severe seasonal A/H3 patients (median age, 71 years) were significantly older than patients with severe pdm09 A/H1 (median age, 7 years) (P < 0.001). Comparison between severe influenza and mild influenza, regardless of influenza A subtypes, by multivariate analysis, found that tachypnea (odds ratio [OR] = 44.3, 95% confidence interval [CI] = 15.7-124.6) and delayed oseltamivir therapy ≧ 48 hours after illness onset (OR = 3.7, 95% CI = 1.3-10.5) were independent risk factors for severe influenza. The findings of this study will improve the understanding of the clinical differences between pdm09 A/H1 and seasonal A/H3, and of influenza-associated complications and predictors for severe outcomes that can help to direct clinicians toward the most effective management of influenza patients to reduce the preventable mortality and morbidity.

This paper proposes a resilient Time-to-Digital Converter (TDC) that lends itself to cell-based design automation. We adopt a shrinking-based architecture with a number of distinctive techniques. First of all, a specialized on-chip re-calibration scheme is developed so that the real-time transfer function of the TDC in silicon (which maps an input pulse-width to its corresponding output code) can be derived on the chip and thereby the absolute value (instead of just a relative code) of an input pulse-width under measurement can be reported. Secondly, the sampling errors stemming from the jitters of training clocks used in the calibration scheme are mitigated by the principle of multi sampling. Thirdly, a flexible coarse-shrinking block is adopted and an automatic adjustment scheme is employed so that the coarse-shrinking block can adjust itself when operated under different input pulse-width ranges.

In this paper, we present a general at-speed test method for die-to-die interconnects and demonstrate its particular application to the interposer wires in a 2.5-D IC. At the heart of this method is a pulse-vanishing test technique (called PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the driver end. If this pulse vanishes at the receiver's output, then it indicates the presence of a delay fault. This PV-test technique is effective for detecting not only resistive open faults, but also resistive bridging faults between interposer wires. This method has several other advantages. For example, the implementation is especially easy as it incorporates only logic cells and can be merged with boundary scan cells. Also, it can support on-the-spot diagnosis which is desirable in applications where subsequent built-in self-repair is needed.

In this paper, we propose a parameterized digitally controlled oscillator that can produce oscillating-clock signal with the tunable frequency covering an entire designated range. Moreover, we formulate the all-digital phase-locked loop optimization process as a search problem, during which we can find a good configuration that not only meets the user-defined requirement but also achieves a smaller area and lower power consumption than a typical manual design. The silicon measurement results show that this is indeed a promising new alternative for analog phase-locked loops, especially for advanced nanometer technologies.

For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous range, and thereby reduce the jitter significantly. This scheme incorporates a new mirror-DCO-based calibration scheme to take into account process variations. We validate this scheme by test chips in 0.18-μm CMOS technology. Measurement results show that, when operating at 1 GHz, the rms jitter is 4.3 ps (0.43%UI) and the peak-to-peak jitter is 35.6 ps (3.56%UI), respectively.

A novel aurous complex containing thiourea and thiocyanate as the mixed ligands is synthesized by the ISRC method in this paper. Its formula is determined as [Au (tu)2 ]SCN H2O by elemental analysis. The electrochemistry studies show it is a typical ionic compound and its conductivity reaches 13×10-4 Sm2mol-1. TG studies and related stability tests reveal the compound is excellently stable. By using single factors experiments the optimal plating index has been gotten and they are: pH=1.5~3.5, [A =1.5~2.5 g/L, temperature 30~50°C and plating time 10 minutes respectively. It is a competitive gold complex and will be find a wide application in electroplating, chemical deposition, ceramic decoration and other related areas.

Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit.

Leakage tests have been a challenge for through-silicon vias (TSVs) in a 3-D IC. Most existing methods are still inadequate in terms of the range of testable leakage currents. In this paper, we borrow the wisdom of the IO-pin leakage test while enhancing it with two features. First, we make it more suitable for a TSV, which has a much smaller capacitance than an IO pin. Second, we support a wide range of leakage test (e.g., from 0.125 μA to 16 μA), and thereby allowing for flexible test threshold setting and leakage characterization. To achieve this goal, we present two sets of techniques-1) wait-time generation by programmable delay line, and 2) wait-time propagation with a self-timed timing control scheme to overcome the timing skew problem due to signal routing. We demonstrate that the entire scheme can be done in only logic gates, making it easy to integrate into the common design flow.

A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt–Trigger inverter, the parametric delay fault on the TSV can be characterized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32768 TSVs when the test clock is running at 10 MHz.

This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-DLL) and a Dual Locking Mechanism (DLM), this method can be used to maintain a global clock signal between two dies in a 3-D IC, and thereby enabling the synchronous 3-D IC design methodology. Unlike previous designs, ours does not need to replicate the delay of the inter-die clock wire. This property can make our scheme more adaptive to various 3-D technologies and more robust to PVT variation. Such a method has several other benefits. For example, it can accommodate the ever-increasing process variation easily through its silicon tracking ability. Simulation results indicate that it can support clock signals running up to 2.8 GHz. Silicon measurements of a test chip in a 90 nm CMOS technology show that the phase error can be locked constantly to less than 9.6 ps at a clock frequency of 600 MHz, with a peak-to-peak jitter of 9.778 ps and a power consumption of only 1.8 mW.

In this paper, we propose a method and the required architecture for characterizing the propagation delays of the through Silicon vias (TSVs) in a 3-D IC. First of all, every two TSVs are paired up to form an oscillation ring with some peripheral circuits. Their joint performance can thus be measured roughly by the oscillation period of the ring. Next, we utilize a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in an oscillation ring-a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring's period. By some following analysis, the propagation delay of each TSV can be revealed. On top of scheme, we also present an architecture that can activate the performance characterization process of each test unit - that consists of two TSVs - one at a time in a proper sequence. The area overhead is only 18.97 equivalent two-input NAND gate per TSV, by which one can gain the ability to profile the capacitances and the propagation delays of the TSVs on a 3-D IC.

Small delay defects escaping traditional delay testing could cause a device to malfunction in the field and thus detecting these defects is often necessary. To address this issue, we propose three test modes in a new methodology called AC-plus scan, in which versatile test clocks can be generated on the chip by embedding an all-digital phase-locked loop (ADPLL) into the circuit under test (CUT). AC-plus scan can be executed on an in-house wireless test platform called HOY system. The first test mode of our AC-plus scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that our method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips are more likely to fall victim to operational failure in the field. The third test mode is to extract the waveform of each flip-flop's output in a real chip. This is made possible by taking advantage of the almost unlimited test memory our HOY test platform provides, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debugging. We have successfully fabricated a Viterbi decoder chip with such an AC-plus scan methodology inside to demonstrate its capability.

In today's multi-die ICs, the die-to-die interconnects are often complicated and susceptible to various kinds of manufacturing defects and stress-induced performance degradation in the field. This phenomenon has prompted a need to perform online monitoring of the signal integrity over the die-to-die interconnects for reliability critical applications. In this work, we present a slack-time binning scheme so that one can constantly quantify the margin of a timing failure threat (TFT) occurring to a registered die-to-die interconnect. The proposed scheme attaches a Slack-Time Monitor (ST-monitor) to each Flip-Flop (FF) that receives a signal transmitted through a die-to-die interconnect under monitoring. Two techniques are introduced to enhance the traditional “Timing-Violation Checker”, namely (1) a tunable guard-band technique, and (2) an offset compensation technique. With these two techniques, one can perform online slack-time binning. Experimental results using a 90nm CMOS process show that the proposed scheme has a low area overhead of only approximately 2.35 times the area of a boundary scan cell.

In a modern multi-core SoC, the Built-In Speed Grading (BISG) of each logic core is often necessary in order to ensure an adequate operating margin for accommodating all kinds of variation (e.g., PVT variation), and to guide the dynamic VDD tuning process as well. In general, a speed grading method for a logic core can be performed by repeating a specific delay test session, (e.g., built-in self-test with the latch-off capture scheme), with varying test clock frequencies to derive the maximum operating speed of a specific core under testing. In this paper, we propose an easy-to-use speed grading method featuring a wide-range synthesizable clock generation scheme so that it can support a logic core that could be used with different supply voltages and speeds in different application domains.

A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, studies have shown that small defects in a clock tree network could lead to unexpected failures in the field and thus need to be identified during the manufacturing test. In this paper, we present a novel test method to determine if a clock network has any small delay faults. This method does not require any change of the clock network, and it is capable of detecting a delay fault as small as 50ps through outlier analysis, while locating the FFs affected by the fault.

A Programmable Phase Shifter is commonly used in a pulsed Radar SoC for controlling the timing of the transceiver. It creates a Phase-Shift Amount (PSA) proportional to a tuning code. In the heart of this design, a Generic Delay-Locked Loop (Generic DLL) is responsible for creating an arbitrarily specified delay. Even though process variation and VDD variation has been properly considered, the temperature variation is often harder to cope with. In this paper, we present a temperature tracking scheme for this purpose. Simulation results show that, the maximum phase error can be thereby reduced from 96ps at its peak down to only 12ps.

SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.

Background Scrub typhus is a clinically important endemic disease in Taiwan. The aims of this study were to analyze the clinical manifestations, laboratory data and complications of pediatric scrub typhus in eastern Taiwan. Patients and Methods We searched medical records for all patients with scrub typhus who were hospitalized between 1992 and 2002 at the Taitung branch of Mackay Memorial Hospital, Taiwan. Records of children under the age of 18 with a confirmed diagnosis were selected for retrospective review. Results During the study period, 145 patients fulfilled the diagnostic criteria for scrub typhus, of whom 106 (73%) were adults and 39 (27%) were children. The mean age of the children was 7.6 ± 4.6 years. The most common clinical manifestations of pediatric scrub typhus were fever ( n = 39; 100%), cough ( n = 28; 72%), anorexia (72%), eschar (69%), chill (67%) and lymphadenopathy (64%). The most common complications were hepatic dysfunction (77%) and pneumonitis (54%). Three children (8%) required intensive care, but the overall survival rate was 97%. One child died with multi-organ failure within 8 hours after admission. Conclusion Scrub typhus should be considered in children with fever and hepatic dysfunction, particularly in those with a history of environmental exposure in an endemic area for scrub typhus. The presence of an eschar offers an important diagnostic clue, but not for all cases. Children with scrub typhus may develop serious complications and may even die if appropriate treatment is not given. Doxycycline is an effective antibiotic for pediatric scrub typhus in Taiwan.

This paper presents a layout-based methodology to predict the exact physical location of a bridging defect inside a standard cell. It involves a number of techniques. First of all, most likely intracell bridging defects are identified through layout analysis and then converted into equivalent logic models. Next, we use a new defect-oriented formulation to generate test pattern for each candidate defect so as to further enhance the diagnostic resolution. Experimental results indicate that this methodology can remove 90% false defect candidates beyond gate-level diagnosis for four real designs and ISCAS'85 benchmark circuits.

A BIST-Assisted Timing-Tracking (BATT) scheme is proposed in this paper to facilitate robust read operation in an SRAM design without sacrificing any circuit performance at all. This scheme has very low area overhead since it uses commonly existing memory BIST circuit for tracking the worst-case silicon speed of the bitlines. It is also highly scalable and therefore suitable for an SRAM compiler that needs to support a wide range of different configurations. Measurement results of 8 manufactured chips of a 2 K-bit SRAM design using TSMC 0.18-mum CMOS technology demonstrate that it can indeed rescue one originally failing chip, while still warranting correct functionality of all the other seven chips, even under some injected variations in which conventional schemes may fail badly.

A conventional latch-type sense amplifier in a static random access memory (SRAM) could trigger sensing failure under severe process variation. On the other hand, a traditional current-mirror sense amplifier could consume too much power. To strike a good balance, this paper presents an automatic-power-down (APD) sense amplifier, which can avoid sensing failure while keeping the power dissipation low. In this scheme, the operation window of the sense amplifier is adaptive to the real silicon speed of its associated column through Schmitt-Trigger-based dual-V HL APD circuitry. A 64-kb SRAM design using the proposed technique in a 22-nm predictive technology model demonstrates that a power savings of 28%-87% over the traditional current-mirror sense amplifier is achievable.