151. Shader-based tessellation to save memory bandwidth in a mobile multimedia processor
- Author
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Chung, Kyusik, Yu, Chang-Hyo, Kim, Donghyun, and Kim, Lee-Sup
- Subjects
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CELLULAR automata , *BANDWIDTHS , *MULTIMEDIA systems , *COMPUTER storage devices , *MATHEMATICAL logic , *VERY large scale circuit integration , *INTEGRATED circuits - Abstract
Abstract: In this paper, we propose an architecture of tessellation hardware to save memory bandwidth in a mobile multimedia processor. To reduce the implementation overhead, floating-point computations of tessellation are accelerated by the conventional GPU pipeline, and only tessellation-specific control logic is handled by an additional hardware unit. Tightly coupled with a vertex shader, the additional unit dynamically produces topological configurations and parametric coordinates of refinement patterns in the type of indexed triangle strips for object-level adaptive tessellation. The topological configurations improve the efficiency of the vertex cache so as to avoid redundant shader operations. Since the proposed tessellator is area-efficient and does not require intermediate memory accesses, its architecture is especially appropriate for the mobile environment, which adopts a shared bus and unified external memory architecture. The proposed tessellator is fabricated on a chip using 0.18μm CMOS technology. With 6.2% additional hardware for a dual-core vertex shader, the implemented chip performs 120Mvertices/s vertex shading and saves memory bandwidth up to 250 times in tessellation. [Copyright &y& Elsevier]
- Published
- 2009
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