336 results on '"Peh, Li-Shiuan"'
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152. Enabling system-level modeling of variation-induced faults in networks-on-chips
153. DRAIN
154. CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs
155. RegReS: Adaptively maintaining a target density of regional services in opportunistic vehicular networks
156. SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS
157. Adaptive spatiotemporal node selection in dynamic networks
158. Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
159. Design of a High-Throughput Distributed Shared-Buffer NoC Router
160. In-network coherence filtering
161. Express Virtual Channels with Capacitively Driven Global Links
162. GARNET: A detailed on-chip network model inside a full-system simulator
163. Special Section on International Symposium on Networks-on-Chip (NOCS)
164. In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
165. Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
166. Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
167. Leveraging on-chip networks for data cache migration in chip multiprocessors
168. Extending open core protocol to support system-level cache coherence
169. Guest Editors' Introduction: Tackling Key Problems in NoCs
170. Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
171. Virtual Circuit Tree Multicasting
172. Thousand-Core Chips [Roundtable]
173. Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
174. A system-level perspective for efficient NoC design
175. NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
176. Toward Ideal On-Chip Communication Using Express Virtual Channels
177. Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies
178. Guest Editors' Introduction: On-Chip Interconnects for Multicores
179. Predicting link quality using supervised learning in wireless sensor networks
180. Express virtual channels
181. Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems
182. Software-directed power-aware interconnection networks
183. Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
184. Circuit-Switched Coherence
185. In-Network Cache Coherence
186. Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
187. Transport layer approaches for improving idle energy in challenged sensor networks
188. A supervised learning approach for routing optimizations in wireless sensor networks
189. Supervised Learning in Sensor Networks: New Approaches with Routing, Reliability Optimizations
190. HybDTM
191. Dynamic Framework for Building Highly-Localized Mobile Web DTN Applications.
192. SMART.
193. A new scheme on link quality prediction and its applications to metric-based routing
194. Hardware-modulated parallelism in chip multiprocessors
195. Session details: Router software
196. Software-directed power-aware interconnection networks
197. Coordinated, distributed, formal energy management of chip multiprocessors
198. A Delay Model for Router Micro-Architectures
199. MARio
200. High-level power analysis for on-chip networks
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