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Directly modulated vertical-cavity surface-emitting lasers (VCSELs) are commonly used in shortreach optical interconnect applications. To enable efficient optical interconnect transceiver systems operating at data rates up to 25 Gb/s and beyond, cosimulation environments, which allow for the optimization of driver circuitry with accurate compact VCSEL models, are necessary. A comprehensive VCSEL model, which captures thermally dependent electrical and optical dynamics and provides direct current, small-, and large-signal simulation capabilities with self-consistency, is presented. The device's electrical behavior is described with an equivalent circuit, which captures both large-signal operation and electrical parasitics, while the optical response is captured with a rate-equation-based model. Bias and temperature dependencies are incorporated into both key electrical and optical model parameters. Experimental verification of the model is performed at 25 Gb/s with a 990-nm VCSEL to study the impact of bias current level and substrate temperature. [ABSTRACT FROM AUTHOR]

While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital equalization for high data rate operation, the ADC and digital equalization power consumption is a key concern in applications that support operation over a wide range of channels with varying amounts of intersymbol interference (ISI). This paper presents a hybrid ADC-based receiver architecture which employs a 3-tap analog feed-forward equalizer (FFE) embedded inside a 6 bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer, resulting in both reduced equalizer complexity and power consumption. Fabricated in general purpose (GP) 65 nm CMOS, the hybrid ADC-based receiver occupies 0. 81\; \textmm^2 area. 10 Gb/s operation is verified for FR4 channels with up to 36.4 dB attenuation, with the proposed dynamic enabling of the digital 4-tap FFE and 3-tap decision feedback equalizer (DFE) on a per-symbol basis resulting in nearly 30 mW savings and an overall receiver power less than 90 mW. [ABSTRACT FROM PUBLISHER]

Photonic interconnects are a promising technology to meet the bandwidth demands of next-generation high-performance computing systems. This paper presents silicon photonic transceiver circuits for a microring resonator-based optical interconnect architecture in a 1 V standard 65 nm CMOS technology. The transmitter circuits incorporate high-swing (2Vpp and 4Vpp) drivers with nonlinear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 Gb/s operation, the 4Vpp transmitter achieves 12.7 dB extinction ratio with 4.04 mW power consumption, excluding laser power, when driving wire-bonded modulators designed in a 130 nm SOI process, while a 0.28 nm tuning range is obtained at 6.8 μW/GHz efficiency with the bias-based tuning scheme implemented with the 2Vpp transmitter. When tested with a wire-bonded 150 fF p-i-n photodetector, the receiver achieves -9 dBm sensitivity at a BER=10^-9 and consumes 2.2 mW at 8 Gb/s. Testing with an on-die test structure emulating a low-capacitance waveguide photodetector yields 17 μuApp sensitivity at 10 Gb/s and more than 40% power reduction with higher input current levels. [ABSTRACT FROM PUBLISHER]

A highly sensitive CMOS-based sensing system is proposed for permittivity detection and mixture characterization of organic chemicals at microwave frequencies. The system determines permittivity by measuring the frequency difference between two voltage-controlled oscillators (VCOs); a sensor oscillator with an operating frequency that shifts with the change in tank capacitance due to exposure to the material under test (MUT) and a reference oscillator insensitive to the MUT. This relative measurement approach improves sensor accuracy by tracking frequency drifts due to environmental variations. Embedding the sensor and reference VCOs in a fractional-N phase-locked loop (PLL) frequency synthesizer enables material characterization at a precise frequency and provides an efficient material-induced frequency shift read-out mechanism with a low-complexity bang–bang control loop that adjusts a fractional frequency divider. The majority of the PLL-based sensor system, except for an external fractional frequency divider, is implemented with a 90-nm CMOS prototype that consumes 22 mW when characterizing material near 10 GHz. Material-induced frequency shifts are detected at an accuracy level of 15 \ppmrms and binary mixture characterization of organic chemicals yield maximum errors in permittivity of <1.5%. [ABSTRACT FROM PUBLISHER]

ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a \BER=10^-9. Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm^2 area. [ABSTRACT FROM AUTHOR]

In subsurface drip irrigation systems (SDI), the emitter flow rate is affected by the root intrusion phenomena and by the so-called back pressure that limits the buried emitters’ outflow. This paper suggests a methodology to investigate the effect of root intrusion and back pressure in SDI performance, for different root guard emitter treatments in a 6-year experimental campaign (2018–2023), carried out in Sicily (Italy). Inlet discharges and pressure heads were collected over time, and their variations were used to quantify the effect of root intrusion in terms of local losses. The change in the SDI hydraulic performance was studied using a modified Hardy Cross method (HCM), which is suitable for lopped drip irrigation networks. The HCM applications also considered local losses and back pressure, requiring a comprehensive hydraulic characterisation of the soil to estimate accurately the factors influencing back pressure. Specifically, the influence of root intrusion in different emitters was analysed by considering the time variation of the fraction α of the kinetic head. The results showed diverse behaviours among the root guard emitter treatments. Emitters treated with different herbicides (He 1 and He 2), revealed no significant α-fraction variation over time, denoting the effectiveness of He 1 and He 2 treatments in root intrusion protection. Whilst, for Copper (Cu) and control (Ctrl) treatments, a severe decrease in emitter flow rate was observed, confirmed by high α-fraction variations over the investigated period. [ABSTRACT FROM AUTHOR]

This Special Section of the IEEE Journal of Solid-State Circuits features expanded versions of key papers presented at the 2018 Custom Integrated Circuits Conference (CICC), held in the DoubleTree Mission Valley in San Diego, CA, USA, April 8–11. [ABSTRACT FROM AUTHOR]