590 results on '"Kang, S. M."'
Search Results
152. Interconnect simulation in a fast timing simulator ILLIADS-I
153. Fas Ligand Expression on Islets as Well as Multiple Cell Lines Results in Accelerated Neutrophilic Rejection
154. An application of fixed point theorems in best approximation theory
155. Common fixed points of biased maps of type(A)and applications
156. Nucleotide substitutions within U5 are critical for efficient reverse transcription of human immunodeficiency virus type 1 with a primer binding site complementary to tRNA(His)
157. Computer modeling and simulation of the Optoelectronic Technology Consortium (OETC) optical bus
158. An efficient transistor folding algorithm for row-based CMOS layout design
159. Identification of a sequence within U5 required for human immunodeficiency virus type 1 to stably maintain a primer binding site complementary to tRNA(Met)
160. Identification and characterization of glima 38, a glycosylated islet cell membrane antigen, which together with GAD65 and IA2 marks the early phases of autoimmune response in type 1 diabetes.
161. Thymidine phosphorylase/platelet-derived endothelial cell growth factor expression associated with hepatic metastasis in gastric carcinoma
162. Construction of a type 1 human immunodeficiency virus that maintains a primer binding site complementary to tRNA(His)
163. Some fixed points of expansion mappings
164. COINCIDENCE POINT THEOREMS FOR MULTI-VALUED AND SINGLE-VALUED MAPPINGS IN MENGER PM-SPACES
165. Greguš type common fixed point theorems for compatible mappings of type (T) and variational inequalities
166. An accurate intrinsic capacitance modeling for deep submicrometer MOSFET's
167. Scalable optoelectronic ATM network for workstations
168. Modeling and simulation of hot-carrier-induced device degradation in MOS circuits
169. Interaction between NF-kappa B- and serum response factor-binding elements activates an interleukin-2 receptor alpha-chain enhancer specifically in T lymphocytes.
170. Optoelectronic integration for high-performance computing and communication
171. ILLIADS: a fast timing and reliability simulator for digital MOS circuits
172. A MODFET-based optoelectronic integrated circuit receiver for optical interconnects
173. Fast approximation of the transient response of Lossy Transmision Line Trees
174. Compatible mappings of type (a) and common fixed points in banach spaces
175. Performance-constrained worst-case variability minimization of VLSI circuits
176. A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays
177. Induction of the POU domain transcription factor Oct-2 during T-cell activation by cognate antigen.
178. Analytic transient solution of general MOS circuit primitives
179. A 10-GHz bandwidth pseudomorphic GaAs/InGaAs/AlGaAs MODFET-based OEIC receiver
180. A high-performance AlGaAs/InGaAs/GaAs pseudomorphic MODFET-based monolithic optoelectronic receiver
181. Computationally efficient simulation of a lossy transmission line with skin effect by using numerical inversion of Laplace transform
182. Metal ions cause the isomerization of certain intramolecular triplexes.
183. An analysis of inductive peaking in photoreceiver design
184. New algorithms for circuit simulation of device breakdown
185. Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation
186. Comparison of Peripheral Nerve Damages According to Glucose Control Timing in Experimental Diabetes.
187. Carbon Dioxide Storage Capacity of Organic-Rich Shales.
188. Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design.
189. An integrated layout system for sea-of-gates module generation.
190. Automated extraction of parasitic BJTs for CMOS I/O circuits under ESD stress.
191. Substrate resistance modeling and circuit-level simulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress.
192. An integrated approach to realistic worst-case design optimization of MOS analog circuits.
193. ILLIADS.
194. Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning.
195. An efficient transistor folding algorithm for row-based CMOS layout design.
196. iSMILE: a novel circuit simulation program with emphasis on new device model development.
197. A timing-driven data path layout synthesis with integer programming.
198. Fast timing simulation of transient faults in digital circuits.
199. Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.
200. Detailed layer assignment for MCM routing.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.