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In this paper we present an electronic system designed to emulate neural networks. Two major restrictions are assumed: discrete synapses (+1,0,−1) and threshold-type neurons. Drawbacks given by restrictions are solved with a more complex learning algorithm that maps real valued configurations for synapses into bipolar ones. The central unit of the system is an ASIC designed in accordance with a new sequential dynamics, which is faster and with better recall characteristics. As a result, the system designed has a fast recall phase and a large number of neurons. A handwritten OCR system is being designed.

The authors present a new learning algorithm for neural networks with discrete synaptic couplings. The main difference with respect to other previous algorithms is that it is defined in the continuous space. Its performance and features are analysed in detail.

Production and maintenance of interactive digital television (iTV) services can be a hard task due to the diversity of deployed digital television (DTV) platforms and the differences in terms of capabilities and functionalities between the receiver devices. The Digital Video Broadcasting (DVB) Portable Content Format (PCF) is a standard platform-independent service description which specifies the viewer experience in an iTV platform. It allows a unified authoring through a later transcoding to the final device. This paper proposes a workflow to produce and maintain platform-independent web-based iTV services from the application design level to the final deployed service through that standard. Moreover, this paper details the main characteristics of an implemented PCF to web-based platform transcoder, which can be applied to most IPTV and WebTV platforms.

We introduce a learning algorithm for feed-forward neural networks with synapses which can only take a discrete number of values. Taking into account the inherent limitations associated to these networks, we think that the performance of the method is quite efficient as we have shown through some simple results. The main novelty with respect to other discrete learning techniques is a different strategy in the search for solutions. Generalizations to any arbitrary distribution of discrete weights are straightforward.

Developing HW modules for standard platforms like PCs or embedded devices requires a complete system emulator availability to detect and fix bugs on developed HW, Operating Systems (OS) drivers and applications. This paper presents a set of plug-ins to an open-source CPU emulator that enables mixed simulations between platforms emulators and hardware (HW) modules described in SystemC. In this paper three plugins for QEMU are described: one for connecting TLM SystemC modules to any bus QEMU emulates, one for connecting SystemC to PCI bus for PC based platform and one plug-in for connecting SystemC to AMBA bus for ARM platforms. With this framework, it is possible to develop OS drivers at the same time HW is developed and final application tested running in this virtual platform.

Changing user scenarios demand wireless connectivity among different standards. As a result, reconfigurability is becoming a key issue in the design of future wireless terminals. In analog front-ends, reconfigurable components are very expensive in terms of design cost and area. Bandpass sampling and digital front-end solutions in general, move the ADC closer to the antenna, avoiding most of the reconfigurable analog hardware. We consider the extreme case of bandpass sampling at RF and analyze the ADC requirements for a multi-standard radio. Two different models, one based on cascade analysis and the other on time-domain simulations, are used with a representative set of emerging wireless standards to derive the ADC requirements: sampling frequency, resolution and clock jitter. This study shows that, with modest RF filtering, RF bandpass sampling will soon become a reality for low power terminals.

Simulating a NoC at the RTL level can be extremely complex, the simulation of a relatively small NoC, such as a 4 times 4 mesh, can involve observing thousands of wires on a standard HDL simulator. The facilities of JHDL to extend the simulator environment together with the possibility to fully analyze the runtime object model of the circuit offers a great opportunity to develop modules that address complex features like high level validation and performance evaluation. We present a developed tool that allows defining a NoC architecture models with some flexibility. Traffic generation processes described with high level language can be added to the model. Simulation can be used to validate the system operation on realistic conditions and get accurate values of expected performance

Developers of next generation Multi-Processor Systems-on-a-chip (MPSoC) silicon platforms used in multimedia mobile devices should design efficient systems for diverse execution time vs. energy consumption trade-offs for a given quality of service. By exploiting Dynamic Voltage and Frequency Scaling (DVFS) techniques we can obtain singular computational/power trades offs points and thus design energy efficient platforms. This paper presents a high level methodology to acquire an optimal set of working points for an MPEG-4 Single Profile (SP) Video encoder implementation. The flow starts from a MPEG-4 encoder described in C++ language which is translated to a SystemC hard/soft description which will be analyzed and further mapped into different platforms. Refined code is migrated to four different processor architectures: a processor research framework (CRISP-Trimaran), a soft core processor with specific functional units implemented on an Altera FPGA, an ASIC and a classic DSP.

In this paper we describe the implementation in SystemC of a scalable and parametrical network on chip (NoC). The NoC, with a mesh topology and wormhole routing, is formed of resources and routers connected by channels. Each router is connected to four neighbours' routers through input and output channels. The channels of the routers have a data bus and two control signals to let a communication based on handshake. A wrapper establishes the communication between the resource and its environment converting the messages into a format appropriated for the NoC. The information is packed to be able to circulate through the NoC and it is unpacked when it arrives to the destination

Future multiprocessor system-on-a-chip (MPSoC) will need high performance and low power requirements due to user demand and limited battery life. In this paper, we take advantage of the architecture flexibility allowed by Network-on-Chip (NoC) to build a parameterizable MPEG Compressor. MPEG compressor System has been developed in synthetizable behavioural SystemC, as a flexible system divided in different tiles. Each tile can be configured as a functional block with different performance parameters in terms of power/speed/area. NoC design implements a 2D mesh with a parameterizable router implemented in high level TLM SystemC. A QoS module takes decisions on packet routing depending on macro-block encoded data (corresponding to I, P and B frames) in real time in terms of power or performance requirements.

In this paper, we study the alternatives for the implementation of any topology through a fully connected neural network. This strategy is based in the fact that, by the moment, most of the programmable VLSI neural networks implement this topology although associated computations usesdifferent strategies like analog computations, systolic or sequential digital computations. An efficient correspondence between a fully connected neural network and any other type of network can be done following one of this strategies: transparent strategies, for which the network is processed independently of its own topology as a fully connected network, and specialized strategies, for which submatrices are taken into account for the acceleration of the computations. The differences between the two strategies is basically related to the balance between the speed of the recall phase, and the complexity of the hardware. Finally we present two chips that implement a sequential dynamics with probabilistic criteria that follow the two strategies and evaluate the advantages and drawbacks of each one.

We introduce a learning algorithm for feed-forward neural networks with synapses which only can take a discrete number of values. The main novelty respect to other discrete learning techniques is a different strategy in the search for solutions which turns out to be quite effective. Generalizations to any arbitrary distribution of discrete weights are straightforward.

Time needed to set-up and send new products to the market is a crucial factor for success, so one important rule is to develop your product as quickly as you can. In the electronics world the systems normally contain some parts in HW and others in SW being the HW/SW partition a crucial issue in the cost-performance trade-off. A bad choice usually requires the redesign or remaps of some parts the system with the consequent waste of time and money. In the last years many new concepts appeared for the design of systems, with the called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and that can be automated (through systems synthesis). Demonstrator based MPEG video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 I ITU-T H.262H (also know as "MPEG2 Video"), for the main profile at main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures.

In complex reconfigurable systems on chip, the dynamism of targeted applications requires an efficient management of platforms. To enable run-time resource management, operating system and reconfigurable SoC platform should be developed together. In this context, additionally to the issues inherent to hardware and software design development, we have to deal with the supplementary difficulty of the interaction between software and hardware, and of both with the platform. In this paper we present a real-time debugging tool operating in a mixed hardware and software environment. This dynamically loadable tool seriously decreases the time required for debugging while the overhead in terms of additional code is minimal.

In this paper a rapid prototyping design flow is presented and applied to a prototype of the base-band physical layer of a Hiperlan/2 WLAN transceiver. This physical layer is a high performance multi-rate system that contains computationally intensive algorithms. A new method for prototyping the design flow and verifying the process is to use the latest generation of system level design environments (visual data flow environment) for DSPs. The System Generator and Matlab/Simulink tools form a visual data flow environment for FPGA allow us to model DSP systems and explore algorithms. This environment also translates designs into hardware implementations that are faithful, synthesizable and efficient, which can be explored and refined in rapid prototyping platforms.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In this article we present a study and the corresponding implementation of low cost printed antennas in the 2,4GHz band. These antennas work with low cost transceivers that give a FR input/output signal in the band of interest. The work is part of a project in the field of sensor networks using technology such as Zigbee or even simpler and cheaper systems. We have focused our attention on parameters such as the antenna impedance, which is very important for achieving maximum power transfer with the transceiver while avoiding adaptation circuits. We are also interested in avoiding balums. We have analyzed these printed antennas in terms of their efficiency and radiation pattern using electromagnetic simulation software. Two structures have been evaluated and compared. The first is a structure derived from a monopole and slot antenna and the second is a printed patch antenna.

Abstrac(- This paper shows the design of the IFFT module corresponding to the baseband processing of an OFDM transmitter according to the IEEE802.11a-g and Hiperlan/2 standard. This module will be included in a future OFDM demonstrator, which will be implemented into a progranunable logic device. We have used our own algorithm for IFFT computing. It is based on the recursive properties called decimation. This algorithm offers optimal characteristics for the hardware implementation: a high degree of parallelism and exactly the same interconnection pattern between any of the algorithm stages. A new point of view in the prototyping design flow and the verification process comes from the use of the last generation system level design environments for nsP" into FPGAs. These environments, called visual data flows, are ideally suited for modeling DSP systems sinc:e they allow a high level of functional abstraction with different data types and operators.

Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottlenecks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimized application mapping.

This paper describes the configurable computing paradigm and discusses its application to real-time industrial visual inspection applications. Automated visual inspection (AVI) applications are briefly described, discussing their requirements over electronic and computing systems. Different technological alternatives usable in these systems are compared. The implementation of a complete configurable computing system is described discussing the different choices in every design step. The system is based on the PCI bus and uses a personal computer as host, with Windows95-98 operating systems. This host computer is in charge of controlling and configuring the designed hardware to map the requirements of AVI applications. The system described is structured using a modular approach that allows users to customize their system to fit the resources required by their applications.

The construction of a system that recognizes vehicle license numbers using feedforward neural networks, after the numbers have been extracted using classical methods, is described. The system is trained and tested on real-world data. In order to reduce the total amount of memory required and increase the process speed, an additional step is added to the learning algorithm that produces low precision weights (+1, 0, -1). The network obtained after this training process has a behavior similar to those networks using floating point representation for weights. A special hardware accelerator is developed to achieve high-speed recognition. >

This paper introduces a new PCI-based system targeted to prototyping implementations of image processing (IP) in computer vision applications with reconfigurable devices. The system is composed of an image digitizing board and a reconfigurable coprocessor with a new architecture for local memory. The paper describes the implementation of these two boards and discusses the design of a new functional programming environment. This environment is based on a library of parameterized modules implementing some of the most common operations in image processing. Two examples of these modules are overviewed and a new architecture for image convolution is presented.

An experiment in specifying a system benchmark in Esterel/C is presented in this paper. The selected benchmark covers a broad variety of features so that the suitability of Esterel/C to specify such systems is tested. The comparison to other system-level design languages shows the validity of this approach and envisages good chances to other approaches steaming from similar languages.

International audience; This paper deals with the implementation of control algorithms for alternative current (ac) motors using co-design methodology for hard or mixed hardware/software solutions. The authors focus on the design flow and experiments using FPGA / DSP platform. A full FPGA implementation of the well-known field oriented control strategy is presented. In a next step a mixed FPGA / DSP platform is presented associated with preliminary results concerning a mixed implementation of the scalar control algorithm.

Design verification methodologies and tool such as DRC and ERC used on MEMS design have been inherited from the transistor based analog and digital full custom design flows. However the devices are defined on a 2D layout, they have a 3D structure. Thus, current tools do not have into account the new features that appear in MEMS design, especially those related with device micro machining. The main consequence on it is that it is necessary to include information of the vertical parameters on the DRC, what is not at all usual in classical design. We claim that the inclusion of such information together with the consequent improvement of tools for DRC, ERC and device parameter extraction, can reduce design and simulation efforts as well as improve the manufacturing yield.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

This paper presents a method to automatically recognize and model singleand multi-output logic gates out of a switch-level network, even for irregular transistor structures. Resulting subcircuit models are directly used in a symbolic simulator for circuit analysis purposes. Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement.

This paper describes a reconfigurable coprocessor based on an Altera CPLD, specifically designed for a real-time computer vision system. An overview of the system is given and the architecture of the coprocessor is described, discussing the utility of its distributed memory organization for image processing applications.

The evolution of microeletronic design techniques implies an important methodological effort to increase the degree of abstraction far from technology and devices. This process is not uniform and depends on the specific electronic domains. As for sensors and actuators, there has been quite a few approaches toward this global system design methodologies, and most of them in the last years. The main points for this relative delay are: non-standard technological processes specially in case of embedded microsystems, different types of analysis required, that use different environments for each magnitude (mechanics, flow, magnetic,..), connection between circuit and structural 3D simulators, whose representations need to be abstracted by introducing the concept of sensor cell libraries, to estimate performance in the global system (large areas, signal sensitivities, mechanical restrictions,...). In the paper, we show the choices we select for these decisions in the case of a new microsystem fabrication process for embedded microsystems, developed together with the tool and design methodology, based on the 1.0µm CMOS from ATMEL-ES2. Some demonstrators are presented, together with measurement results.

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We propose a design and technology methodology and CAD tools for a microsystems fabrication based on the 1.0 micrometers CMOS from ATMEL-ES2. In order to profit from vendor cell libraries, design kits have to be enhanced to deal with the new conception environment. Main contributions are, sensor dependent technology file, device modeling and automatic generation for different ranges, and adaptation of semi- custom tools (simulation environment and P and R) for complete microsystems design. A library of dedicated sensor cells is being designed using Cadence DFWII and the foundry design kit. These sensors are fabricated with the standard CMOS process plus some post-processing steps. Three levels of post-processing are considered: 1) pH-ISFET sensors fabricated using standard CMOS, 2) gas flow and radiation sensors based on thermopiles using simple post-processing. The post-processing is compatible with the foundry CMOS process. Our technology has been developed up tot he point of maximum simplification that results in the use of only one additional mask for back-side etching. Passivation layer together with oxide windows are used for front-side etching with excellent results.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Real-time optical processing is an area of increasing interest in several fields like pattern recognition and inspecting tasks. The development of Spatial Light Modulators (SLMs) capable to display a complex amplitude 2D- distribution in real-time has been very important to obtain real-time optical processors. One of the biggest challenges for improving these processors is to obtain SLMs with a pixel-by-pixel control, which could be easily implemented and fully controlled spatially and with grey-level addressing. Liquid Crystal Displays (LCDs) are inexpensive and suitable SLMs for recognition optical purposes. The LCD panels from the Epson VP100PS videoprojector have been deeply characterized and intensively used as SLMs in optical correlators for pattern recognition. The SLMs can be used in the filter plane as well as in the input plane. If the input image to analyze entails particular requirements in spatial resolution and grey level quantization the response features of the SLM used to display the input image can be critical. In this work we present a full pixel-by-pixel control of the matrix with a PC board. A Field Programmable Gate Array (FPGA) is designed to control a PC board as a prototype to implement a Very Large Scale Integration ASIC driver using the 2.5 microns technology available from the Centro National de Microelectronics (CNM-CSIC, Bellaterra, Spain). The project results in an inexpensive and easy- reconfigurable PC board with the FPGA prototype, and an easy migration to a fully integrated driver of the display.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

This paper presents a symbolic method to detect short and open circuit faults in switch-level networks. Detection and fault sensitization vector determination are possible since the behavior of each node is described by a set of two functions: the on-set and the off-set functions. Their analyses provide designers with an efficient tool for circuit verification and test pattern generation.

This paper describes the construction of a system that recognizes vehicle license numbers using feed forward neural networks, once they have been extracted using classical methods. The system has been trained and tested on real-world data. In order to reduce the total amount of required memory and increase the process speed, an additional step has been added to the learning algorithm, that produces low precision weights {+1,0,−1}. The network obtained after this training process has a similar behaviour to those networks using a floating point representation for weights. A special hardware accelerator has been developed to achieve high speed recognition.

In this model, the human cochlea is divided into six equal sections; the acoustic wave is studied in one section. The aim of the circuit is an implementation of the equations from the model. In order to make all the necessary operations, the arithmetic unit is able to do products, additions and transferences between registers and memories. >

Nowadays industrial monoprocessor and multipro- cessor systems make use of hardware floating-point units (FPUs) to provide software acceleration and better precision due to the necessity to compute complex software applications. This paper presents the design of an IEEE-754 compliant FPU, targeted to be used with ARM Cortex-M1 processor on FPGA SoCs. We face the design of an AMBA-based decoupled FPU in order to avoid changing of the Cortex-M1 ARMv6-M architecture and the ARM compiler, but as well to eventually share it among different processors in our Cortex-M1 MPSoC design. Our HW- SW implementation can be easily integrated to enable hardware- assisted floating-point operations transparently from the software application. This work reports synthesis results of our Cortex-M1 SoC architecture, as well as our FPU in Altera and Xilinx FPGAs, which exhibit competitive numbers compared to the equivalent Xilinx FPU IP core. Additionally, single and double precision tests have been performed under different scenarios showing best case speedups between 8.8x and 53.2x depending on the FP operation when are compared to FP software emulation libraries.

This paper describes a 12-bit current mode digital to analog converter. Circuit topology uses two arrays of 64 equal current sources, each one generating both the current associated to six bits, corresponding to either MSB or LSB parts. The main novelty of that topology is the method used to limit the maximum current provided by the LSB block, which ensures a monotonic behavior of the system. The circuit has been designed and fabricated using a 0.35 /spl mu/m CMOS process and occupies an area of 0.17 mm/sup 2/.

In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and can be automated (through systems synthesis). A MPEG demonstrator based on video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 | ITU-T H.262H (also know as "MPEG2 video"), for the main profile and main level (720/spl times/480, 30 fps). The encoder implements frames I or I-pictures. It has been developed a MPEG compressor based on DCT (discrete cosine transform) through two different methodologies. First one, it is based in Matlab DSP builder from Altera that is a down up methodology, based on component instantiation. And the other, it is a top down methodology based on behavioural SystemC description and synthesized with SystemC behavioural compiler from synopsys.

Semantic Search and Ontologies are one of the key technologies that can improve content management. Nonetheless, in order to be widely diffused, these technologies lack real-time capabilities, that speed up both the indexing and the retrieval processes. This contribution presents the approach and strategy proposed to tackle this problem, within the Spanish project E-Sentencias; a project for the development of a management system for lawyers that includes documentation and multimedia related to the management of their legal cases

Memory organization has proven to be a key point when implementing image processing (IP) algorithms due to the changes in data formats along the process. The latency produced by memory access is in most cases responsible for the failure in achieving the temporal requirements of real time processing. We review the different memory organizations in real word real time image processing systems, and introduce a library of memory controllers designed to optimize memory access in a system devoted to prototyping these kinds of applications. This system was designed to be embedded in a PCI based computer and has an architecture specially designed to give support to a wide number of processing schemes, allowing the user to store images in its distributed local memory with different organizations. Our library of controllers allows users to optimize memory access for specific image sizes and pixel resolutions, and to store data in different organizations.

There is some consensus that Embedded and HPC domains have to create synergies to face the challenges to create, maintain and optimize software for the future many-core platforms. In this work we show how some HPC performance analysis methods can be successfully adapted to the embedded domain. We propose to use Virtual Prototypes based on Instruction Set Simulators to produce trace files by transparent instrumentation that can be used for post-mortem performance analysis. Transparent instrumentation on ISS kills two birds in one shot: it adds no overhead for trace generation and it solves the problem of trace storage. A virtual prototype is build to generate OTF traces that are later analyzed with Vampir. We show how the performance analysis of the virtual prototype is valuable to optimize a parallel embedded test application, allowing an acceptable speedup factor on 4 processors to be obtained.