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Acne vulgaris is a common skin disease that is difficult to treat due to its multifactorial etiology. The presence of sebum and keratinocytes within the hair follicle often prevent medication from penetrating deep into the follicle where the causal bacteria are to be found. Medications able to penetrate into the follicle are often irritating to the skin. Recently, a technology has been developed that can penetrate sebum and deliver medication deep in the follicle while also being gentle on the skin. This novel microgel complex is therefore a critical next step in the treatment of acne and also an important tool for people who suffer from a lower quality of life due to persistent acne breakouts.

Plasma process induced damage (PID) to thin gate oxide of different thickness was investigated in this paper with antenna test structures to enhance the effect of plasma charging. Gate leakage under Fowler-Nordheim (F-N) stress, threshold voltage, and time dependent dielectric breakdown (TDDB) was applied for gate oxide degrading measurement. It is found that gate oxide with around 5nm electrical oxide thickness (EOT) is more sensitive to plasma process and can be easily revealed with gate leakage. Gate oxide TDDB test with short loop wafers indicated that contact (CT) etching stop layer and back end of line (BEOL) process, especially high density plasma (HDP) chemical vapor deposition (CVD) of inter-metal-dielectric (IMD) plays the main role in oxide damage. These phenomena provide important approaches to reduce PID effect in integrated circuit manufacturing.

In this paper, a realistic atomic model is used to study the atomic ordering effect on electronic structures of Si 0.5 Ge 0.5 . The hybrid density functional theory (DFT), HSE06, is chosen as the methodology. The calculated bandgap and effective masses of Si and Ge at various symmetry points are first validated by the reported experimental data and empirical pseudo-potential method (EPM) calculations. The study of two different Si 0.5 Ge 0.5 atomic configurations shows that the SiSi-GeGe case is more stable than SiGe-SiGe (RS2 structure). In addition, the electron effective masses of the former one are larger than those of the latter one, and those calculated by EPM with virtual crystal approximation (VCA). This large electron effective mass is attributed to the localized electron orbital of the lowest anti-bonding state in the SiSi-GeGe case which leads to a flat E-k curve. However, no obvious ordering effect on hole effective mass is found.

The ab initio work quantitatively explains the physical mechanism of threshold voltage shifts in n-type and p-type metal-oxide-semiconductor field-effect transistors with HfO 2 /Al 2 O 3 gate stack. In the study, the θ phase alumina has been chosen for better lattice matching of the (100) HfO 2 and (100) Si substrate. Using dipole correction method, the dominant dipole moment responsible for the threshold voltage shift has been identified at the interface of HfO 2 /Al 2 O 3 . Our HfO 2 /Al 2 O 3 atomic model shows the dipole moment decreases almost linearly as the alumina thickness decreases from four monolayers (13 A) to one monolayer (3 A). On account of the effects of capacitance and the dipole moment, our ab initio calculation quantitatively explains the trend and sensitivity of experimental threshold voltage shifts on n- and p-MOSFET's.

Negative shift of resistance during stress migration was observed in Cu-based, dual-damascene technologies. One significant reason is caused by via copper crushing through the barrier layer into copper trench underneath, which means that via location acts main role in large shrinking of via resistance. Besides, negative shift of via resistance is found to be increasing with baking time, which indicates that anneal effect can also play an important role in decreasing via resistance.

This paper introduces a guidance, which is displayed by a flow chart, for the process reliability data comparison of advanced semiconductor technologies. The present semiconductor manufacturing process is very complex and its quality control requirement also becomes more and more strict. Different reliability data may analyzed by different methods considering both engineering and statistical evidence so we can best assess process reliability performance not only considering the lifetime requirements. Engineering comparison method is based on fitting the reliability data with proper distribution or lifetime model and comparing the lifetime at a specified condition with 95% confidence band. We apply F-T test for two groups data and one-way ANOVA for multi-groups statistical comparisons. Practical examples are given to illustrate our proposed guidance flow.

We propose a method for construcing general sliced Latin hypercube design, intended for computer experiments. A general sliced Latin hypercube design has multiple layers, at each of which there are multiple Latin hypercube designs that can be sliced into smaller Latin hypercube designs at the next layer. The proposed method is easy to implement, capable of accommodating any number of factors and exible in run size. Such designs include ordinary Latin hypercube design and sliced Latin hypercube design as special cases. A special case of general sliced Latin hypercube design with two layers, called doubly sliced Latin hypercube design, is studied in detail, including its sampling properties. The more exible structure of doubly sliced Latin hypercube design than sliced Latin hypercube design allows more exible batch size for both collective evaluation of dierent computer models and batch sequential evaluation of a single computer model. Numerical examples are provided to show the advantage of the former over the latter.

Systematic sources of variations in factorial experiments can be effectively reduced without biasing the estimates of the treatment effects by grouping the runs into blocks. For full factorial designs, optimal blocking schemes are obtained by applying the minimum aberration criterion to the block defining contrast subgroup. A related concept of order of estimability is proposed. For fractional factorial designs, because of the intrinsic difference between treatment factors and block variables, the minimum aberration approach has to be modified. A concept of admissible blocking schemes is proposed for selecting block designs based on multiple criteria. The resulting 2 n and 2 n–P designs are shown to have better overall properties for practical experiments than those in the literature.

TCAD plays an increasingly critical role in advanced technology research and development. The areas of impact expanded to not only predicting device outcome from process input, but also to topics traditionally not addressed by TCAD.

Impact of quantum confinement on electron mobility and its stress responses for (100) and (110)-orientated single-gate (SG) and double-gate (DG) nMOSFETs is studied. Unstrained electron mobility in (110) DG nMOSFETs is found to be significantly higher than that of (110) SG devices. This paper discusses another physical explanation to the experimentally observed higher electron mobility in (110) FinFET sidewall channels as compared to that observed in planar (110) devices. It is also found that the electron mobility increases faster under uniaxial tensile stress for (110) devices than for (100) ones. The higher mobility in (110) DG devices is attributed to the lighter confinement effective mass of Δ4 valleys and the non-parabolicity of Δ2 valleys along the directions. With high enough tensile strain, DG nMOSFETs with (110) surface orientation are expected to outperform these on (100).

In this work a drift-diffusion simulator is utilized to study the electrostatics of a cylindrical gate-all-around junctionless nanowire transistor. For carrier transport properties such as carrier scattering and velocity in channel, a full band Monte Carlo is adopted to simulate non-equilibrium and ballistic behaviors. Two major cases: different S/D extension schemes and channel doping effects are examined in this study. It is observed that S/D extension underlap can benefit short-channel control and carrier velocity. In addition, channel doping is found to play an import role to increase carrier injection velocity in the junctionless nanowire transistors.

Pad residue or contaminations will strongly influence the bonding pad quality and potentially lead to further bonding pad corrosions due to chemical or electrochemical reactions. Many papers have reported that fluorine compounds remained on the bonding pads surface after bonding pads etching will easily lead to multiform corrosions on the bonding pads. In this paper, a leaf-like bonding pad defect was studied and characterized by Auger Electron Spectroscopy, Transmission Electron Microscope, Scanning Electron Microscope, Energy Dispersive X-ray Detector and so on. The top view and cross-section morphologies of the bonding pad defect were observed using SEM and TEM. And the elemental composition of the leaf-like bonding pad defect was analyzed by AES and EDX. AES surface analytical results showed that the fluorine concentration on the corroded bonding pad was much higher than that on the good one. EDX results also showed high fluorine concentration at the corroded area. From the Auger depth profiling results, it was found that the alumina at the corroded area of the aluminum bonding pad was much thicker than the normal native alumina, which might influence the bondablity of aluminum bonding pad to the package materials and lead to the potential failure of the devices. TEM cross-section observation further confirm that alumina at the corroded area was more than 80nm.

This paper reports the research of applying the worst stress condition of thick gate oxide LDMOSFET hot carrier reliability. Based on electrical characteristic and hot carrier degradation investigation, the worst stress condition selection and failure mechanism are discussed and then the reasonable stress condition is proposed in this paper.

Traditional latch-up (VDD-to-VSS) in CMOS IC's is formed by the parasitic p-n-p-n structure between VDD and VSS. In modern technologies, although the guard rings and substrate/ well pickups could efficiently overcome the latch-up failure in CMOS ICs, the latch-up failure phenomenon is still existed in many special application circuits. With mixed signal design requirements, there are more than 2 kinds of devices that are deployed in one chip to implement the design with higher voltage system on the advanced technologies with lower voltage application in the mixed-voltage process. Therefore, these comprehensive process and design approaches could provide more flexibility for the chips to be connected with older system [1-2]. A latch-up phenomenon is reported here that the latch-up current path occurs between adjacent power pins of 65nm process, IO circuit is powered by different power supplies. In this product, IO circuitry is with 3.3V and core circuitry is with 1.2V power supply. Because there is no VDD-to-VDD latch-up rule, the 3.3V n-well to 1.2V n-well space was

Stress-Memorization-Technique by Si dislocations is effective in enhancing NFET device performance [1,2]. For the first time, MD (Molecular Dynamic) simulations are applied to explain the formation mechanism of dislocations during the Solid-Phase-Epitaxy-Regrowth (SPER) process. A semi- empirical TCAD method based on lattice-KMC (L-KMC) is then developed to predict dislocation formation. The simulated dislocation positions agree well with silicon experiments characterized by TEM. TCAD simulations show that the resulting dislocations are along the [111] direction and provide ∼650MPa average longitudinal stress in channel regions, consistent with Nano-Beam-Diffraction (NBD) strain measurement. The channel stress is predicted by simulation to further increase by 1.5X after the poly-silicon gate removal step in a replacement-gate process. The dislocation SMT enhances NFET electron mobility by 25% and Ion-Ioff performance by 15%.

Ultra shallow junction with high activation is necessary to reduce source/drain resistance and enable continued device scaling. The adoption of non-planar device architectures also presents new doping profile engineering challenges due to the 3D nature of the channel and source/drain regions. Advanced doping technologies are emerging to meet the new USJ and profile engineering challenge. Due to the increasing process complexity and development cost, predictive TCAD modeling will be critical. The modeling challenges of the advanced doping technologies are discussed.

A data center is an integrated IT system housing multiple-unit servers intended for providing various application services. A significant portion of the costs associated with operating and maintaining a data center is used for heat removal. A growing trend in the IT industry is to use computer experiments to study thermal properties of data centers because the corresponding physical experimentation can be time consuming, costly, or even infeasible. This chapter presents useful statistical methods for the design and analysis of data center computer experiments.

(1993). ARE LARGE TAGUCHI-STYLE EXPERIMENTS NECESSARY? A REANALYSIS OF GEAR AND PINION DATA. Quality Engineering: Vol. 6, No. 1, pp. 21-37.

According to 2009 ITRS roadmap, advances in process technologies, introduction of new materials, and adoption of new device architectures are expected to enable CMOS scaling to 22nm node and beyond [1]. The added process complexity will likely to lead to increased process development time and cost. Predictive TCAD modeling can be invaluable to guide development direction, narrow down experimental conditions and reduce the length and number of learning cycles. Significant TCAD modeling challenges exist in comprehending new physics and developing efficient and effective methodologies. This review paper focuses on FEOL modeling and highlights major challenges in: USJ, stress and variability modeling. Existing TCAD capability gaps and model development needs are discussed.

In this work, new halo profile engineering is proposed to suppress the threshold voltage variation (σVt) caused by discrete random dopant fluctuation (RDF). An in-house 3D atomistic numerical simulation tool is utilized to assess nMOSFETs σVt caused by RDF for a HK/MG process. The results show that σVt can be effectively suppressed by 10% by optimizing rotation and tilt angles of the halo implant.

Quantifying the mechanical properties of nanomaterials is challenged by its small size, difficulty of manipulation, lack of reliable measurement techniques, and grossly varying measurement conditions and environment. A recently proposed approach is to estimate the elastic modulus from a force-deflection physical model based on the continuous bridged-deformation of a nanobelt/nanowire using an atomic force microscope tip under different contact forces. However, the nanobelt may have some initial bending, surface roughness and imperfect physical boundary conditions during measurement, leading to large systematic errors and uncertainty in data quantification. In this article, a statistical modeling technique, sequential profile adjustment by regression (SPAR), is proposed to account for and eliminate the various experimental errors and artifacts. SPAR can automatically detect and remove the systematic errors and therefore gives more precise estimation of the elastic modulus. This research presents an innovative approach that can potentially have a broad impact in quantitative nanomechanics and nanoelectronics.

Identifying promising compounds from a vast collection of feasible compounds is an important and yet challenging problem in the pharmaceutical industry. An efficient solution to this problem will help reduce the expenditure at the early stages of drug discovery. In an attempt to solve this problem, Mandal, Wu and Johnson [Technometrics 48 (2006) 273--283] proposed the SELC algorithm. Although powerful, it fails to extract substantial information from the data to guide the search efficiently, as this methodology is not based on any statistical modeling. The proposed approach uses Gaussian Process (GP) modeling to improve upon SELC, and hence named $\mathcal{G}$-SELC. The performance of the proposed methodology is illustrated using four and five dimensional test functions. Finally, we implement the new algorithm on a real pharmaceutical data set for finding a group of chemical compounds with optimal properties., Comment: Published in at http://dx.doi.org/10.1214/08-AOAS199 the Annals of Applied Statistics (http://www.imstat.org/aoas/) by the Institute of Mathematical Statistics (http://www.imstat.org)

New types of designs called nested space-filling designs have been proposed for conducting multiple computer experiments with different levels of accuracy. In this article, we develop several approaches to constructing such designs. The development of these methods also leads to the introduction of several new discrete mathematics concepts, including nested orthogonal arrays and nested difference matrices., Comment: Published in at http://dx.doi.org/10.1214/09-AOS690 the Annals of Statistics (http://www.imstat.org/aos/) by the Institute of Mathematical Statistics (http://www.imstat.org)

A smooth response surface (SRS) algorithm is developed as an elaborate data mining technique for analyzing gene expression data and constructing a gene regulatory network. A three-dimensional SRS is generated to capture the biological relationship between the target and activator-repressor. This new technique is applied to functionally describe triplets of activators, repressors, and targets, and their regulations in gene expression data. A diagnostic strategy is built into the algorithm to evaluate the scores of the triplets so that those with low scores are kept and a regulatory network is constructed based on this information and existing biological knowledge. The predictions based on the identified triplets in two yeast gene expression data sets agree with some experimental data in the literature. It provides a novel model with attractive mathematical and statistical features that make the algorithm valuable for mining expression or concentration information, assist in determining the function of uncharacterized proteins, and can lead to a better understanding of coherent pathways.

There are numerous books on the design of experiments. However, this book by Wu and Hamada clearly stands out from its peers. There are several features that make it a very special book on experime...

Traditionally, to assess reliability lifetimes and to evaluate reliability performance of semiconductor devices and chips, we test the samples to their failures. This can be called the "Test-to-Fail" scenario, which usually takes a long time (e.g., longer than a week). The Test-to-Failure scenario is required especially at the qualification stage, whose objective is to obtain the lifetimes of, e.g., devices, dielectrics, and metal lines. Due to the long test times, this approach is inadequate for reliability monitors, which need to be completed in a much shorter period of time so the product shipment will not be delayed and, if failed, timely corrective actions can be taken. Therefore, we are in urgent need of a much more efficient method to judge if the monitor meets reliability requirements. The "Test-to-Target" reliability test methodology perfectly matches such demand by only stressing the samples to much shorter times and can be applied on most common reliability tests like NBTI (Negative Bias Temperature Instabilities), HCI (Hot Carrier Injection), TDDB (Time Dependent Dielectric Breakdown), Isothermal EM test, and IMD (Inter Metal Dielectric) Vramp test. The corresponding specs for the Test-to-Target approach are defined based on the baseline records from the former complete Test-to-Fail reliability tests. From practical exercises after a long time, we prove the Test-to-Target methodology a truly useful approach particularly effective for reliability monitors, inline reliability assessments, process change management, nonconformance dispositions, and tool releases.

We develop a combinatorial condition necessary for the existence of a saturated asymmetrical orthogonal array of strength 2. This condition limits the choice of integral solutions to the system of equations in the Bose-Bush approach and can thus strengthen considerably the Bose-Bush approach as applied to a symmetrical part of such an array. As a consequence, several nonexistence results follow for saturated and nearly saturated orthogonal arrays of strength 2. One of these leads to a partial settlement of an issue left open in a paper by Wu, Zhang and Wang. Nonexistence of a class of saturated asymmetrical orthogonal arrays of strength 4 is briefly discussed.

Measurements made on heavily doped n-channel accumulation-mode planar metal-oxide-semiconductor field-effect transistors (MOSFETs) reveal that the channel mobility can reach values significantly higher than the bulk mobility at the same doing level. This effect is attributed to a screening effect: in the accumulation channel, the high concentration of the majority carriers brings about an electrostatic screening effect that reduces impurity coulomb scattering. As a result, mobility values that can reach twice the value expected in the bulk material are observed in the accumulation channel.