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The introduction of OS-2 has given rise to a great deal of misinformation, including the idea that the existence of the Unix system makes OS-2 unnecessary. This is untrue. In reality, OS-2 and Unix are systems with completely different goals, characteristics and market niches and they should not be viewed as competitors. The Unix system was designed to support multiuser applications and its enforcement of interprocess and inter-user protection is strict. OS-2, on the other hand, was designed as a single-user operating system, so its philosophy of protection is very different. Software developers may find that they need to bypass OS-2 and take control of a peripheral device, especially in the case of graphics applications that are not written to run in a Presentation Manager window or that rely on video display modes. Instructions for writing such applications are given.

Stalking a Peripheral Interface A few years ago, the relative performance of disk drives exceeded that of CPUs. Disks provided data to CPUs faster than they could process it. Today, […]

WINGED MEMORY As the 1980s become the 1990s, single-chip processors continue to enjoy unparalleled advances in power and performance. Studying the Intel 80x86 microprocessor family, for instance, researcher Glen Myers […]

INTELLIGENT CONTROLLER TRIMS SCSI OVERHEADS As high-speed Caches and single-cycle instructions make microprocessor systems faster, the computer's data processing and semiconductor memory subsystems no longer limit system performance. Now, to […]

A bus is defined as a platform for adapting a microprocessor and I-O interfaces to an application with a set of software standards. The choice of bus can be limited when the microprocessor is used as a baseline. Multibus and VME bus are products of semiconductor manufacturers, and their use is strongly related to the use of certain microprocessors. The STD bus can adapt a wide variety of microprocessors including 16-bit devices like the 68000, 80188 and 80186.

Small Computer System Interface DURING THE PAST FEW YEARS manufacturers of small computer systems and intelligent peripheral devices realized the need for an industry standard I/O interface for their systems. […]

When choosing a digital signal processor (DSP) chip, it is important to consider interrupts, memory architectures, I-O control, and fixed- or floating-point math. DSP ICs use a Harvard-type architecture, in which program memory and data are separate. Some DSP manufacturers provide one address and one data bus for all communication with memory and I-O chips, while others provide separate buses to control separate data and instruction memories. The trade off is simplicity versus more information to the CPU per time period. Many DSP chips use pipelining to maintain high processing speed, but inherent delay is troublesome to programmers.

Knowing what your system is doing is one of the most important jobs of a system administrator. Any number of resources can become a bottleneck and keep users from getting […]

Two factors that are prompting more designers to incorporate and implement the Small Computer System Interface (SCSI) I-O bus in their designs are the increased user demand for SCSI in low- to mid-range applications and the performance and flexibility advantages that SCSI has to offer. Use of a standard SCSI interface permits system expansion without the addition of dedicated controller boards or without substantial software changes, and provides significant improvement in the overall speed of a system. The SCSI integrated circuits (ICs) offered by several vendors are discussed, and use of these products can help to simplify the design task. However, there are various SCSI host implementation options for different applications, and extra effort for hardware design and firmware writing will be required to take advantage of these options.

Making Micro Channel I/O Easy with EPLDs Add-in cards for personal computers with open architectures, such as IBM's Micro Channel-based PS/2, are a boon for users. Add-on cards permit more […]

Adding 32-bit performance to Multibus I systems Many Multibus I users would like to obtain more performance out of existing applications. New high speed 32-bit μPs present a very attractive […]