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The impact of key process parameters on the electrical characteristics of atomic layer deposited HfO2 films has been systematically studied with MHOS devices via capacitance–voltage (C–V) measurement. C–V hysteresis curves revealed that charge storage capacity is significantly enhanced with decreasing substrate temperature from 350 down to 150 °C and/or increasing purge time of the inert gas. The developed HfO2 trapping layer was also demonstrated by a MAHOS memory device. Improved memory window, fast program speed and good retention characteristics have been obtained. The study provides a reference for memory performance improvement of HfO2-based charge trap flash memory. [ABSTRACT FROM AUTHOR]

In this letter, the retention properties of charge trapping memory with decreased thickness of ultra-thin HfO2 charge trapping layer are investigated by Kelvin probe force microscopy (KFM) technology. Experiment results show that retention properties became worse with the reducing of HfO2 thickness and increasing of temperature. Based on total remaining charge density and lateral leakage charge density extracted from the contact potential differences, we find that vertical charge leakage acted as a dominant role of charge loss with respect to lateral charge redistribution. Furthermore, effective trap energies are extracted from KFM analysis at high temperatures and it is concluded that the suppression of lateral charge redistribution in thinner HfO2 layer results from deeper trap energies. [ABSTRACT FROM PUBLISHER]

The metal oxide solid electrolyte-based RRAM device is a promising candidate for post-Flash nonvolatile memories. The critical operation of such a device is the reset process, and the reliability study of the reset process and its physical understanding are important to RRAM development. This letter reports the observation of the unstable reset behavior in the \ZrO2-based solid electrolyte RRAM. During the reset process, the LRS resistance (RL) of the device will first reduce and then increase to reach the HRS. It is also seen that V0 (i.e., the voltage at which a decrease of RL takes place) decreases with an increase of RL. This instability might be attributed to the subsequent growth of the filament after the energy barrier is reached to overcome electrochemical reactions during the reset process. Based on these experimental results, a physical model is developed to help explain the dependence of V0 on RL, which provides an important guideline to the optimization of RRAM operations. [ABSTRACT FROM PUBLISHER]

In this letter, the insertion of a Cu nanocrystal (NC) layer between the Pt electrode and \ZrO2 film is proposed as an effective method to improve resistive switching properties in the \ZrO2 -based resistive switching memory. This Cu/\ZrO2:Cu/Cu NC/Pt memory exhibits asymmetric nonpolar resistive switching behavior, low operating voltage ( < 1.2 V), low Reset current (< \50\ \mu\A), and high uniformity of resistance switching. The switching mechanism is believed to be related with the formation and rupture of conductive filament. The NC-induced electrical field enhancement has the benefit to accelerate and control the CF formation process, thus leading to low-switching threshold voltage and high uniformity. [ABSTRACT FROM PUBLISHER]

The ferroelectric field effect transistor (FeFET) is a very promising candidate for low-power and non-volatile memory. However, the co-existing effect of ferroelectric polarization and interface charge trapping in the FeFETs is demonstrated and many efforts have been made to eliminate this charge-trapping effect, which is usually treated as a deleterious effect. In contrast, we have found that the charge-trapping effect can play a dominant role in ferroelectric gates. In this work, we have verified that the charge-trapping effect of the ferroelectric/insulator interface could induce a memory window as the main physical mechanism in the TiN/Hf0.5Zr0.5O2/SiO2/p-Si (MFIS) structure, in which the ferroelectric characteristics of HZO thin films was verified through a reverse-grown MFIS structure. We also demonstrated that 2.5 nm SiO2 is optimal for the charge tunneling effect and the device has the largest memory window. Moreover, in order to enlarge the memory window of MFIS capacitors, we utilized the stress-enhanced ferroelectric polarization characteristics of Hf0.5Zr0.5O2 to improve the charge-trapping effect. Such a finding demonstrates that the ferroelectric-aided charge-trapping devices are potential to be used in non-volatile memories. [ABSTRACT FROM AUTHOR]

In the above-named article [ibid., vol. 34, no. 7, pp. 870?872, Jul. 2013], the corresponding author is not correctly indicated. Z. Huo and M. Liu should be the authors to whom correspondence for the published letter should be directed toward. [ABSTRACT FROM PUBLISHER]

The high thermal budget of three-dimensional NAND Flash (3D NAND Flash) is the key issue limiting the increase in vertical integration. The main purpose of this article is to design a local and high temperature annealing function to reduce the thermal budget and gain a high activation rate without diffusion at a target depth to improve the performance of 3D NAND Flash devices by laser annealing with green wavelength. The method of nanosecond pulse laser annealing (ns-PLA) for amorphous silicon (a-Si) crystallization and activation has been proven, and this method has the benefits of a low thermal budget and controllable heating. According to previous experiments, one of the important results is that ns-PLA with high energy can provide a high temperature that reaches the melting point of a-Si and obtain a deep and monocrystal-like silicon channel through liquid phase crystallization in 3D NAND applications and obtain a higher activation rate. These results cast emerging light on low thermal budget processes based on ns-PLA in 3D NAND flash for future architecture such as Xtacking architecture, and have significant ramifications for impurity activation rates and reducing channel leakages. [ABSTRACT FROM AUTHOR]

The magneto-electric coupling (MEC) effect has been considered an effective method for the voltages controlled magnetic anisotropy in traditional ferroelectric/ferromagnetic structures. Unlike traditional perovskite ferroelectrics, the ferroelectric hafnium-based oxides hold great potential for use in the complementary metal oxide semiconductors (CMOS) circuit with the advantages of CMOS compatibility and easy scaled-down and lower leakage current. In this article, the MEC effects in the PtCoRu/Hf0.5Zr0.5O2 (HZO) heterostructure have been investigated using the polar magneto-optical Kerr effect microscopy and anomalous Hall effect. The major modification of perpendicular magnetic anisotropy of the PtCoRu thin film was controlled obviously within the ±4 V polarized voltages of the Hf0.5Zr0.5O2 (HZO) film, accompanying with the coercivity field and remnant magnetization significantly decreased. The Hall voltages of PtCoRu in Hall bar devices were also controlled effectively under ±3 V polarized voltages. Such a finding proposes a more optimized method for the magnetic logic gates and memories based on voltage-controlled magnetic anisotropy in future. [ABSTRACT FROM AUTHOR]

It is difficult to adjust asymmetrically saddle-shape wafer warpage resulted from high-stress material in 3D NAND Flash memory. This paper proposes a novel method that the suitable trenches on the backside of wafer is formed to improve saddle-shape warpage asymmetrically. Effects of different trench pitches, CDs and depths are studied by FEM (finite element method) simulation. This solution provides an instruction for solving warpage in 3D NAND flash memory manufacturing. [ABSTRACT FROM AUTHOR]

Channel holes (CH) and common source line (CSL) etch are two of key process challenges in 3D NAND. With the increase of stacked layers, the aspect ratio become larger than 50:1. One of key issues is CSL tilting to CH, leading to serious word-line leakage and block fail in array. In this work, it is demonstrated that trapped charges brought by CH etch process can affect the CSL slit etch process seriously, and lead to CSL tilting issue. Charging model was used to explain the phenomenon and is validated by experiments. An approach by removing the backside films for charges release via poly-Si deposition film is proposed to solve this issue. This work provides effective approach to solve the special deep trench tilting issue in 3D NAND memory processes development. [ABSTRACT FROM AUTHOR]

Cu diffusion caused by stress, current or light induced migration in Cu interconnect is the main cause of circuit failure in BEOL (Back End of Line) process. The diffusion at the Cu/cap layer interface has been widely demonstrated to be the main path of copper diffusion. The copper diffusion between the copper line and the upper cap layer is studied in this work. In order to eliminate copper diffusion and improve reliability in BEOL process, several methods are used in this work. 1. Adding the count of via above Cu line to reduce stress gradient below the via. 2. Increasing the pre-clean flow rate before depositing the via glue layer to form a self-forming film to improve adhesion of glue layer and cap layer in order to improve the uniformity of sidewall interface adhesion strength. 3. The wafer is shielded from light to reduce photochemical reactions and suppress Cu migration induced by light. Based on these optimization factors, the lowest circuit failure caused by the copper diffusion is achieved. • Several methods are used to solved copper diffusion caused by electromigration and stress migration. • Adding the count of via above Cu line to reduced stress gradient below the via. • Increasing the pre-clean flow rate to form a self-forming film to improve adhesion of glue layer • The wafer is shield form light to reduce photochemical reactions and suppress Cu migration induced by light. [ABSTRACT FROM AUTHOR]

• In this work, the influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash memory is investigated. • It is found that H rich passivation layer is dominant hydrogen source in poly-Si channel grain boundary traps (GBT) passivation, compared with hydrogen in ambience. • The degree of GBTs passivation can be improved by adjusting hydrogen content stored in dielectrics. • Besides, different interlayer films in BEOL process are found to be critical to cell device characteristics. • It is considered that BEOL film stacks can influence poly-Si GBT density and cell device characteristics during subsequent hydrogen passivation process. In this work, the influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash is investigated. Two hydrogenation methods in final passivation process are compared and hydrogen in passivation layer is found to be more effective for poly-Si grain boundary traps (GBT) passivation, according to device characteristics. Interlayer used as copper cap layer can also act as potential hydrogen diffusion source as well as final passivation layer. Besides, different interlayer films in BEOL process are found to be critical to cell device characteristics. It is considered that BEOL film stacks can influence poly-Si GBT density and cell device characteristics during subsequent hydrogen passivation process. [ABSTRACT FROM AUTHOR]

Highlights • Top select gate transistor (TSG) shows wider initial Vth distribution, and even worse after erase, in 3D NAND flash memory. • Grain boundary traps can induce a local potential barrier in offset region, which results in higher TSG initial Vth. • Random grain boundary position, leads to worse variation of TSG initial Vth. • The local potential barrier cannot be reduced by erase operation, leading to worse Vth distribution after erase. • Two methods are proposed to achieve tight distribution and improved erase uniformity. Abstract The electrical characteristics of top select gate transistor (TSG) has been investigated in vertical channel three dimensional NAND flash memory. TSG shows wider initial Vth distribution as compared with memory cells, and even worse after erase. By experimental analysis and TCAD simulation, a physical model based on grain boundary (GB) interface traps is proposed to explain the mechanism. Grain boundary traps in offset region between bit line contact and TSG can induce a higher local potential barrier in channel, which results in higher TSG initial Vth. Besides, random GB position within offset region, leads to worse variation of TSG initial Vth. Furthermore, the local potential barrier in offset region of TSG cannot be reduced by erase operation, leading to worse Vth distribution after erase. According to proposed model, two methods with optimization of offset doping energy and poly-Si GB trap passivation condition are proposed to achieve tight distribution and improved erase uniformity. [ABSTRACT FROM AUTHOR]

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG. [ABSTRACT FROM AUTHOR]

3D NAND Flash memory still suffers from many reliability issues in practice, such as endurance and data retention errors. Meanwhile, due to process variation, pages with different layers show different error characteristics even in the same block. In this paper, we firstly propose a deep neural network-based codeword error level prediction model that can effectively predict the level of codeword errors, and we consider all the main factors that affect the codeword errors, including the P/E cycles and retention time, the location information of the codeword. The new network structure can effectively reduce the weight size by approximately 27% without loss of accuracy compared to traditional neural network. Based on this prediction model, we further propose an optimized scheme to reduce the read latency of the system. The results of the model prediction can help the controller to choose a suitable decoding scheme, thus reducing the overall read latency. Experiments show that the proposed network can predict the error level of the codeword to over 97% accuracy, and also significantly help to improve the average read performance with a maximum latency reduction of 45.3%. • We explore the error characteristics and layer variations of the 3D TLC NAND flash. • We proposed a part-connected neural network to predict codeword error level. • The prediction results of network can be used to improve the LDPC decoding latency. [ABSTRACT FROM AUTHOR]

With the increase of retention time and program/erase (P/E) cycles, the reliability of 3D NAND Flash memory with large storage capacity degrades. Because of its excellent error correction capability, the low density parity check (LDPC) code has become the mainstream method for solving reliability problems in modern NAND Flash memory. However, the log-likelihood ratio (LLR) obtained by the conventional scheme is not accurate enough to guarantee decoding performance. Moreover, page bit error rate (BER) variation exacerbates LLR inaccuracy. To solve these problems, we propose a Monitor-Units BER Calibrated LDPC (MBCL) algorithm, which adds additional data as monitor units (MUs) to monitor the change of BER in pages and get more accurate LLR values. On this basis, we propose an All State BER Estimation LDPC (ABEL) algorithm to utilize the BER obtained by MUs to estimate the BER of all other voltage states. It reduces the storage overhead of the MBCL algorithm. Compared with the conventional LDPC scheme, the proposed algorithms extend the lifetime by up to 5.83 times and reduce the decoding iterations by up to 78.63%. • We explore the effect of page variation on bit error rate (BER). • We explore the remodeling of threshold voltage distribution by Monitor Units (MUs). • The page BER variation is taken into account in the LDPC decoding process. • An algorithm that utilizes the MUs to assist LDPC decoding is proposed. • Another algorithm based on the BER relationship between different states is proposed. [ABSTRACT FROM AUTHOR]