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A two-channel 10bit 80MHz current-steering D/A converter is designed and realized. An architecture of 6+2+2 segments is selected for high linearity and dynamic performance, and also for area and performance trade-off. To further improve its static and dynamic performance, the current source array is optimized, current switches and the distribution of clock are well considered. This circuit is implemented in 0.18mum CMOS process. The measured DNL and INL are 0.35LSB and 0.6LSB respectively. The total power is 23mW under 1.8 V supply voltage

A capacitive step-down converter in 0.25 mum CMOS using a linear mode pre-regulator is presented. The linear pre-regulator operates both in pulse frequency mode under low load conditions and in current mode under high output load. In pulse frequency mode the pre-regulator limits the charge current of the capacitor network improving the electromagnetic compatibility. Under high load conditions the converter operates in a current mode which means that the switched capacitors are clocked with a fixed duty cycle ratio and the regulation of the output voltage is performed by the pre-regulator

A 3.125Gbit/s clock and data recovery (CDR) circuit is described. The circuit adopts parallel structure to recover clock from high-speed data stream. The working clock is reduced by this method and lower power is achieved. Timing jitter has been considered carefully and the loop parameters are optimized to reduce the output jitter. The circuit is designed with 0.18/spl mu/m CMOS process: the simulated function and performance meet the requirements and the core power dissipation is 56mW.

A new structure proposed in this paper, which synthesizes a half-band filter by multiple use of the subfilters saves the hardware cost greatly. Then the coefficient optimization based on simulated annealing algorithms is developed and it obtains better the frequency response performance of the filter than the coefficient optimization based on greedy algorithms, such as local search.

A broadband programmable gain amplifier (PGA) with a small gain step and low gain error has been designed in 0.13 μm CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error. The proposed PGA shows a decibel-linear variable gain from −4 to 20 dB with a gain step of 0.1 dB and a gain error less than ±0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.

This paper describes a low-power portable sensor interface dedicated to sensing and processing electrocardiogram (ECG) signals. Dry electrodes were employed in this ECG sensor, which eliminates the need of conductive gel and avoids complicated and mandatory skin preparation before electrode attachment. This ECG sensor system consists of two ICs, an analog front-end (AFE) and a successive approximation register analog-to-digital converter (SAR ADC) containing a relaxation oscillator. This proposed design was fabricated in a 0.18 μm 1P6M standard CMOS process. The AFE for extracting the biopotential signals is essential in this ECG sensor. In measurements, the AFE obtains a mid-band gain of 45 dB, a bandwidth from 0.6 to 160 Hz, and a total input referred noise of 2.8 μV rms while consuming 1 μW from the 1.8 V supply. The noise efficiency factor (NEF) of our design is 3.4. After conditioning, the amplified ECG signal is digitized by a 12-bit SAR ADC with 61.8 dB SNDR and 220 fJ/conversion-step. Finally, a complete ECG sensor interface with three dry copper electrodes is demonstrated in real-word setting, showing successful recordings of a capture ECG waveform.

A wideband receiver RF front-end for IR-UWB applications is implemented in 0.13 μm CMOS technology. Thanks to the direct sub-sampling architecture, there is no mixing process. Both LNA and VGA work at RF frequencies. To optimize noise as well as linearity, a differential common-source LNA with capacitive cross-coupling is used, which only consumes current of 1.8 mA from a 1.2 V power supply. Following LNA, a two-stage current-steering VGA is adopted for gain tuning. To extend the overall bandwidth, a three-stage staggered peaking technique is used. Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6–7 GHz, a minimum noise figure of 4.5 dB and a largest IIP3 of −11 dBm. The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm2 area.

A gated ring oscillator (GRO) based time-to-digital converter (TDC) is presented. To enhance the resolution of the TDC, a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2. The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm2. According to the measurement results, the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range, the maximum clock frequency of this circuit is larger than 200 MHz. Under a 1 V power supply, with a 200–800 ps input time difference, the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

A 10 MHz ripple-based on-time controlled buck converter is presented. A novel low-cost dual ripple compensation, which consists of coupling capacitor compensation and passive equivalent series resistance compensation, is proposed to achieve a fast load transient response and robust stability simultaneously. Implemented in a 2P4M 0.35 μm CMOS process, the converter achieves fix-frequency output with a ripple of below 10 mV and an overshoot of 10 mV at 400 mA step load transient response. With width optimization of the power transistors in an ultra-heavy load and PFM control in a light load, the efficiency stays at over 83% for a load range from 20 mA to 1.5 A and the peak efficiency reaches 90.16%.

A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented. It features a selectable interpolation rate (2x/4x/8x) with a programmable interpolation filter. To improve the high-frequency performance, a "fast switching" technique that adds additional biasing to the current-switch is adopted. The data-dependent clock loading effect is also minimized with an improved switch control by using a double latch. This DAC is implemented in 65 nm CMOS technology with an active area of 1.56 mm2. The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal, respectively.