Search

In this work a resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results are presented for two CMOS processes, XFAB 0.18 μm and IBM 0.13 μm. Experimental results from one fabrication run demonstrate a reference voltage of 570 mV, with a temperature coefficient as low as 11 ppm/°C for the 0-125 °C range, while the power consumption of the whole circuit is 5 nW under a 0.9 V supply at 27 °C. The occupied silicon area is 0.0022 mm $$^2$$ . [ABSTRACT FROM AUTHOR]

A 50 MHz-1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network is presented. It was implemented without any inductor and offers a differential output for balun use. Noise canceling and linearity boosting techniques were combined to improve the amplifier performance in such a way that they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 μm × 71 μm area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain >23.7 dB (power gain >19.1 dB), a NF <3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) >3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S <−16 dB. When optimized for best NF, it achieves a voltage gain >24.7 dB (power gain >19.8 dB), a NF <2 dB over the entire band, an IIP3 >−0.3 dBm and an S <−11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range −55 to 125 °C was observed for Gain, NF and S11. Power consumption is 18 mW under a 1.2 V supply. [ABSTRACT FROM AUTHOR]

Lists the reviewers who contributed to IEEE Transactions on Electron Devices in 2013. [ABSTRACT FROM PUBLISHER]

The article looks into the new approaches of MOSFET mismatch modeling. The author points that digital and analog integrated circuits relies on the matched behavior of identically digital design for current and future submicron technologies. Significantly, the article focuses on the analysis of mismatch in MOSFET due to random fluctuations of dopant concentration. The author points out that the conventional bulk CMOS technology still dominates the microelectronics industry. The design and details of the model are presented.

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 μm technology confirm the accuracy of our mismatch model under various bias conditions. [ABSTRACT FROM AUTHOR]

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed. [ABSTRACT FROM AUTHOR]