151. A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers.
- Author
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Yu, Lilan, Miyahara, Masaya, and Matsuzawa, Akira
- Subjects
ANALOG-to-digital converters ,DATA pipelining ,ENERGY conservation ,ENERGY consumption ,ELECTRONIC linearization - Abstract
This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
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