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A strain sensor inspired by a Widlar self-biased current source topology called $\beta$-multiplier is developed to obtain a strain-dependent reference current with high supply rejection. The sensor relies on the piezoresistive effect in the silicon MOS transistors that form the current reference circuit. The device behavior is analytically computed and verified with experimental measurements under four-point bending test. A basic implementation with an integrated resistor reaches a strain sensitivity of 2.54 nA/$\mu\epsilon$ (gauge factor of 324) for a temperature sensitivity of 52.06 nA/{\deg}C. A more advanced full-transistor circuit based on current subtraction principle is furthered implemented in order to reach strain sensitivity up to 12.02 nA/$\mu\epsilon$ (gauge factor of 1773) and temperature sensitivity of -28.72 nA/{\deg}C. This implementation includes a CMOS active load to tune the strain and temperature sensitivities with a total power consumption between 20 and 150 $\mu$W.

CuO grown by room-temperature direct current reactive magnetron sputtering is introduced to realize p-type thin-film transistors (TFTs) with a high-k HfO2 gate dielectric fabricated by atomic layer deposition. The devices work in an accumulation mode (AM) with two apparent threshold voltages corresponding to the formation of a buried channel and an accumulation layer, respectively. A CuO AM TFT with a channel length of 25 μm exhibit a competitive on-off ratio ( Ion/Ioff) of 1.3 × 102, a subthreshold swing ( SS) of 1.04 V dec−1, and a field-effect mobility ( μFE) of 1.1 × 10−3 cm2 V−1 s−1 at room temperature. By measuring a CuO metal oxide semiconductor (MOS) capacitor at room temperature, a high acceptor doping density ( NA) of ∼5 × 1017 cm−3, a high positive effective fixed surface charge density ( Qf) of ∼9 × 1012 cm−2, and a low interfacial trap charge density ( Dit) of ∼6 × 1010 eV−1 cm−2 at the HfO2/CuO interface are estimated. The μFE extracted from the accumulation regime appears lower than the Hall mobility measured for a similarly processed CuO layer on glass due to the increased hole concentration in CuO TFTs, compared to a Hall concentration of ∼1014 cm−3, following the MOS process. SS appears limited by the decreased channel to gate capacitance ( Ccg) related to the buried channel in AM TFTs, parasitic capacitance to ground, and potentially very high interfacial traps at the non-passivated CuO/air interface.

This paper presents an experimental investigation of two different printed circuit board (PCB) inductive sensors, with meander and non-spiral shapes, to assess their capabilities and best orientation for corona partial discharge (PD) detection. First, simulations with the Ansys HFSS software are performed in order to evaluate the equivalent electrical circuit of the two sensors and their 2d radiation patterns. The meander sensors presented a resonant frequency of 600 MHz, while it was around 1.1 GHz for the non-spiral. The 2d radiation pattern showed that better sensitivity is achieved when the inductive sensor is oriented 90 degrees with respect to the PD source. Experimental tests showed a peak-to-peak voltage of the PD signal detected by both sensors of around 14 mV when the orientation was 90 degrees with a main frequency around 35 MHz. The peak-to-peak voltage dropped to about 5.4 mV and 6.9 mV for the meander and the non-spiral sensors, respectively, with a main frequency of about 33.5 MHz, when the orientation was 0 degrees. The obtained PRPD patterns and the PD signal shapes were quite similar to those provided by a High-Frequency Current Transformer (HFCT) commercial sensor.

This paper systematically investigates the electrical properties of thin Al2O3/SiO2 (with a target equivalent oxide thickness of 4.9 nm) as gate dielectric stack in the metal–oxide–semiconductor (MOS) capacitor. Different deposition techniques, i.e. thermal oxidation, thermal atomic layer deposition, and plasma-enhanced atomic layer deposition, are employed in the fabrication of MOS capacitors. The second derivative, Terman and conductance methods are used to extract the fixed oxide charges and interface trap densities in the MOS capacitors. Our results demonstrate that the Al2O3/SiO2 stack presents better performance in terms of negative fixed oxide charges and low interface trap density compared with the single-layer SiO2 with the similar equivalent oxide thickness about 3.9 nm. Furthermore, to evaluate the reliability of the Al2O3/SiO2 gate dielectric stack, the leakage current is analyzed. Contributions from Pool-Frenkel emission, trap-assisted tunneling, and Fowler-Nordheim mechanisms to the leakage current are detailed. Our results indicate that Al2O3/SiO2 gate dielectric stacks fabricated by plasma-enhanced atomic layer deposition Al2O3 and thermal SiO2 feature the lowest leakage current.

This paper presents the test results of an electrically small loop antenna sensor towards detecting the radiated magnetic field due to partial discharge (PD) activities. The loop antenna prototype was printed on an FR-4 substrate with a thickness of 1.6 mm, featuring a compact size of 20 mm times20 mm times1.7 mm. The proposed sensor, initially simulated with Ansys HFSS software, has a resonant frequency of about 100 MHz. Its detection capability for three types of partial discharges (i.e., corona, surface and internal PDs) has been evaluated. Laboratory experiments showed that the evaluated loop spiral antenna is appropriate for the detection of the three types of PDs. Indeed, the results show a peak-to-peak voltage equal to 22.87 mV, 74.8 mV, and 79.72 mV, respectively, for corona, surface, and internal PDs, with a frequency spectrum showing a maximum at 42.19 MHz, 16.41 MHz, and 35.1 MHz, respectively. Lastly, the performance of the proposed small loop sensor was compared to that of the commercial HFT sensor. The results show that the two sensors present comparative sensitivity for the three types of PD.

Perovskite solar cells (PSCs) are one of the most promising photovoltaic technologies. Amongst several challenges, developing and optimizing efficient electron transport layers that can be up-scaled still remains a massive task. Admittance measurements on metal-oxide-semiconductor (MOS) devices allow to better understand the optoelectronic properties of the interface between perovskite and the charge carrier transport layer. This work discloses a new pathway for a fundamental characterization of the oxide/semiconductor interface in PSCs. Inverted MOS structures, that is, glass/fluorine-doped tin oxide/tin oxide (SnO2)/perovskite are fabricated and characterized allowing to perform a comparative study on the optoelectronic characteristics of the interface between the perovskite and sputtered SnO2. Admittance measurements allow to assess the interface fixed oxide charges (Q(f)) and interface traps density (D-it), which are extremely relevant parameters that define interface properties of extraction layers. It is concluded that a 30 nm thick SnO2 layer without annealing presents an additional recombination mechanism compared to the other studied layers, and a 20 nm thick SnO2 layer without annealing presents the highest positive Q(f) values. Thus, an effective method is shown for the characterization of the charge carrier transport layer/perovskite interface using the analysis performed on perovskite-based inverted MOS devices. info:eu-repo/semantics/publishedVersion

The trade-off between mobility and stability in oxide thin-film transistors (TFTs) hinders further advances of an active-matrix flat panel display. Herein, a solution-processed bilayer active channel is designed to improve the stability and mobility simultaneously. The optical bandgap and work function of Tb:In2O3 films are modulated by tuning the film thickness and Tb concentration of Tb-doped indium oxide (Tb:In2O3) films. Large conduction band offset is achieved in a Tb:In2O3 bilayer channel, which induces accumulation of abundant electrons at the interface. The mobility is significantly improved to 38.2 cm2/V s, and the photoinduced stability of bilayer Tb:In2O3 TFTs is improved with low threshold voltage shift of 0.26 and −0.38 V under negative-bias illumination stress and negative-bias temperature illumination stress, respectively.

This paper demonstrates a procedure for total insitu recovery of on-membrane n-type MOSFET from Total Ionizing Dose (TID) defects, due to the exposure to gamma radiation. After a total dose of 348 krad (Si), several annealing steps were applied using an integrated micro-heater with a maximum temperature of 364 °C. The electrical characteristics of the transistor are recorded initially in normal conditions, after irradiation and then after each step of the thermal annealing. The electro-thermal annealing of the transistor allowed a total recovery of the original characteristics after a major shift due to radiation-induced defects. Power Spectral Density (PSD) of noise measurements showed a clear domination of the Random Telegraph Noise (RTN) behavior due to the creation of oxide defects after irradiation. After annealing, the RTN behavior vanishes with a further important decrease of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing.

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

This paper proposes a curve extraction method for I-V curves and analog figures-of-merit of self-cascode MOSFET associations (SC) using a code that exploits I-V curves of single transistors as input. The method was validated by using experimental measurements of fabricated SC and the very single transistors that compose them. The results indicate a very low error between the SC generated by the code and the measured reference for operation in saturation regime and above threshold voltage, for both the I-V curves and their derivatives. This method is then valid for the assessment of the SC structures in new technologies, avoiding experimental dedicated layouts or complex set-ups.

In this paper, measurements and simulations of miniature monopole antennas for ultra-wideband (UWB) GHz intra- and inter-chips communication and biomedical applications are presented. Folded designs on four substrates are studied: 1) standard bulk; 2) high-resistivity bulk; 3) ultra low-loss radiofrequency silicon-on-insulator (RF SOI); and 4) quartz. Among the Si-based substrates, RF SOI with its trap-rich sublayer demonstrates the best performances with the lowest RF power losses and centimetric transmission distance between antennas. Transmitted power between two antennas was measured from 0.01 to 20 GHz. Using substrate characterization of resistivity, permittivity, and loss tangent based on measured coplanar waveguide lines on the same substrates, good agreement is obtained between the return losses of simulated antennas on each substrate and numerical solutions, confirming the impact of the substrate properties. An antenna bandwidth of 680 MHz is demonstrated at 6.0 GHz meeting the criterion for UWB radio communications in the 6–10 GHz band.

This paper presents detailed RF characterization of 28-nm FDSOI nMOSFETs at cryogenic temperatures down to 77 K. Two main RF figures of merit (FoM), i.e., current gain cutoff frequency ( $f_{T}$ ) and maximum oscillation frequency ( $f_{\max }$ ), as well as elements of small-signal equivalent circuit are extracted from the measured S-parameters. Increases of $f_{\textit T}$ and $f_{\max }$ by about 85 GHz and about 30 GHz, respectively, are demonstrated at 77 K. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This paper suggests 28-nm FDSOI as a good candidate for future cryogenic applications.

In this work, the properties of the interface traps between various Al2O3/SiO2 dielectric stacks and Si substrate are investigated by the conductance method. The trap state density and energy level distribution in the silicon bandgap are extracted for four stacks fabricated by different processes. Our results indicate that the trap state density can be optimized so that Al2O3/SiO2 can be advantageous for nano-scale transistors and resistive switching memory.

${\rm{Cu}}({\rm{In}},{\rm{Ga}}){\rm{S}}{{\rm{e}}_2}$ (CIGS) is a promising light harvesting material for large-area broadband photodetection, but it has been rarely studied up to now. Here an In

In Cu(In,Ga)Se2(CIGS) thin-film solar cells, interface recombination is one of the most important limiting factors with respect to device performance. Herein, metal–insulator–semiconductor samples are used to investigate and compare the passivation effects of Al2O3and HfO2at the interface with CIGS. Capacitance–voltage–frequency measurements allow to qualitatively and quantitatively assess the existence of high negative charge density (Qf ≈ −1012 cm−2) and low interface-trap density (Dit ≈ 1011 cm−2 eV−1). At the rear interface of CIGS solar cells, these, respectively, induce field-effect and chemical passivation. A trade-off is highlighted between stronger field-effect for HfO2and lower interface-trap density for Al2O3. This motivates the usage of Al2O3to induce chemical passivation at the front interface of CIGS solar cells but raises the issue of its processing compatibility with the buffer layer. Therefore, an innovative Al2O3/HfO2multistack design is proposed and investigated for the first time. Effective chemical passivation is similarly demonstrated for this novel design, suggesting potential decrease in recombination rate at the front interface in CIGS solar cells and increased efficiency. 300 °C annealing in N2environment enable to enhance passivation effectiveness by reducingDitwhile surface cleaning may reveal useful for alternative CIGS processing methods.

This work investigates different Al2O3-based dielectric stacks for various applications, including surface passivation of solar cells and photodetectors, replacement of SiO2 gate dielectric in advanced MOSFETs. Ultra-thin Al2O3/SiO2 (3/2 nm) stacks were deposited on silicon by using different techniques. A reference sample with only a single dry-grown SiO2 layer (3 nm) was prepared for comparison purpose. The effective carrier lifetimes were measured by the contactless photoconductance decay method. The lowest surface recombination velocity was calculated to be 34 cm/s in the Al2O3/SiO2 stack. The negative fixed charge density in the stacks was extracted from C–V characteristics. Our results reveal that the effective carrier lifetimes depend on the stacks deposition techniques and conditions, and provide a guideline for optimization.

Sensitivity to low-energy photons in phase change materials enables the development of efficient millimeter-wave (mm-wave) and terahertz (THz) detectors. Here, we present the concept of uncooled mm-wave detection based on the sensitivity of IMT threshold voltage to the incident wave by exploiting the characteristics of reversible insulator-to-metal transition (IMT) in Vanadium dioxide (VO2) thin film devices. The detection concept is demonstrated through actuation of biased VO2 2-terminal switches encapsulated in a pair of coupled antennas on a Si/SiO2 substrate. We also study the behavior of VO2 switches interrupting coplanar waveguide (CPW)s. Ultimately, we propose an electromagnetic wave-sensitive voltage-controlled spike generator based on the VO2 switches in an astable circuit. The fabricated sensors show record figs. of merit, such as responsivities of around 66.3 kHz/mW with a low noise equivalent power (NEP) of 20 nW at room temperature, for a footprint of 2.5×10−5 mm2, which can be easily scaled. This solution gives 3 times better responsivity with only 1/10 footprint of the state of the art. However, the footprint is capable of being scaled down to few hundreds of nanometers. The responsivity in static measurements is 76 kV/W in the same circumstances. Based on experimental statistical data measured on robust fabricated devices, we investigate and report stochastic behavior and noise limits of VO2-based spiking sensors that are expected to form a new class of energy efficient transducers. The results highlight the capability of VO2 phase transition to serve for building electromagnetic power sensors, that can be triggered by low energy photons.

The effect of device fabrication processing conditions is often overlooked in the evaluation of the contact resistance in metal–graphene contact. In this work, we investigate the Ti–graphene contact resistance theoretically and experimentally. A compact model has been proposed to reveal and evaluate the role of different factors in controlling the value of contact resistance. A layer of oxidized Ti or polymer residues at the Ti–graphene interface has been considered to explain the reduced carrier transmission probability through the interface. Experimental results report a low contact resistance as small as 271.45 $\Omega ~\cdot \mu \text{m}$ and our model agrees with the measured values. The proposed model explains the large variation of the contact resistance reported in the literature up to date and help to improve metal–graphene contact for future applications.

In this article, we propose a self-gating radio frequency (RF) energy harvester (RFEH) for reaching a high-power harvesting efficiency (PHE) at a low incident RF power level with a high peak-to-average power ratio (high-PAPR) waveform. It includes a power switch between a cross-coupled rectifier and its supplied load to cut off the reverse leakage current in between the short power bursts. The power switch is dynamically controlled based on an indication of the ability of the RFEH to effectively charge the load at the instantaneous incident power level. This is achieved by comparing the load voltage with the open-circuit voltage of a replica rectifier. A comparator with optional proteresis (reversed hysteresis) is proposed for compensating its logic delay at the start and at the end of the short RF power bursts. As a result, the power switch is accurately turned on only during the power bursts. The self-gating RFEH was prototyped for 2.45-GHz wireless power transfer (WPT). It includes a cross-coupled rectifier with the proposed self-gating circuit fabricated in a 65-nm process, a discrete balun, a parasitic-aware-sized p matching network, and an off-the-shelf power management unit (PMU) with maximum power point tracking (MPPT). Measurement results show sensitivity as low as −26.7 dBm with a peak PHE of 32.3% at −14.1-dBm incident power. Compared with the state-of-the-art works, the proposed design significantly improves the RFEH performance at the target low average incident power.

We have developed a straightforward die-level thinning process suitable for Silicon-On-Insulator (SOI) dies. The process has been demonstrated on SOI CMOS die assembled on rigid and flexible PCBs using previously-developed anisotropic conductive adhesive flip-chip method. Unlike standard wafer-level thinning processes, in the demonstrated process the full thickness SOI die is directly mounted on PCB and after that thinned. The demonstrated process is simple and robust; it comprises fewer process steps compared to conventional die thinning process. The ultra-thinning process has no effects on the assembly integrity and device performance.

The manufacturing of modern silicon-based MEMS requires highly energy- and resource-intensive processes. Understanding and gathering objective data of the impacts of silicon manufacturing is crucial to select design strategies reducing the environmental impacts. In this work, we present a bottom-up assessment of the embodied energy and carbon footprint of two piezoresistive pressure sensors, by adapting previously published LCA data set to model the sensors process sheets. Then we use these models as generic models of pressure sensors processes to discuss their environmental impacts regarding their performances. Our results highlight that using Silicon-on-Insulator (SOI) substrates and deep reactive ion etching (DRIE) as release process could lead to a 50-fold reduction of the environmental impacts of MEMS pressure sensors regarding to their specifications.

Preventing device obsolescence in Internet-ofthings (IoT) is mandatory for its massive deployment to be ecologically sustainable. This calls for ultralow-power (ULP) reprogrammable microcontroller units (MCUs) for long lifetime, yet with sufficient computing performance to extract the meaningful information from the sensed data before transmitting it to the cloud. In this article, we present the SleepRunner MCU with logic/memory/power management co-optimization for best exploitation of the forward back biasing (FBB) capability in fully-depleted silicon-on-insulator (FDSOI) technologies. For low active power, we use ultralow-voltage (ULV) low-Vt logic with upsized gate length and asymmetric FBB, a ULP SRAM macro with low read-access energy and switched-capacitor voltage regulators (SCVRs) for ULV supply generation from a single I/O voltage. The custom ULP SRAM macro is based on an ultralowleakage (ULL) FBB-compatible bitcell for low SRAM retention power. In addition, a dual-loop digital unified frequency/backbias regulation (UFBR) system efficiently compensates process and temperature variations with short wakeup from the zero-back-bias deep-sleep mode. Performance is measured for a synthetic benchmark and biomedical inference applications. The measured 40-MHz 2.6-μW/DMIPS (3.3 μW/MHz) active and 131-nW/kB deep-sleep power consumptions with CPU state retention are respectively 3× and 2.5× lower than for a conventional MCU design in this technology. This demonstrates the interest of 28-nm FDSOI with the proposed FBB-driven system optimization for ULP MCUs. Index Terms—Adaptive process, voltage, and temperature (PVT) compensation, CMOS digital integrated circuits, fullydepleted silicon-on-insulator (FDSOI), microcontroller, nearthreshold computing, SRAM, ultralow power (ULP), ultralow voltage (ULV).

C u ( I n , G a ) S e 2 (CIGS) is a promising light harvesting material for large-area broadband photodetection, but it has been rarely studied up to now. Here an In2S3/CIGS heterojunction photodiode on steel is shown to be highly broadband photo-sensitive, with a photoresponsivity over 0.8 A/W, an external quantum efficiency over 100%, and a detectivity over 8×1010 Jones from 505 to 910nm under a reverse bias of 1 V. Moreover, the CIGS photodiode exhibits an outstanding weak light detection ability (i.e., at light power density of 20 µ W / c m 2 ), reaching a record responsivity of 2.06 A/W, an impressive EQE of 293%, and a good detectivity of 2.3 × 1 0 11 Jones at 870 nm under 1 V reverse bias. Importantly, the CIGS photodiode, working as a self-powered photodetector, under 0 V, shows a record detectivity of ∼ 3.4 × 1 0 12 Jones with a high responsivity of ∼ 0.44 A / W and a high EQE of ∼ 63 % , at 870 nm.

In this work, we assess the applicability of the well-known split CV technique for mobility extraction in 28 nm FDSOI transistors with gate length down to 25 nm using TCAD simulations. We identify the significant bias dependence of the parasitic source/drain resistance and the contribution of the inner fringing capacitance as the main sources of error in the conventional split CV extraction. An improved split CV method, correcting for these parasitics, is demonstrated to accurately extract the effective mobility and its dependence on the gate voltage for devices down to 25 nm gate length. Measurements on 28 FDSOI transistors confirm the insights from the TCAD simulations.

Silicon membrane strip photodetectors are fabricated based on thin silicon-on-insulator (SOI) wafers. The thin SOI wafer is realized by exploiting a thinning process on back-side. Such detectors can be implemented in proton-beam position detection because its ultra-thin membrane substrate can reduce beam scattering and offer the considerable advantages of a higher radiation hardness. A p-spray implantation process is typically performed at the silicon surface between the n+-strips in order to insulate them, without requiring an extra photolithographic mask. In this paper, the sources of leakage current in the detector are firstly studied by considering both activation energy and simulation analysis in Silvaco TCAD. While the device is operating below avalanche breakdown voltage, the Shockley-Read-Hall (SRH) process and trap-assisted-tunneling (TAT) process are dominantly contributing in leakage current. The dominant breakdown voltage is attributed to the premature breakdown in the junction of p-spray/n+-region. The shift of this breakdown voltage under repeated avalanche processes is analyzed in-depth by both experiments and simulations, as a function of temperature and electrical stress conditions, which are introducing an important reliability problem. The electrical stress can be attributed to an increase of fixed charge density at the Si/SiO2 interface. The breakdown voltage finally increases by 4 V after successive avalanche breakdowns as function of the applied excess bias voltage beyond breakdown voltage.

Current sensing solutions must combine an ultra-low energy consumption trend with high reliability. The challenge lies on a fine setting of the detection threshold with the assurance of a sufficient sensitivity. In this article, the uncertainty introduced on gas sensing applications by the inherent sensor noise is studied. A 1/f model of the electronic noise in polypyrrole-based ammonia (NH3) sensors is presented and used to estimate the intrinsic signal-to-noise ratio (SNR), giving an effective precision of 10.7 bits, i.e., down to 31.4 ppb in terms of NH3 concentration. No significant improvement in SNR is achieved by increasing the bias voltage and hence the power consumption.

International audience; We present a simulation strategy using ATLAS-2D to optimize the back-contact hole grid (i.e. size and pitch of openings) of the Al2O3-rear-passivation layer in ultra-thin CIGS photovoltaic cells. We first discuss and compare our simulation model with a series of experimental reference (i.e. non passivated) and passivated UT-CIGS cells to decouple the crucial parameters of the passivation. The simulation results follow the experimental trends both for the current in the dark and for the PV parameters under illumination, highlighting the beneficial effects of the passivation on the cell performances. Furthermore, it stresses the influence of the passivation quality at the Al2O3/CIGS interface and of the contact resistance at the Mo/CIGS interface within the openings. Further simulations quantify significant improvements in short-circuit current and open-circuit voltage for different sizes of openings in the Al2O3 layer, relative to an excellent passivation quality (i.e. high density of negative charges in the passivation layer). However, a degradation of performances is predicted for a poor passivation (i.e. low density of such charges) or a high contact resistance, when compared to reference cells. Consequently, we point out an optimum in efficiency when varying the opening widths at fixed hole pitch and fixed contact resistance. At equivalent contact resistance, simulations predict that the sizes of the pitch and openings can be increased without optimal performance losses when maintaining a width to pitch ratio around 0.2. This simulation trend has been confirmed by a series of experiments, indicating that it is crucial to care about the dimensions of the opening grid and the contact resistance of passivated cells apart from different material properties. These simulation results provide significant insights for optimal cell design and characterizations of passivated UT-CIGS PV cells.

Controlled oscillators are a leading option for sensor interfaces when high input dynamic range (DR) is needed. This is often met in applications like gas, temperature and strain sensing where the low level measurand is embedded in a high DC common-mode signal. Aiming for high DR and high accuracy, with low energy use, challenges the interface linearity and signal-to-noise ratio. Such performance requires the use of specific analytical tools for the design of the interface. In this article a methodology for the quantification of noise-related uncertainty in oscillator-based resistive sensor interfaces is presented. A time-domain analysis of the output oscillation is performed with the aid of classical period jitter tools and long-term stability is assessed with the Allan variance. Finally, an energetic evaluation constrained by the output requirements is carried out. As an application case, the methodology is used to evaluate the performance of a gas sensor interface confirming the need and usefulness of the proposed approach to achieve best accuracy.

We present a 2D model of an Al 2 O 3 -passivated ultrathin Cu(In, Ga)Se 2 photovoltaic cell with rear-contact pattern. Simulation results follow the experimental trends, highlighting the significant effects of the passivation quality and of the Mo/CIGS contact resistance. Improvements in Jsc and Voc are discussed for different sizes of openings, relative to an excellent passivation quality (i.e. high density of negative charges in the passivation layer). However, a degradation is predicted for a poor passivation (i.e. low density of such charges) or a high contact resistance. We point out an optimum in efficiency when varying the opening widths at fixed hole-pitch and fixed contact resistance for a width to pitch ratio around 0.2. These simulation results provide significant insights for optimal cell design and characterizations of passivated UT-CIGS PV cells.

This paper aims at comparing the tuning range of three different planar inductor layouts built on a Printed Circuit Boards (PCB), namely the spiral inductor, the nonspiral inductor, and the meander inductor. Initially, we identify the equivalent electric model for the three inductors. All models are validated theoretically by analytical equations, by simulation through Sonnet software®, and also by measurements. For the same surface occupancy, the spiral inductor presents the higher inductance value, while the nonspiral inductor has the higher quality factor and self-resonant frequency. The tunability range is investigated by placing a shielding metal plate above for all PCB inductors. The inductance value is reduced, when the air gap between the metal plate and the inductance decreases. In addition, results demonstrated that the spiral inductor has the higher range, with a variation of more than 90%, followed by the non-spiral inductor. The meander one showed a change less than one-tenth of the spiral inductor.

In this work, we discuss the I-V and low-frequency noise characteristics of on-membrane 6$\mu$m-wide 1$\mu$m-long n-MOSFETs for analog low-power sensor interfaces, in e.g. pressure or gas measurements. After MEMS processing (i.e. bulk Si Deep Reactive Ion Etching), a high power spectral density (PSD) with clear signs of Random Telegraph Noise (RTN) (with $\Delta$Id/Id as high as 40%) is observed. Cadence simulations predict lower PSD values. At the same time, the MOSFET I-V measurements show threshold voltage, transconductance and subthreshold slope discrepancies compared to simulations. In order to heal these detrimental effects of DRIE, a high-temperature in-situ thermal annealing ($T=265^{\circ}$C for 2 min) is applied. As a result, the noise power is reduced by a factor of about 10, the MOSFET electrical characteristics are also partially recovered and become close to simulations. An analytical study based on noise and current models fits the interpretation of effects linked to interface traps.