390 results on '"Daniel Grosse"'
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152. Property analysis and design understanding.
153. Contradiction Analysis for Constraint-based Random Simulation.
154. Debugging Contradictory Constraints in Constraint-Based Random Simulation.
155. Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow.
156. Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares.
157. RevLib: An Online Resource for Reversible Functions and Reversible Circuits.
158. Quantified Synthesis of Reversible Logic.
159. Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking.
160. Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
161. Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme [Quality-Driven Design and Verification Flow for Digital Systems].
162. Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques.
163. SWORD: A SAT like Prover Using Word Level Information.
164. Fast exact Toffoli network synthesis of reversible logic.
165. Exact sat-based toffoli network synthesis.
166. Improvements for constraint solving in the systemc verification library.
167. Estimating functional coverage in bounded model checking.
168. Formal Verification on the Word Level using SAT-like Proof Techniques.
169. Improving the Quality of Bounded Model Checking by Means of Coverage Estimation.
170. HW/SW co-verification of embedded systems using bounded model checking.
171. HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.
172. CheckSyC: an efficient property checker for RTL SystemC designs.
173. Acceleration of SAT-Based Iterative Property Checking.
174. Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors.
175. Checkers for SystemC designs.
176. Symbolic Error Metric Determination for Approximate Computing.
177. Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm.
178. Efficient Automatic Visualization of SystemC Designs.
179. Formal verification of LTL formulas for SystemC designs.
180. Modeling Multi-Valued Circuits in SystemC.
181. Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen.
182. BDD-based verification of scalable designs.
183. Reachability Analysis for Formal Verification of SystemC.
184. Heuristic Learning Based on Genetic Programming.
185. Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics.
186. Preliminaries
187. Introduction
188. Conclusion
189. Digital Early Security Validation
190. AMS Enhanced Code Coverage Verification Environment
191. AMS Metamorphic Testing Environment
192. AMS Enhanced Functional Coverage Verification Environment
193. Automatic TLM Fault Localization for SystemC.
194. Equivalence Checking of Reversible Circuits.
195. Debugging reversible circuits.
196. Towards Fully Automatic Synthesis of Embedded Software.
197. Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques.
198. Exact Synthesis of Elementary Quantum Gate Circuits.
199. Verbessertes virtuelles Prototyping
200. Formale Verifikation von SystemC-basierten Entwürfen durch symbolische Simulation
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