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Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multiple different FPGA clock signal path configurations are measured, and the results are presented. The influence of clock routing is identified as critical when MMCM or PLL modules are omitted. It is demonstrated that with careful resource and routing allocation, the clock signal's jitter performance does not have to be deteriorated by the absence of jitter filtering blocks. The proposed technique was implemented and verified and relative jitter performance was measured in the AMD/Xilinx Artix 7 35T FPGA platform. [ABSTRACT FROM AUTHOR]

A three-way power divider based on Bagley polygon is here reduced in dimension by applying the concept of reducing delay line length by applying open circuit stubs. Whereas this technique is known in literature, the delay line reduction is done symmetrically by placing the stub mid-line, which would imply packing issues leading to a reduced size reduction. In this contribution a theoretical development on non-symmetric reduced length delay line is carried out, allowing for a more effective size reduction of the Bagley-based power divider. Measurements on a prototype designed at 2.45 GHz occupying less than half of the area of a canonical Bagley divider with comparable performances over a slightly reduced operational bandwidth prove the validity of the approach. [ABSTRACT FROM AUTHOR]

Monitoring the condition of the aircraft actuators in various operating and environmental circumstances, this paper presents a method for measuring the surface roughness of aircraft actuators. The proposed method starts with the current and vibration signal as failure indicators and a dual-tree complex wavelet transformation (DTCWT) to generate the necessary features. Time-delay neural networks (TDNNs) have been developed for real-time performance monitoring to categorize problems and determine their severity. The simulation results show that the suggested method can accurately identify various faults. [ABSTRACT FROM AUTHOR]

In the era of developing technology, faster applications in modern electronic systems increase the demands for less energy consumption, area, power, and delay. This research paper presents various classes of parallel adders and hybrid parallel adders in academic studies. In this study, hybrid parallel collector performance criteria for the delay, area, energy, and power consumption of the proposed models were investigated comparatively. In addition, the performance results of the hybrid parallel adder tools investigated in this study regarding certain criteria are shared. According to the comparative results obtained, hybrid parallel adder circuits with less delay, area, power, and energy consumption can be designed. By looking at these results, it will be possible to make hybrid model selections by considering the data in terms of collectors of the processors to be designed for the areas to be studied. The comparative results are given in Table 1. which shows the results obtained by the researchers by conducting experiments. In this research on hybrid parallel adders, bits of all lengths were generally tried to be considered. According to the research on these parallel adders, the experimental results of hybrid parallel adders in terms of different delay, area, power, and energy are brought together and their comparative analyzes are given. [ABSTRACT FROM AUTHOR]

The interactions between marine wildlife and marine energy devices are not well understood, leading to regulatory delays for device deployments and testing. Technologies that enable marine wildlife observations can help to fill data gaps and reduce uncertainties about animal–device interactions. A validation test conducted in Galveston Bay near La Porte, Texas, in December 2022 used a technology package consisting of a tethered balloon system and three independent sensor systems, including three-band visible, eight-band multispectral, and single-band thermal to detect three marine-mammal-shaped surrogates. The field campaign aimed to provide an initial step to evaluating the use of the TBS and the effectiveness of the sensor suite for marine wildlife observations and detection. From 2 December to 7 December 2022, 6 flights were conducted under varying altitudes and environmental conditions resulting in the collection of 5454 images. A subset of the images was classified and analyzed with two collection criteria including Beaufort wind force scale and TBS altitude to assess a range of observations of a surrogate from near-shore to offshore based on pixel count. The results of this validation test demonstrate the potential for using TBSs and imaging sensors for marine wildlife observations and offer valuable information for further development and application of this technology for marine energy and other blue economy sectors. [ABSTRACT FROM AUTHOR]

In this work, a comb‐line leaky‐wave antenna with a pair of wide stubs is proposed with enhanced gain and reduced cross‐polarization. To ensure broadside scanning, three sections of transmission lines are used in the stub with the longitudinal offset. The stubs are placed half‐wavelength apart on both sides of the delay line to achieve high gain and a low‐cross polarization level. The antenna provides 46.8% impedance bandwidth with |S11| below −10 dB. The maximum measured gain and total efficiency are 18.5 dBi and 85%, respectively. The optimized broadside frequency of the leaky‐wave antenna is 10.2 GHz. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata are a new nanoscale technology that has overcame several limitations in metal oxide technology and facilitates digital integrated circuits designs. A counter is a module that is employed in various digital systems. In this study, a progressive design for a three-bit counter has been presented using T flip-flops, which try to enhance the circuit efficiency. This circuit has 110 cells and occupies 0.11 µm2 which reduces 33% of the counter area. The delay and the cost of this design are 1.5 clock cycles and 18, respectively. The simulation results illustrate 25% improvement in the circuit delay and 61% reduction in the circuit cost compare to the best prior circuit. [ABSTRACT FROM AUTHOR]

Optical digital‐to‐analog converters (DACs) are key to overcoming the enormous power consumption caused by the slowdown of Moore's Law. In previous work, an optical DAC consisting of a signal generator and an intensity converter was presented. The generating component was integrated into the device, but a higher level of device integration is desirable. An optical DAC device with a built‐in intensity converter for a 2‐bit binary phase‐shift keying (BPSK) signal is demonstrated. The integrated device consists of two delay line interferometers (DLIs) with silicon waveguides. The first is used to generate a quadrature PSK (QPSK) signal from two BPSK signals, and the second is used to convert the QPSK constellation into light intensities. Experimental results show that the 2‐bit digital codes 00, 01, 10, and 11 can be successfully converted into four different light intensities depending on their pattern at 10 Gbps. [ABSTRACT FROM AUTHOR]

A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than −40 dBc image rejection ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer is proposed. In this design, the 45° LO power splitter is composed of a Wilkinson divider, a series delay line with electrical length of 45° on one side of the divider, and a shunt 90° transmission line on the other side. This configuration is attractive because of its design simplicity and easy fabrication. Compared with the conventional techniques that utilize capacitors and inductors instead of the shunt 90° transmission line, the proposed LO power splitter can alleviate the issue of process variation. The demodulator demonstrates an IRR lower than −40 dBc from 37.5 to 41.5 GHz. In addition, conversion gain is 1.3 ± 0.9 dB from 33 to 41 GHz with 6 dBm LO power. The total direct current power consumption is 78 mW from 1.0 V supply voltage. At the modulation scheme of 4096-QAM, the proposed demodulator demonstrates 1.7% (−35.1 dB) error vector magnitude (EVM), which is very close to the EVM measurement floor 1.6% (−36 dB) of our millimeter-wave signal analyzer. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Mine Automation is the property of Industry & Mine Automation Editorial Department and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper provides a clear demonstration that a coplanar stripline (CPS) as a balanced line can act to re-establish the phase balance in the presence of phase deviation from a 180° distance between two input signal lines connected to the CPS. A half-wave delay line splitter connected to a CPS works as a balun to feed a balanced antenna, such as a quasi-Yagi antenna. This type of balun structure has been widely used to feed balanced antennas with a frequency bandwidth of up to 60%. Nevertheless, no clear explanation has been given regarding how the broadband antennas could be implemented with this type of balun structure. In this paper, through 3D EM simulations and measurements, it is shown that the half-wave delay line splitter indeed only results in the 180° phase balance at one frequency, but the subsequently connected CPS acts to recover the phase balance between the signal lines. The CPS can recover the phase balance within a phase imbalance of ~π/3, which determines the usable bandwidth of this structure. For a demonstration, with a center frequency of 10 GHz, samples of the half-wave delay line splitter connected to a CPS are fabricated and measured. [ABSTRACT FROM AUTHOR]

Summary: This paper reports the development of a reflectarray (RA) antenna using overlapping tri‐resonance phase distribution to produce enhanced bandwidth performance in X/Ku band frequencies. The RA with square aperture (24 cm) operating from 11 to 15.8 GHz is constructed using unit cells with concentric Malta cross and square ring developed on Diclad substrate isolated from the ground through a 2.5‐mm air layer. Variation in the concentric element's size along with the length of the delay line connected to the square ring offers a 518° phase range. The distribution of the 529 RA elements is done using the phase variations observed at 12, 13, and 14 GHz. The optimized design of the proposed antenna offers a simulated peak gain of 27.43 dBi at 12 GHz and a 1‐dB gain bandwidth of 38%. The experimental validation of the fabricated prototype exhibits a peak gain of 27.4 dBi at 12 GHz with a sidelobe level (SLL), and cross‐polarization level less than −15.6 dB, and −28 dB respectively, and a 1‐dB gain bandwidth of 37%. The enhanced performance characteristics of the proposed X/Ku wideband reflectarray antenna befit the uplink and downlink operations of fixed satellite services (FSS). [ABSTRACT FROM AUTHOR]

We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from −75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs' performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved root mean square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. Total on-chip power of 0.968 W was achieved using Artix-7, while 1.997 mW of power consumption was achieved using the ProASIC3L device. We worked to determine the temperature sensitivity for both FPGA devices, which could help in the design and optimization of FPGA-based TDCs for many applications. [ABSTRACT FROM AUTHOR]

Packet switching revolutionized the Internet by allowing the efficient use of network resources for data transmission. In a previous work, we introduced packet switching in quantum networks as a path to the Quantum Internet and presented a proof-of-concept for its application to quantum key distribution (QKD). In this paper, we outline a three-step approach for key rate optimization in a packet-switched network. Our simulated results show that practical key rates may be achieved in a sixteen-user network with no optical storage capacity. Under certain network conditions, we may improve the key rate by using an ultra-low-loss fiber delay line to store packets during network delays. We also find that implementing cut-off storage times in a strategy analogous to real-time selection in free-space QKD can significantly enhance performance. Our work demonstrates that packet switching is imminently suitable as a platform for QKD, an important step towards developing large-scale and integrated quantum networks. [ABSTRACT FROM AUTHOR]

We theoretically investigate influences of electronic circuit delay, noise, and temperature on write-error-rate (WER) in voltage-controlled magnetization switching operation of a magnetic-topological-insulator-based device by means of the micromagnetic simulation. This device realizes magnetization switching via spin–orbit torque (SOT) and voltage-controlled magnetic anisotropy (VCMA), which originate from the 2D-Dirac electronic structure. We reveal that the device operation is extremely robust against circuit delay and signal-to-noise ratio. We demonstrate that the WER on the order of ∼ 10 − 4 or below is achieved around room temperature due to steep change in VCMA. Also, we show that the larger SOT improves thermal stability factor. This study provides a next perspective for developing voltage-driven spintronic devices with ultra-low power consumption. [ABSTRACT FROM AUTHOR]

In this study, we discuss the application of high-stability, pulsed mode-locked lasers (MLLs) as sources of sampling signals with low jitter in wide-bandwidth, photonic analog-to-digital converters. The implementation of a promising method of increasing the sampling rate of signals with bandwidth up to 2 GHz requires systems with multispectral, repetitively pulsed sampling sequences. On account of the sensitivity of such systems to temperature changes and mechanical disturbances, the jitter of the sampling sequences increases and errors in setting the light-signal delays in the spectral channels result in the violation of pulse-repetition equidistance. Consequently, such a degradation of sampling-sequence quality decreases analog-to-digital conversion precision. The method of processing automatic control of an analog optical path using digital feedback and motorized delay lines is proposed for sampling multispectral sequence pulses equidistance improvement. The results of mathematical modeling and experimental implementation of the method in a 3-channel sampling multispectral sequence generation system with tripling of the pulses rate of the source MLL are presented. The discussed method can be applied in constructing optical sampling-based, analog-to-digital microwave photonic systems for different purposes. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Chongqing University of Technology (Natural Science) is the property of Chongqing University of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The exciting properties of multi-valued logic (MVL) in overcoming the limitations of binary systems have led to widespread research on this topic. Considering various types of MVL, quaternary logic is more compatible with the existing binary systems. This paper proposes a nonvolatile quaternary flip-flop (NQFF) based on the unique features of the carbon nanotube field-effect transistors (CNTFETs) and magnetic tunnel junctions (MTJs). The proposed NQFF utilizes Spin-Hall effect (SHE)-assisted spin-transfer torque (STT) MTJs to provide nonvolatility with lower write energy, and multi-Vt gate-all-around (GAA) CNTFETs offer higher performance. On the other side, due to the usage of a shadow latch and the design of the proposed circuit, the delay of MTJ switching does not affect the delay of the whole circuit. The simulation results show that the proposed NQFF offers 50% lower PDP when the system is idle for only 25% of its total operational time. [ABSTRACT FROM AUTHOR]

In the Industrial Internet of Things (IIoT), a significant amount of perceived data is generated from massive IoT devices, which requires timely computing for value maximization. Multi-access edge computing (MEC), which deploys computing nodes close to the data source, is a promising computing paradigm for IIoT applications. However, due to the limited computation resource, it is challenging for edge nodes to provide a low delay to massive data. In addition, the wireless transmission environment varies with IoT devices over time. Some data even cannot be uploaded to the edge server due to the worse link quality. Reconfigurable intelligent surface (RIS), which deploys passive reflecting elements between end users and base station to reflect wireless signals, is a new technique for changing the wireless transmission performance via reconfiguring the phase shift of RIS. It is beneficial to apply RIS in MEC for reducing transmission delay and achieving green edge computing. This paper considers a RIS-assisted device-edge collaborative MEC for industrial applications. We propose to minimize the energy consumption of IoT devices constrained to the delay requirements via jointly optimizing the offloading decisions between end and edge computing nodes, the phase shift of RIS, CPU resource allocation of edge server, and transmission power of IoT devices. A distributed and cooperative scheme, called RIS-assisted DAEM, which includes the DAECO and DCEM algorithms for CO and PORA subproblems, respectively, is proposed to solve the formulated problem. The simulation results have illustrated the efficiency of the proposal for energy consumption reduction constrained to the delay requirements. [ABSTRACT FROM AUTHOR]

Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications, such as lidar, radar, and artificial intelligence. Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility, and thus makes it possible to develop large-scale programmable optical signal processors. The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors. In this paper, we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches. The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers (MZCs), four Ge/Si photodetectors, four channels of thermally-tunable optical delaylines. Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step. Particularly, these waveguide spirals used here are designed to be as wide as 2 µm, enabling an ultralow propagation loss of 0.28 dB/cm. Meanwhile, these MZCs and MZSs are designed with 2-µm-wide arm waveguides, and thus the random phase errors in the MZC/MZS arms are negligible, in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly. Finally, this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities, including tunable time-delay, microwave photonic beamforming, arbitrary optical signal filtering, and arbitrary waveform generation.

Thin-film lithium niobate is an attractive platform for GHz-frequency applications in low-power RF analog signal processing, optomechanics, and quantum devices due to its high coupling, low loss, excellent optical properties, and compatibility with superconducting quantum circuits. We demonstrate aluminum interdigitated transducers (IDTs) in this platform for horizontal shear (SH) waves between 1.2 and 3.3 GHz and longitudinal waves between 2.1 and 5.4 GHz. For the SH waves, we measure a piezoelectric coupling coefficient of 13 % and 6.0 dB/mm propagation losses in delay lines up to 1.2 mm with a 300 ns delay in air at room temperature. In these high k eff 2 transducers, electrical loading gives rise to large reflections and resonances. Finite element method models and an experimental finger-pair sweep are used to characterize the role of resonance in these transducers, illuminating the physics behind the large motional admittances of these small-footprint IDTs. [ABSTRACT FROM AUTHOR]

Recent advances in the growth of aluminum scandium nitride films on silicon suggest that this material platform could be applied for quantum electromechanical applications. Here, we model, fabricate, and characterize microwave frequency silicon phononic delay lines with transducers formed in an adjacent aluminum scandium nitride layer to evaluate aluminum scandium nitride films, at 32% scandium, on silicon interdigital transducers for piezoelectric transduction into suspended silicon membranes. We achieve an electromechanical coupling coefficient of 2.7% for the extensional symmetric-like Lamb mode supported in the suspended material stack and show how this coupling coefficient could be increased to at least 8.5%, which would further boost transduction efficiency and reduce the device footprint. The one-sided transduction efficiency, which quantifies the efficiency at which the source of microwave photons is converted to microwave phonons in the silicon membrane, is 10% at 5 GHz at room temperature and, as we discuss, there is a path to increase this toward near-unity efficiency based on a combination of modified device design and operation at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements. Most of the nonlinearity of FPGA-based TDCs comes from the routing of the design. It is promising to realize TDCs using internal routing resources available in FPGAs, as these devices contain a lot of routing resources and are resistant to voltage and temperature changes. This work implements and tests a TDC based on a series of counters driven by a variable delay line that exploits the internal routing resources available in the FPGA as delay elements. A manual placement and routing technique that results in greater resolution and linearity is proposed. The time-interleaving concept is used to improve the resolution of the TDC. A measurement matrix with 512 and 1024 parallel counters is implemented on a Zynq Evaluation and Development (ZED) board. The result of the 1024-unit TDC showed that a dynamic range of 93.6 ns can be measured using a 4-bit coarse gray code counter running at a reference frequency of 171 MHz, and a resolution of 5.7 ps is achieved. The implemented TDC is low-cost, has a fast time to market, and it benefits from the abundant routing resources in the FPGA. [ABSTRACT FROM AUTHOR]

The statistical pyramid dense time-delay neural network (SPD-TDNN) model makes it difficult to deal with the imbalance of training data, poses a high risk of overfitting, and has weak generalization ability. To solve these problems, we propose a method based on the joint loss function and improved statistical pyramid dense time-delay neural network (JLF-ISPD-TDNN), which improves on the SPD-TDNN model and uses the joint loss function method to combine the advantages of the cross-entropy loss function and the comparative learning of the loss function. By minimizing the distance between speech embeddings from the same speaker and maximizing the distance between speech embeddings from different speakers, the model could achieve enhanced generalization performance and more robust speaker feature representation. We evaluated the proposed method's performance using the evaluation indexes of the equal error rate (EER) and minimum cost function (minDCF). The experimental results show that the EEE and minDCF on the Aishell-1 dataset reached 1.02% and 0.1221%, respectively. Therefore, using the joint loss function in the improved SPD-TDNN model can significantly enhance the model's speaker recognition performance. [ABSTRACT FROM AUTHOR]

This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC–6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC–6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors' knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology. [ABSTRACT FROM AUTHOR]

The recognition of human actions in videos is one of the most active research fields in computer vision. The canonical approach consists in a more or less complex preprocessing stages of the raw video data, followed by a relatively simple classification algorithm. Here we address recognition of human actions using the reservoir computing algorithm, which allows us to focus on the classifier stage. We introduce a new training method for the reservoir computer, based on "Timesteps Of Interest", which combines in a simple way short and long time scales. We study the performance of this algorithm using both numerical simulations and a photonic implementation based on a single non-linear node and a delay line on the well known KTH dataset. We solve the task with high accuracy and speed, to the point of allowing for processing multiple video streams in real time. The present work is thus an important step towards developing efficient dedicated hardware for video processing. [ABSTRACT FROM AUTHOR]

Since its first demonstration in 1995, terahertz time‐domain imaging has attracted an increasingly growing interest for its ability to reveal spectral fingerprints of materials and probe changes in refractive index and absorption, as well as detect the inner structure of complex objects via time‐of‐flight measurements. Practically, however, its widespread use has been hampered by the very long acquisition time typically required to spatially raster‐scan the object, and for each spatial point, record the field in time via a delay line. Here, this fundamental bottleneck is addressed by implementing a scanless single‐pixel imaging scheme, which sets the path for an unprecedented reduction of both system complexity and acquisition time. By properly exploiting natural wave diffraction, time‐to‐space encoding applied to terahertz point detection allows for an almost instantaneous capture of the terahertz waveforms, while multidimensional images are reconstructed via a computational approach. The scheme is a promising solution for the development of next‐generation fast and compact terahertz imagers perfectly suitable for high‐repetition‐rate laser sources. [ABSTRACT FROM AUTHOR]

The existence of an ultra-wide acoustic bandgap of novel nanophononic crystal in gigahertz (GHz) frequency ranges for a one-dimensional (1D) in the "out-of-plane" modes, and a two-dimensional (2D) in the "out-of-plane" modes is investigates. The maximum bandgap ratio up-to 141% for ultra-high frequency range of phononic crystal is also investigated. The results demonstrate that the transmission spectrum amplitude and bandgap of phononic crystal strongly agree in the same frequency region. It has been investigated that when the resonator is employed with phononic crystal the Qanchor increase from 6340 to 7.65 × 1010. So the quality Q of resonator is boost very high, and the insertion loss is reduced to 91.98% by employing the proposed nanophononic crystal to resonator. Furthermore, this work verifies the propagation of acoustic waves is completely banned through proposed nanophononic crystal, and the transmission response of this phononic crystal is also verified by delay line configurations. [ABSTRACT FROM AUTHOR]

We present a new concept of metasurface filters to preferentially extract pulsed waveforms at a constant frequency from a complex superimposed input signal. This filtering capability is realized using circuit-based metasurfaces, denoted waveform-selective metasurfaces, that behave according to the pulse duration of the incident wave. Importantly, our metasurface filters overcome a long-lasting issue of eliminating unnecessary pulses under simultaneous incidence without relying on variables that are commonly used for modulation schemes, e.g., frequency, time, and spatial variation (angular dependence). Such simultaneous filtering is made possible by integrating several types of waveform-selective metasurface unit cells with delay lines and successive interference cancellation processes. Moreover, we show that our concept can be extended to incorporating broadband signals, additional pulses, and variables used for existing modulation schemes. Our study therefore provides a higher degree of freedom to control electromagnetic waves and phenomena with possible applications including wireless power transfer and communications. [ABSTRACT FROM AUTHOR]

A single-layer reflectarray antenna working at C- and X-bands is designed in this paper. The proposed reflectarray element is mainly composed of three square rings. Four phase delay lines are attached to the outer ring to obtain the phase shift at C-band, and the inner two square rings are utilized to extend the phase range at X-band. The phase shift of the element reaches up to 375° and 560° at 5.9 GHz and 10.4 GHz, respectively. The cross-polarization level of the reflectarray is effectively suppressed by using a mirror symmetric element arrangement. To experimentally validate the proposed design, a center-fed dual-band prototype reflectarray with the size of 180 mm×180 mm is designed, fabricated, and tested. The measured peak gains are 16.5 dBi at 6.2 GHz and 17.1 dBi at 10.3 GHz, respectively. Besides, the measured 1-dB gain bandwidth is 9.15% (5.83-6.37 GHz) at the lower band and 3.27% (10.12-10.46 GHz) at the upper band, respectively. Moreover, the cross polarizations at both bands are under -21 dB. [ABSTRACT FROM AUTHOR]

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The recent compute-in-memory (CiM) architectures are proposed as a promising solution to support Deep Neural Network and Convolutional Neural Network to solve large and complex tasks in various machine learning applications. The CiM architecture overcomes the limitation of the current Von-Neumann architecture by performing logic computations within the memory also called as in-memory computing. In most CiM, the in-memory logic operations are performed on the weights stored in memory using the inputs that are processed through bitlines or wordlines using pulse width modulated (PWM) signals. For precise operation, the applied input signals must be stable. However, one of the main challenges faced during the input signal generation is the deviation in the width values due to process, voltage, and temperature variations. Addressing this challenge, in this work, we aim to mitigate the impact of one of these variations on the generated PWM signals. Therefore, in this work, we propose to design a tunable delay line that provides a linear PWM signal corresponding to an input vector which is further utilized to perform local computation in memory. Further, to minimize the impact of process variations, we propose an autonomous on-chip calibration circuit that dynamically tunes the delay lines to obtain stable and process-invariant pulse width modulated signals. Our simulation results for the proposed DL demonstrate a total delay of 559 psec with a delay error of less than 2% under various process corners. [ABSTRACT FROM AUTHOR]

Summary: The work presented in this paper aims to develop a low‐cost ultra‐wideband (UWB) radar system that has the capability to image through the wall of a human target. The proposed radar system relies heavily on a field‐programmable gate array (FPGA) platform. The Xilinx FPGA Kintex‐7 (KC705) board is employed to integrate the main functionalities of the radar system, such as the generation and acquisition of a UWB signal. The generated signal is a monocycle signal, which has an ultra‐wide bandwidth. Due to the UWB nature of this signal, the radar system achieves better penetration ability, as well as high imaging resolution. However, the major challenge of a UWB radar system lies in the stage of digitization, as it requires a high sampling rate analog‐to‐digital converter (ADC). In fact, such a chip is very expensive. Hence, to reach a high sampling resolution using a low‐cost and low‐speed ADC, an efficient sampling strategy is implemented. In contrast to other UWB sampling methods, which require a hardware delay line chip, the new sampling scheme depends only on the FPGA firmware to realize a combination of real‐time and equivalent‐time sampling, which provides better jitter performance. Finally, to demonstrate the imaging capability, experimental tests are conducted in an indoor environment while human targets are located in different places. The measurement results revealed that the proposed radar system has the ability to provide 2D images that accurately determine the location of the target. [ABSTRACT FROM AUTHOR]

Magnetic skyrmions with a well-defined spin texture have shown unprecedented potential for various spintronic applications owning to their topologically non-trivial and quasiparticle properties. To put skyrmions into practical technology, efficient manipulation, especially the inhibition of skyrmion Hall effect (SkHE) has been intensively pursued. In spite of the recent progress made on reducing SkHE in several substituted systems, such as ferrimagnets and synthetic antiferromagnets, the organized creation and current driven motion of skyrmions with negligible SkHE in ferromagnets remain challenging. Here, by embedding the [Co/Pd] multilayer into a surface acoustic wave (SAW) delay line where the longitudinal leaky SAW is excited to provide both the strain and thermal effect, we experimentally realized the ordered generation of magnetic skyrmions. The resultant current-induced skyrmions movement with negligible SkHE was observed, which can be attributed to the energy redistribution of the system during the excitation of SAW. Our findings open up an unprecedentedly new perspective for manipulating topological solitons, which could possibly trigger the future discoveries in skyrmionics and spin acousto-electronics. Skyrmions are a type of topological spin texture that have generate considerable interest for use in information storage and processing, and unconventional computing. Despite this interest, controlled generation, and motion without a Skyrmion hall effect remain an issue. Here, Chen et al combine a Skyrmion hosting magnetic multilayer with a surface acoustic wave (SAW) delay line, and show how SAWs can create, order, and allow for Skyrmion motion, without the Skyrmion Hall effect. [ABSTRACT FROM AUTHOR]

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity. [ABSTRACT FROM AUTHOR]

The field-dependence elastic modulus of magnetostrictive films, also called Δ E or Δ G effect, is crucial for ultrasensitive magnetic field sensors based on surface acoustic waves (SAWs). In spite of a lot of demonstrations, rare attention was paid to the frequency-dependence of Δ E or Δ G effect. In this work, shear horizontal-type SAW delay lines coated with a thin FeCoSiB layer have been studied at various frequencies upon applying magnetic fields. The change of shear modulus of FeCoSiB has been extracted by measuring the field dependent phase shift of SAWs. It is found that the Δ G effect is significantly enhanced at high-order harmonic frequencies close to the ferromagnetic resonance frequency, increasing by ∼82% compared to that at the first SAW mode (128 MHz). In addition, the smaller the effective damping factor of a magnetostrictive layer, the more pronounced Δ G effect can be obtained, which is explained by our proposed dynamic magnetoelastic coupling model. [ABSTRACT FROM AUTHOR]

An ammonia sensor based on a delay-line surface acoustic wave (SAW) device is developed in this study by coating the delay line area of the device with a nano-structured molybdenum disulfide (MoS2) sensitive material. A SAW device of 122 MHz was designed and fabricated with a pair of interdigital transducers (IDTs) defined on a 128° y-cut LiNbO3 substrate using photolithography technologies, and the aluminum IDT electrodes were deposited by a DC magnetron sputtering system. By adjusting the pH values of precursor solutions, molybdenum disulfide (MoS2) nanospheres were prepared with various structures using a hydrothermal method. Finally, an NH3 gas sensor with high sensitivity of 4878 Hz/ppm, operating at room temperature, was successfully obtained. The excellent sensitivity performance may be due to the efficient adsorption of NH3 gas molecules on the surfaces of the nanoflower-like MoS2, which has a larger specific surface area and provides more active sites, and results in a larger change in the resonant frequency of the device due to the mass loading effect. [ABSTRACT FROM AUTHOR]

Simulation of wave propagation in the three-dimensional (3D) modeling of the vocal tract has shown significant promise for enhancing the accuracy of speech production. Recent 3D waveguide models of the vocal tract have been designed for better accuracy but require a lot of computational tasks. A high computational cost in these models leads to novel work in reducing the computational cost while retaining accuracy and performance. In the current work, we divide the geometry of the vocal tract into four equal symmetric parts with the introduction of two axial perpendicular planes, and the simulation is performed on only one part. A novel strategy is defined to implement symmetric conditions in the mesh. The complete standard 3D digital waveguide model is assumed as a benchmark model. The proposed model is compared with the benchmark model in terms of formant frequencies and efficiency. For the demonstration, the vowels /O/,/i/,/E/,/A/, and/u/have been selected for the simulations. According to the results, the benchmark and current models are nearly identical in terms of frequency profiles and formant frequencies. Still the current model is three times more effective than the benchmark model. [ABSTRACT FROM AUTHOR]

The implementation of attosecond photoelectron–photoion coincidence spectroscopy for the investigation of atomic and molecular dynamics calls for a high-repetition-rate driving source combined with experimental setups characterized by excellent stability for data acquisition over time intervals ranging from a few hours up to a few days. This requirement is crucial for the investigation of processes characterized by low cross sections and for the characterization of fully differential photoelectron(s) and photoion(s) angular and energy distributions. We demonstrate that the implementation of industrial-grade lasers, combined with a careful design of the delay line implemented in the pump–probe setup, allows one to reach ultrastable experimental conditions leading to an error in the estimation of the time delays of only 12 as over an acquisition time of 6.5 h. This result opens up new possibilities for the investigation of attosecond dynamics in simple quantum systems. [ABSTRACT FROM AUTHOR]

The world is witnessing a transformative shift towards sustainable energy solutions, and hydrogen gas has emerged as a promising clean energy carrier with the potential to revolutionize our energy landscape. As hydrogen pipelines become an integral part of the infrastructure supporting this green energy transition, ensuring their safety and reliability becomes paramount. Among the critical challenges faced by hydrogen pipeline operators, one of the most pressing is the detection of gas leakage. Detecting hydrogen gas leaks in pipelines is not only essential for maintaining the integrity of the infrastructure but also for preventing potential safety hazards and minimizing environmental impacts. This paper presents a design to detect such leakages using two-dimensional delay line SAW based hydrogen gas sensor using COMSOL Multiphysics. The sensor is constructed with langasite piezoelectric substrate, IDT is built with aluminium and ZnO is used for sensing layer. To enhance the sensitivity of the device palladium nano particles are added to the sensor with extra conductive layer placed in the sensing layer. The proposed sensor is analysed for surface deflection, electric potential with as well as without hydrogen gas by varying the width of conductive layer from 1000μm to 3000μm.In addition to this, sensor is also tested for hydrogen environment with the concentration of gas ranging from 10ppm to 100ppm and sensitivity of the sensor is analysed. The simulated results relieved that the deflection of the sensor decreases with hydrogen gas and surface electric potential increases at all the widths of conductive layer. The conductive layer with width of 3000 μm achieved maximum deflection, electric potential and high sensitivity due to amplification provided by the conductive layer and nano particles. With hydrogen gas the sensor experiences a positive frequency shift due to change in electro acoustic effect on the sensing layer. But the sensor exhibits linearity with deflection and frequency with rise in the concentration of hydrogen gas. Further an electric equivalent model of the SAW sensor is designed using Colpitts oscillator to generate the operating frequency of SAW sensor. Electronic equivalent model is simulated using NI Multisim. The device has shown close approximation of theoretical frequency, simulated frequencies. [ABSTRACT FROM AUTHOR]

This paper examines the efficiency of a downlink non-orthogonal multiple access (NOMA) system by using a deep learning (DL)-based stacked long short-term memory (S-LSTM) scheme. The vehicle-to-vehicle (V2V) channel is considered to be time-selective as a result of node mobility and the presence of imprecise channel state information (CSI). The use of the fifth generation (5G) tapped delay line type C (TDL-C) independent and identically distributed (IID) fading channel models allows for the production of channel taps that properly replicate the Nakagami-m fading wireless channel. The paper examines the outage probability (OP) and symbol error rate (SER) of both traditional and suggested channel estimators. It analyzes these metrics under various fading parameters, pilot symbols (PS), learning rate (LR), and batch size. The training of deep neural network (DNN) models is performed using the Adam optimizer. Enhancing the signal-to-noise ratio (SNR) may decrease the SER which results in the enhanced identification of the downlink channel in NOMA cell-based systems. Reducing the LR has a positive effect on the SER, validating the analytical findings that indicate greater changes in DNN weights and larger validation mistakes when the LR is raised. Nevertheless, this benefit is accompanied by the drawback of more frequent updates, resulting in a delay in the model's convergence. [ABSTRACT FROM AUTHOR]

This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold‐FET connected high electron mobility transistors acting as varactors. Two types of periodically‐loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two‐tone measurements, and the circuit demonstrates a 3rd‐order intercept input power larger than 30 dBm for control biases above −12 V. [ABSTRACT FROM AUTHOR]

To study the influence of different resistance lines and rows delay intervals on the shape of the muck pile and the throwing distance of open-pit bench blasting based on the open-pit bench blasting test, two-dimensional particle flow code (PFC2D) is used for numerical simulation. The experimental and simulation data were compared and analyzed, and the error value was acceptable. Meanwhile, different resistance lines and row delay intervals are used to conduct numerical simulation analysis. The results show that the height change of the muck pile is directly proportional to the resistance line, and the rock throwing distance is inversely proportional to the resistance line change. The best resistance line is 1.75 m in the actual working condition, according to the effect of the muck pile. By fitting the relationship between the resistance line and rock throwing distance and blasting muck pile's height, it is found that the relationship is nonlinear. By simulating different row delays, the optimal row delay time difference in the bench blasting model is determined to be 25 ms under similar working conditions. It provides a guiding significance for the blasting parameter design under similar working conditions. [ABSTRACT FROM AUTHOR]

This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed at the transistor and application levels to justify the performance of our design. Simulations performed using the HSPICE tool confirm the significant improvement in the performance of the proposed circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Additionally, via a MATLAB tool, the image blending (alpha blending) application uses inaccurate Full Adder cells. Software simulations confirm the suitable quality of the final images according to the image quality evaluation criteria. [ABSTRACT FROM AUTHOR]

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW. [ABSTRACT FROM AUTHOR]

Radio wave propagation in an intra-vehicular (IV) environment is markedly different from other well-studied indoor scenarios, such as an office or a factory floor. While millimetre wave (mmWave)-based intra-vehicular communications promise large bandwidth and can achieve ultra-high data rates with lower latency, exploiting the advantages of mmWave communications largely relies on adequately characterising the propagation channel. Channel characterisation is most accurately done through an extensive channel sounding, but due to hardware and environmental constraints, it is impractical to test channel conditions for all possible transmitter and receiver locations. Artificial neural network (ANN)-based channel sounding can overcome this impediment by learning and estimating the channel parameters from the channel environment. We estimate the power delay profile in intra-vehicular public and private vehicle scenarios with a high accuracy using a simple feedforward multi-layer perception-based ANN model. Such artificially generated models can help extrapolate other relevant scenarios for which measurement data are unavailable. The proposed model efficiently matches the taped delay line samples obtained from real-world data, as shown by goodness-of-fit parameters and confusion matrices. [ABSTRACT FROM AUTHOR]

The measurement errors induced by the space‐time adaptive processing (STAP) is gaining attention for its significant detriment to the precision of the global navigation satellite system (GNSS) receiver positioning. To mitigate measurement errors, the steering vector (SV) estimation method based on spreading is widely employed in measurement error mitigation algorithms. However, the hazard of the SV estimation fluctuation problem is ignored in these algorithms. In this paper, the specific harm of such SV estimation fluctuation problem is analysed. To alleviate such problem and to eliminate the measurement errors as much as possible, a robust STAP beamformer for GNSS receivers is proposed. First, to acquire a series of robust SVs in different integration times, a desired signal covariance (DSC) matrix is iteratively reconstructed to remove the disturbance from thermal noise and the residual jamming signals. Second, to eliminate measurement errors, a replacement matrix is formed to help guarantee the phase linearities of the tapped delay lines (TDLs). Numerical examples demonstrate that the method can achieve a set of stable SV estimations and linear phase TDLs, leading to a carrier‐to‐noise‐power ratio (C/N0$C/N_0$) of more than 50 dBHz and a code phase bias of less than 3.4 m, which outperform the methods used for comparison. [ABSTRACT FROM AUTHOR]

In this paper, a comparative investigation of a C-band long-pulse high-efficiency klystron-like relativistic cavity oscillator is carried out by using numerical simulation and practical experiments. It is indicated that owing to the improper configuration of the solenoid, some returning electrons originating from the cathode supporting rod would hit the entrance of the diode and shunt the input electric power. As a result, the startup process of the device is delayed and the saturated output power is decreased as well. In the initial experiment, the output power and the pulse duration are only about 3.2 GW and 78 ns, respectively. To eliminate the influence of the returning electrons, by increasing the turn number of the winding at both ends of the solenoid, the magnetic field at the diode region is enhanced so that the returning electrons could be guided to the shielding bowl in front of the insulator. As the shielding bowl is under the same potential as the cathode, the returning electrons would not shunt the input power. In contrast, after solenoid compensation, the output power of the device is increased to 4.4 GW at a diode voltage of 700 kV and a current of 14 kA, whereas the pulse duration is extended to 96 ns. Also, the corresponding conversion efficiency achieves about 45%. [ABSTRACT FROM AUTHOR]

When an FIR-Hilbert transformer with an even-numbered filter order of N is used in real-time signal processing, a delay line should be placed in parallel to compensate for the delay time of N/2 arising from the FIR-Hilbert transformer. In general, the FIR-Hilbert transformer possesses a ripple governed by a filter order, a transition bandwidth, among others. In contrast, the delay line does not possess any ripple. Then, an issue regarding the ripple is encountered during signal processing. In this letter, a practical method is proposed to nullify the ripple effect in signal processing. A simple solution is that the same ripple exists on the Hilbert transformer and delay line. Subsequently, two Weaver's modulators for generating the USB signal are placed in parallel, and the real part of one of the two is used for a delay line and the imaginary part of the other of the two is used for a Hilbert transformer. When the same FIR-LPF is introduced into each of the two, the ripple effect can be nullified. [ABSTRACT FROM AUTHOR]