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We investigated the molecular beam deposition of Al2O3 on Ge0.95Sn0.05 surface with and without an ultra thin Ge cap layer in between. We first studied the atomic configuration of both Ge1−xSnx and Ge/Ge1−xSnx surfaces after deoxidation by reflection high-energy electron diffraction and resulted, respectively, in a c(4×2) and (2×1) surface reconstructions. After in situ deposition of an Al2O3 high-κ gate dielectric we evidenced using time-of-flight secondary ion mass spectroscopy analyses that Sn diffusion was at the origin of high leakage current densities in the Ge1−xSnx/Al2O3 gate stack. This damage could be avoided by inserting a thin 5-nm-thick Ge cap between the oxide and the Ge1−xSnx layer. Finally, metal-oxide-semiconductor capacitors on the Ge capped sample showed well-behaved capacitance-voltage (C-V) characteristics with interface trap density (Dit) in the range of 1012 eV−1 cm−2 in mid gap and higher close to the valence band edge.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al2O3/GaSb interface have been studied by in situ deposition of an Al2O3 high-kappa gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C-V with relatively low D-it along the bandgap, these results point out an efficient electrical passivation of the Al2O3/GaSb interface. (C) 2011 American Institute of Physics. [doi:10.1063/1.3569618] This work is part of the IMEC Industrial Affiliation Program and is supported by the European Commission’s project FP7-ICT-DUALLOGIC no. 214579, “Dual-Channel CMOS for (sub)-22nm High Performance Logic.” The authors would like to thank Th. Conard and A. Franquet for XPS characterizations, F. Paola and H. Bender for TEM analyses, and H. Costermans for the support of the MBE tool.

In this paper, a nanoanalytical investigation of electron beam evaporated PdGe ohmic contacts onto an n+ In0.53Ga0.47As layer using electron energy loss spectroscopy (EELS) is presented. The chemical information reported in this paper has been obtained using EELS spectrum images (SI) that allow not only depth resolution but also spatial resolution which is essential in such inhomogeneous systems.

Deep Level Transient Spectroscopy (DLTS) has been applied to MOS capacitors (MOSCAPs) fabricated on n- and p-type GaAs and on n-type InxGa1-xAs epitaxial layers deposited by MBE on GaAs substrates. The gate dielectric consists of 10 nm ALD Al2O3. It is shown that the dominant deep levels in the case of GaAs MOSCAPs are two broad interface-state-related bands centered around midgap, which appear to be very similar to what has been found in the past for other gate dielectrics on GaAs. At the same time, it is reported that the interface-state peak shifts closer to the conduction band for the InxGa1-xAs layers, whereby the activation energy becomes smaller for higher x. However, it is demonstrated that in this case not only interface states contribute to the DLTS emission signal but also deep levels associated with threading dislocations (TDs) in the relaxed layers. This contribution grows progressively with the In content, i.e., with the amount of relaxation. From this, it is concluded that InxGa1-xAs/GaAs substrates are not favorable for inversion-type of MOS devices due to the increasing impact of the TDs on the device performance.

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Physical and electrical properties of Ge/Al2O3/Pt and Ge/GeO2/Al2O3/Pt gate stacks using molecular beam deposition were proposed in this work. In spite of a straight deposition of Al2O3 on Ge substrate, XPS and TEM analysis revealed the formation of a thin interfacial layer coming from the intermixing between Ge sub-oxides and the high-ĸ dielectric. Electrical measurements showed a high density of interface states (3x1012eV-1.cm-2) mainly due to the presence of this interlayer. Performing a FGA in 10% H2/90% N2 on such structures leads to a significant reduction of DIT and leakage current density. Moreover, growing an in-situ GeO2 layer on Ge before high-ĸ deposition allowed us to reduce the interface states and to reach a very low DIT-value of 1~2x1011eV-1.cm-2 for Ge/GeO2/Al2O3 gate stacks after FGA, providing the efficient passivation of Ge/GeO2 interface. It has also been demonstrated that Al2O3 was a good capping layer, preventing from Ge/GeO2 interfacial degradation under high temperature treatment.

In this study, we investigate the limitations to sheet resistance and Hall effect characterization of ultra-shallow junctions (USJs) in In0.53Ga0.47As. We compare conventional van der Pauw and Hall effect measurements with micro four-point probe (M4PP) and micro Hall effect methods. Due to the high carrier mobility of InGaAs, we extend the micro-Hall effect position error suppression method to also take geometrical magnetoresistance into account. We find that the conventional techniques fail to measure accurately on n(++)/p(+) USJ due to a significant leakage current, whereas the M4PP and micro Hall effect methods are able to give accurate results. Finally, we observe a significant reduction in the carrier mobility for InGaAs USJ.