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The displacement ductility limit for seismic design of concrete piles is determined for the range of cohesionless soils expected in practice. The curvature ductility capacity associated with specified performance limit states, namely, the “serviceability” and “damage-control” limits, is determined based on the current provisions for confining steel. An analytical model is applied to assess the displacement ductility factor at the specified curvature ductility level. The investigated parameters include the soil stiffness, pile diameter, longitudinal reinforcement ratio, axial force level, and pile above-ground height. A set of design displacement ductility factors is recommended and verified to ensure the satisfactory seismic performance.

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultralow-power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static, such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 s on some benchmarks.

Wire bonding is one of the key processes which connects the wafer die and the lead frame in the IC packaging process. It is noted that process parameters influence both the speed and quality of bonding. Parameters, such as descending speed and cycles affect the bonding speed; while parameters such as bonding force and ultrasonic energy level affect the strength of joint. Both situations will affect the output (unit per hour, UPH), and lead to the variation of the production capacity as well.Nowadays, most companies in Taiwan still follow the rule of thumb when setting the process parameters. However, the large number of parameters in the bonding process makes it difficult for engineers to find appropriate parameters at once efficiently based on their experience only. When new products are introduced into mass production, engineers must go through multiple adjustments in a repeated trial and error way to find out the appropriate parameters, which takes lots of time, manpower and material resources.Using data mining techniques to establish predictive models for process parameters can not only increase the production capacity but also reduce the cost of the operation during adjustments. However, most studies in the field of wire bonding parameter optimization focused on increasing the bonding quality, while little consider the operation time and quality simultaneously. In this study, a data mining framework is proposed to extract the relationship between the bonding speed, bonding quality and the parameters.This study aims to increase production capacity by enhancing the bonding quality and the bonding speed simultaneously via recommending optimized process parameters. The proposed framework is based on a defect classification model constructed by random forest (RF) and extreme gradient boosting (XGBoost) method, and a multi-objective process parameters optimization model applying particle swarm optimization (PSO) method.An empirical study was conducted in a leading IC packaging and assembly company in Taiwan. The empirical result on 2 testing products reveals that the proposed approach increases the bonding quality by 70%, whereas the bonding speed is enhanced by 20%; overall, the proposed approach benefits output UPH by 26.6%, 5.0% for each product. Besides improving the production capacity, the proposed framework can also recommend parameters systematically and more quickly to enhance engineers’ parameter tuning efficiency on-line and achieve the goal of reducing the introduction time of new products.

Studies have shown that stair exercises can enhance the strength of lower limbs for patients with limb disorders. However, there are only few systems that can monitor the lower limb exercises in the medical institutes. To analyze the lower limb exercises instantaneously, we propose a smart single-sensor wearable device, $S^{3}-Sock$, equipped on shoes. The sock can monitor and measure the stride count, step height, and the distance of step trajectory about lower limb exercises. The experimental results demonstrate that the proposed system is reliable under different lower limb exercises. The averages of absolute mean errors of stride count in stair-climbing and walking are about 2.00% and 0.88%, respectively. The averages of absolute mean errors of step height are about 5.12% and 8.23% in step-by-step and step-over-step stair climbing, respectively.

Logic locking is a technique used for intellectual property protection. An effective attacking method based on satisfiability (SAT) algorithm, known as SAT attack, was proposed to decrypt an encrypted design successfully. To strengthen logic locking, this paper proposes a glitch-based logic locking method designed for sequential circuits. The proposed new schemes of key-gates can generate glitches, and use rising and falling transitions as key-inputs for the comprehensive logic locking. Experimental results show that the proposed glitch key-gate (GK) has high capability to be embedded in a set of IWLS2005 Benchmarks [22]. The cell area overhead in the designs encrypted with GKs are 10.68%, 12.22%, and 26.11% on average for encryptions with 8, 16, and 32 key-inputs, respectively, and the overhead can be reduced substantially when the GKs are combined with other logic locking methods.

In the wire bonding process, different setting value of manufacturing parameters affect the quality of the solder joints and the speed of wire bonding significantly. And when a new product is introduced, it is difficult to quickly obtain effective parameters simply by relying on the experience of the engineers. The study aims to propose a data mining framework to help the IC packaging factories to increase production capacity by reducing the number of downtimes and speeding up the wire bonding time. The proposed data mining framework employed random forest and XGBoost method to classify the occurrence of defect, MARS algorithm to predict the wire bonding time, and genetic algorithm to search for the manufacturing parameters. By exploring the production data, the proposed framework finally provides a set of recommended manufacturing parameters of the second bonding process. This study cooperates with a leading assembly company in Taiwan to validate the proposed framework. The empirical result reveals that it improves the packaging yield by 0.03%. The domain engineers can also find parameters more systematically and quickly by the proposed framework.

Cu–Zn alloy micropillars were fabricated using microanode-guided electroplating (MAGE) at a constant voltage of 4.6 V under an initial inter-electrode gap of 30 µm in pyrophosphate baths. Energy-dispersive spectroscopy and X-ray diffractometry analysis revealed that the micropillar alloys exhibit an increase in the Zn content from 8.05 at.% (in α phase) to 54.60 at.% (in β, and β' phases) with an increase in the ratio of [Zn2+]/[Cu2+] in the bath from 8/1 to 128/1. Transmission electron microscopy revealed that the Cu–Zn alloy micropillars were composed of nano-grains with different sizes depending on the bath employed. Nano-indentation test indicated that the micropillar containing 40.51 at.% Zn (in presence of β-phase) exhibits the maximum hardness (at 5.30 GPa) and highest Young's modulus (at 113.64 GPa). Simulation of the electric field using the commercial software COMSOL 5.2 revealed that the highest field strength centralized at the cylindrical top displayed only a slight increase (from 152.2 to 152.5 kV/m) with an increase in the ratio of [Zn2+]/ [Cu2+] in the bath. Potentiodynamic cathodic polarization is useful for understanding the mechanism of microanode-guided electroplating. Electrochemical impedance spectroscopy performed at characteristic potentials confirms the mechanism extremely well.

Emerging countries and traditional industries may not be ready for direct migration of Industry 4.0. In particular, the broiler is a major source for meat, while poultry farming in emerging countries is mainly by small and medium-sized enterprises (SMEs) or family businesses. The live broilers need to maintain the desired specification for food processing while optimizing the feeding conversion rate for revenue management. Conventionally, broiler growth monitoring and prediction rely on farmers’ experience and a small amount of data by unrigorous sampling. Although the automatic weighing system (AWS) has gradually been employed to replace manual weighing to reduce cost and casualties, existing automatic weighing systems have limited capability for weight monitoring and weight prediction of broiler future growth. To fill the gaps, this study aims to employ Industry 3.5 as a hybrid and develop a data-driven framework for weight monitoring and prediction to support smart production for poultry farming for revenue optimization. The proposed framework contains two modules. The weight monitoring integrates Gaussian Mixture Model, bootstrapping resampling, and weighted mean technique to estimate the current weight of live broilers in the farm via big data including electronic signals collected from the farms via multiple sensors and devices. The weight prediction module employs mathematical growth functions as a basis and daily feedback for adjustment to provide real-time weight prediction to support related decisions for smart production. An empirical study was conducted in Taiwan. The results have shown the practical viability of this approach. The developed solution is implemented in the broiler industry.

Artificial Neural Networks (ANNs) have been widely used to deal with various classification problems for decades. Different algorithms for synthesizing ANNs have been proposed as well. The number of neurons in an ANN usually controls the tradeoff between classification ability and computational efficiency. That is, more neurons tend to yield better results but are less efficient in either the training or recalling phase. Furthermore, if the neurons are implemented by physical devices, the implementation cost can be effectively reduced with fewer number of neurons in an ANN. In this paper, we propose a method to minimize the number of neurons used in an ANN that is built by using Voronoi diagrams without suffering any capability loss. We have conducted experiments on a set of benchmarks. The experimental results show that the resultant ANNs reduce the number of neurons by up to 94 percent.

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultra-low power consumption. Existing SET synthesis methods synthesize a Boolean network into a large reconfigurable SET array where the height of SET array equals the number of primary inputs. However, recent experiments on device level have shown that this height is restricted to a small number, say, 10, rather than arbitrary value due to the ultra-low driving strength of SET devices. On the other hand, the width of an SET array is also suggested to be a small value. Consequently, it is necessary to decompose a large SET array into a set of small SET arrays where each of them realizes a sub-function of the original circuit with no more than 10 inputs. Thus, this article presents two techniques for achieving area-efficient SET array decomposition: One is a width minimization algorithm for reducing the area of a single SET array; the other is a depth-bounded mapping algorithm, which decomposes a Boolean network into many sub-functions such that the widths of the corresponding SET arrays are balanced. The width minimization algorithm leads to a 25%--41% improvement compared to the state of the art, and the mapping algorithm achieves a 60% reduction in total area compared to a naïve approach.

In this work, the feasibility of liquid level detection based on structural vibration modes is investigated. We specifically consider impact-induced vibration modes of an aluminum solid partially immersed in a water tank. A free-edge bonded fiber Bragg grating (FBG) sensor and a corresponding high-speed FBG filter-based demodulation system are employed to measure the transient impact responses. To perform more accurate in vacuo finite element analysis (i.e., for the mode shapes, resonant frequencies, and the impact responses), elastic constants of the aluminum solid and impact loading history of a steel ball are obtained beforehand respectively according to the elastic wave theory and with a polyvinylidene fluoride (PVDF)-based technique. Our experimental results show good correspondences of intensities and shifts of the impact-induced resonant modes with liquid levels. The modes of the same type (e.g., double modes in out-of-plane or in-plane dominated modes) are shown to possess similar behaviors in relationships between shifts of the resonant modes and the liquid level. This work also provides related experimental evidence for future researchers interesting in simulation of complicated fluid-structure interaction (FSI) problems for three-dimensional structures.

The technology of mathematical expression identification and recognition extracts mathematical expressions in document images, and it has been studied for over a decade. Based on previous works, we develop an automatic recognition tool, named EqnEye, which leverages the OpenCV library to perform image processing and Tesseract tool to recognize mathematical symbols. We also apply correction methods before the recognition stage to improve the recognition accuracy. To improve the efficiency for processing images of high resolution, the parallel implementation of thresholding method on GPU is integrated into this work. Experimental results exhibit the success of our correction methods to enhance the accuracy and the slight improvement to the performance. In addition, porting the recognition tool to handy devices can produce more value-added applications.

Summary For modal testing, active vibration control, or structural health monitoring, determination of sensing locations becomes a crucial issue once the interesting mode has nodal lines on which the sensors are bonded. Theoretically, only nodal points but not nodal lines would exist along free edges of the structures. Thus, measurements of vibrations along free edges of structures would maximize the number of detecting (i.e., for monitoring application) or observing (i.e., for active control application) modes. However, conventional sensors such as strain gauges or accelerometers can only be bonded on flat or smooth surfaces. In this work, fiber Bragg gratings, which possess linear geometric shape, are employed to investigate the feasibility of detecting more vibration modes along free edges of structures. A traction-free aluminum solid with symmetric geometry subjected to various impact loadings is considered. To verify the capability of the free-edge bonded FBG sensors for detecting vibration modes from impact-induced responses, relationships between sensing locations, impact locations, and intensities of modes, are discussed with the aid of mode shapes obtained by the finite element me\thod. Within frequencies up to 30 kHz, 14 out-of-plane dominated and 25 in-plane dominated modes in frequency domain are examined. Multiple modes, that is, repeated roots, two or more modes with identical frequencies due to symmetric geometry, are also analyzed. Our experimental results show that placing the FBGs along free edges of structures to acquire and analyze more vibration modes is feasible. Copyright © 2016 John Wiley & Sons, Ltd.

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultralow power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches have been proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, seldom mapping algorithms that consider the existence of defective nanowire segments were proposed. Furthermore, before the defect-aware mapping, we have to know the locations of defects in SET arrays. Thus, this paper presents the first diagnosis approach to identify the locations of defects in SET arrays followed by two defect-aware algorithms for mapping SET arrays in different scenarios. The experimental results show that the proposed diagnosis method can detect 100% of defects under a defect rate and distribution in SET arrays. As for the mapping algorithms, the results show that our approach can successfully map the SET arrays with 11.13% and 7.69% width overhead on average in the baseline detour mapping algorithm and defect-reuse mapping algorithm, respectively, in the presence of 5000-ppm defects.

Power consumption has become a primary obstacle for circuit designs at present. Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its low power consumption. Since, only a few electrons are involved in the switching process, the drivability of SETs is ultra-low such that the height of an SET array is limited to a small number. This paper presents a delay minimization synthesis flow that decomposes a circuit into a network of SET Array Blocks (SABs) with a fixed height and width. The experiments were conducted for different sizes of SABs over a set of benchmarks. The experimental results showed that we can have the smallest average Area Delay Product (ADP) when the height is 5 and the width is 10 of an SAB, which indicates that such size of SABs is proper to synthesize SET networks.

Fault-based verification technique is a method to qualify a verification environment. The better verification environment can detect output differences between the fault-free and fault-injected circuits with a higher probability. Since different injected faults could cause the same output response under all stimuli, which are called equivalent faults, maximally identifying these equivalent faults can improve the efficiency of verification environment qualification without sacrificing its quality. The 2016 CAD Contest at ICCAD posed the problem of identifying equivalent faults in the circuits. This paper presents our work in the Contest with some improvements.

This paper presents a method based on range-equivalent circuit technique for SAT-based bounded sequential equivalence checking. Given two sequential circuits to be verified, instead of straightforward unrolling the miter of two sequential circuits, we iteratively minimize the miter with a range-equivalent circuit technique before adding a new timeframe. This is because the previous timeframes can be considered as a pattern generator that feeds input patterns to the next timeframe. Experimental results show that the proposed method saved up to 91% of time for reaching the same bounded depth compared with previous work on IWLS2005 benchmarks.

Recently, Threshold logic attracts a lot of attention due to the advances of its physical implementation and the strong binding to neural networks. Approximate computing is a new design paradigm that focuses on error-tolerant applications, e.g., machine learning or pattern recognition. In this paper, we integrate threshold logic with approximate computing and propose a synthesis algorithm to obtain cost-efficient approximate threshold logic circuits with an error rate guarantee. We conduct experiments on IWLS 2005 benchmarks. The experimental results show that the proposed algorithm can efficiently explore the approximability of each benchmark. For a 5% error rate constraint, the circuit cost can be reduced by up to 65%, and 22.8% on average. Compared with a naive method, our approach has a speedup of 2.42 under a 5% error rate constraint.

S1. PICO question. S2. Excluded RCTs that did not provide sufficient information on EN. S3. Definitions of GI bleeding and nosocomial pneumonia in the included RCTs. S4. Risk of bias graph and summary of the included RCTs. (DOCX 39 kb)

Power consumption has become one of the primary challenges to meetMoore’s law. For reducing power consumption, single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultralow power consumption in operation. Previous works have proposed automated mapping approaches for SET arrays that focused on minimizing the number of hexagons in the SET arrays. However, the area of an SET array is the product of the bounded height and the bounded width, and the height usually equals the number of inputs in the Boolean function. Consequently, in this paper, we focus on the width minimization to reduce the overall area in the mapping of the SET arrays. Our approach consists of techniques of product term minimization, branch-then-share (BTS)-aware variable reordering, SET array architecture relaxation, and BTS-aware product term reordering. The experimental results on a set of MCNC and IWLS 2005 benchmarks show that the proposed approach saves 45% of width compared with the work by Chiang et al. , which focused on hexagon count minimization, and also saves 13% of width compared with the work by Chen et al. , which focused on width minimization.

Many bridges located in seismic hazard regions suffer from serious foundation exposure caused by riverbed scour. Loss of surrounding soil significantly reduces the lateral strength of pile foundations. When the scour depth exceeds a critical level, the strength of the foundation is insufficient to withstand the imposed seismic demand, which induces the potential for unacceptable damage to the piles during an earthquake. This paper presents an analytical approach to assess the earthquake damage potential of bridges with foundation exposure and identify the critical scour depth that causes the seismic performance of a bridge to differ from the original design. The approach employs the well-accepted response spectrum analysis method to determine the maximum seismic response of a bridge. The damage potential of a bridge is assessed by comparing the imposed seismic demand with the strengths of the column and the foundation. The versatility of the analytical approach is illustrated with a numerical example and verified by the nonlinear finite element analysis. The analytical approach is also demonstrated to successfully determine the critical scour depth. Results highlight that relatively shallow scour depths can cause foundation damage during an earthquake, even for bridges designed to provide satisfactory seismic performance.

Additional file 4: Table S4. Non-compliance rate reported in the included RCTs.

Quantum-dot Cellular Automata (QCA) has emerged as a new design paradigm for nanotechnologies. Since the operational logic in QCA is the majority logic, much research about the synthesis and optimisation of majority logic has been proposed recently. In this paper, we propose an optimisation method by merging nodes in the Majority-Inverter-Graph, which is the representation of majority logic circuits. Instead of using satisfiability solvers, our approach can identify the node mergers by using logic implications for circuit size reduction. The experimental results show that for a set of EPFL benchmarks, our approach can minimise the node count by 21% when integrated with the state-of-the-art on average.

Lithium metal anode has been regarded as the "Holy Grail" of next-generation battery technologies. In order to stabilize the electrodeposited Li metal for safe and high energy batteries, highly concentrated electrolytes (solvate electrolytes) have been proposed to suppress the formation of Li dendritic structure and polysulfide dissolution in lithium-sulfur (Li-S) batteries. (1-5) In this talk, we use in situ transmission X-ray microscopy (TXM) to study the effect of solvate electrolyte on Li plating/stripping process. In situ TXM images show that electrodeposited Li particles with uniform density are formed in solvate electrolyte during initial plating process. The effect of solvate electrolyte on the mechanism of Li growth is studied in detail. Additionally, in situ spectroscopy including Raman and X-ray spectroscopy (X-ray diffraction and X-ray absorption spectroscopy) are used to investigate sulfur reaction mechanism and the interaction between polysulfide and solvate electrolyte. We found that the sulfur species formed in the solvate electrolyte are different from the sulfur species formed in conventional DOL/DME electrolyte. These results suggest that solvate electrolyte changes both polysulfide solubility and sulfur reaction mechanism. We next propose different solvate electrolytes with low polysulfide solubility and high stability toward Li metal to enhance the capacity retention of Li-S batteries. References: [1] L. Suo et al., Nat. Commun. 2013, 4, 1481. [2] K. Dokko et al., J. Electrochem. Soc. 2013, 160, A1304. [3] M. Cuisinier et al., Energy Environ. Sci., 2014, 7, 2697. [4] Y. Yamada et al., J. Electrochem. Soc. 2015, 162 (14), A2406. [5] L. Cheng et al., ACS Energy Lett. 2016, 1, 503.

Recently, single-electron transistors (SETs) have been attracting substantial attention and are considered candidate devices for future integrated circuits due to their ultralow power consumption. To realize SETs, a binary decision diagram-based SET array is proposed as a suitable candidate for implementing Boolean circuits. Then, some works started developing computer-aided design techniques for this new architecture. However, most of them focused on the development of mapping techniques. How to verify the mapping results is still an open problem. Thus, in this paper, we address this problem and develop a satisfiability (SAT)-based verification method. We propose a transformation approach to model the functionality of a mapped SET array as a conjunctive normal form formula. Then, the problem that whether the SET array is functionally equivalent to its specification circuit can be solved with a SAT solver. The experimental results show that the proposed method can successfully verify correct and incorrect SET array implementations with reasonable verification time.

Comparison of patients screened for PJP and patient enrollment in 3 studies in Peking Union Medical College Hospital. (DOCX 73Â kb)

PJP diagnosis by methenamine and PCR in participating centers. (DOCX 59Â kb)

Summary of published studies. (DOCX 88Â kb)

This article does research on 4MSC-3000 cotton picker transmission system thorough. It establishes transmission system dynamics model and vibration differential equation, ADAMS virtual prototyping technology is used to do simulation on the transmission system. Kinematics relations and dynamic characteristics of the transmission system are found out. Through the dynamic analysis of the model to solve, we can get kinetic curve of gearbox, each axis, gears and so on. Then provide the necessary theoretical basis for follow-up prototype design.

This paper presents a logic restructuring technique named node addition and removal (NAR). It works by adding a node into a circuit to replace an existing node and then removing the replaced node. Previous node-merging techniques focus on replacing one node with an existing node in a circuit, but fail to replace a node that has no substitute node. To enhance the node-merging techniques on logic restructuring and optimization, we propose an NAR approach in this paper. We first present two sufficient conditions that state the requirements of added nodes for safely replacing a target node. Then, an NAR approach is proposed to quickly detect the added nodes by performing logic implications based on these conditions. We apply the NAR approach to circuit minimization together with two techniques: redundancy removal and mandatory assignment reuse. We also apply it to satisfiability (SAT)-based bounded sequential equivalence checking (BSEC) to reduce the computation complexity of SAT solving. The experimental results show that our approach can enhance our prior automatic test pattern generation-based node-merging approach. Additionally, our approach has a competitive capability of circuit minimization with 44 times speedup compared to a SAT-based node-merging approach. For BSEC, our approach can work together with other optimization technique to save a total of approximately 39-h verification time for all the benchmarks.

This article uses the flow field numerical simulation technology, it does simulation research for the flow field of the whole pneumatic conveying cotton trunk, through studying different types of jet orifice of the conveying trunk of comb—type cotton picker, finding out the influence of jet orifice width on pressure and velocity field, further understanding flow field distribution characteristics of the internal pneumatic cotton conveyance system, and providing necessary basis for the machine.

Zhishin clay and Black Hill bentonite are used as raw clay materials in this study. These clays are mixed with Taitung area hard shale to produce the backfill material for potential application as barrier for the disposal of low-level radioactive waste. The interaction between concrete barrier and the backfill materials is simulated by an accelerated migration test to investigate the effect of concrete on the expected functions of backfill material. The results show some decrease in swelling potential in the backfill material near the interface. Also, backfill material close to the contact with concrete exhibits greater change in the ratio of calcium/sodium concentration, due to the release of calcium ions from the concrete material.

Effects of different impact angles such as 45°and 90°on the erosion-abrasion properties of Al-Mn alloy and its composites reinforced with Al2O3 particulates were studied by rotating erosion-abrasion test, and the failure mechanism were analyzed. The results show that the as-cast Al-Mn alloy is composed of aluminium-manganese solid solution, MnAl6 and Al11Mn4 phase, while the δ-Al2O3 particles are included in the composites besides the aforementioned microstructures. The cumulative mass loss of the Al-Mn alloy and its composites at 45° are both more than those at 90°, however, the loss of the composites are lower than those of the Al-Mn alloy, suggesting that the former possesses more excellent erosion-abrasion resistance properties.

Designing a top-stem-cutter part for the top-cutter machine. Adams was used to analysis the moving simulation, with the help of it, the normal structure and dimension were inspected and verified. In this paper, the tract of the top-stem-cutter part analyzed by Adams was matched the result from the theoretical calculations; the model and structure also had been analyzed by Ansys, which provided a way to analysis and verify the machine, and analysis of the model can get the nature frequency of the top-stem-cutter part, and it had given us a way to lower frequency of machine; the structure analysis provided that the stress of the top-stem-cutter part should be lower than certain value.

Effects of different impact angles such as 45°and 90°on the erosion-abrasion properties of hypereutectic Al-Mn alloy and its composites reinforced with Al2O3 particulates were studied by rotating erosion-abrasion test, and the microstructure and the worn surfaces were analyzed. The results show that the as-cast Al-Mn alloy is composed of aluminium-manganese solid solution, MnAl6 and Al11Mn4 phase, while the δ-Al2O3 particles are included in the composites besides the aforementioned microstructures. With elongating the erosion time, the wear rates of the Al-Mn alloy and its composites increase at the impact angle of 90°, whereas they firstly increase and then decrease , and there is a maximum at 45°. The distortion wear caused by the normal stress is dominant at 90°, which lead to the erosion pits on the worn surface. However, the cutting wear by the shear stress is predominant at 45°, which result in the ploughs.

Effects of different impact angles such as 45°and 90°on the erosion-abrasion properties of eutectic Al-Mn alloy and its composites reinforced with Al2O3 particulates were studied by rotating erosion-abrasion test, and the microstructure and the worn surfaces were analyzed. The results show that the as-cast Al-Mn alloy is composed of aluminium-manganese solid solution, MnAl6 and Al11Mn4 phase, while the δ-Al2O3 particles are included in the composites besides the aforementioned microstructures. With elongating the erosion time, the wear rates of the Al-Mn alloy and its composites increase at the impact angle of 90°, whereas they firstly increase and then decrease , and there is a maximum at 45°. The distortion wear caused by the normal stress is dominant at 90°, which lead to the erosion pits on the worn surface. However, the cutting wear by the shear stress is predominant at 45°, which result in the ploughs.

In this paper, we used the dynamic strain measurement method to measure the top-cutter machine of cotton’s stress under its working state. With sorting out data and analyzing it, we obtained the stress condition of the framing and the working parts. And the measurement result could be used to analyze the axle’s fatigue strength and check whether it was safe or not. It provided integrant basis for the further design of the machine.

As the first step of DRAM manufacture, preanneal process plays an important role in determining the threshold voltage variation. It is found that the higher trans-1,2-dichloroethene flow in pad oxide growth and the higher nitrogen flow in high-temperature annealing step would respectively engender a lower boron segregation coefficient and higher nitridation of the oxide, both modify the boron distribution in the substrate and consequently the behavior of the threshold voltage. As the feature size of DRAM devices enter nanometer regime, besides gate oxidation, ion implantation and related thermal processes, the impact of preanneal process condition should be prudentially taken into consideration for rigorous control of the threshold voltage in the advanced DRAM production.

Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow.

The influence of process condition on the resistivity of the arsenic-doped polysilicon electrode for the cell capacitors in trench DRAM was investigated. Rather than the arsine flow, it is found that the thickness of the undoped amorphous silicon plays a vital role in determining the overall resistivity. When the total polysilicon thickness is kept unchanged, moderately increasing the thickness of the lower two undoped amorphous silicon would engender a reduced resistivity while moving the arsenic peak location away from the polysilicon/storage dielectric interface, which is critical in leakage current suppression. With these improved properties, less bit line coupling (BLC) loss from the characterization on DRAM product is observed. The result of this study is quite important for trench DRAM manufacturer to enhance product yield before the technology of metal electrode is mature.

Exact approaches to combinational equivalence checking, such as automatic test pattern generation-based, binary decision diagrams (BDD)-based, satisfiability-based, and hybrid approaches, have been proposed over the last two decades. Recently, we proposed another exact approach using signal probability. This probability-based approach assigns probability values to the primary inputs and compares the corresponding output probability of two networks via a probability calculation process to assert if they are equivalent. The shortcoming of all these exact approaches is that if two networks are too complex to be handled, their equivalence cannot be determined, even with tolerance. An approximate approach, named the probabilistic approach, is a suitable way to give such an answer for those large circuits. However, despite generally being more efficient than exact approaches, the probabilistic approach faces a major concern of a non zero aliasing rate, which is the possibility that two different networks have the same output probability/signatures. Thus, minimizing aliasing rate is substantial in this area. In this paper, we propose a novel probabilistic approach based on the exact probability-based approach. Our approach exploits proposed probabilistic equivalence checking architecture to efficiently calculate the signature of network with virtually zero aliasing rate. We conduct experiments on a set of benchmark circuits, including large and complex circuits, with our probabilistic approach. Experimental results show that the aliasing rate is virtually-zero, e.g., 10-6013. Also, to demonstrate the effectiveness of our approach on error detection, we randomly inject errors into networks for comparison. As a result, our approach more efficiently detects the error than a commercial tool, Cadence LEC, does. Although our approach is not exact, it is practically useful. Thus, it can effectively complement exact methods to improve the efficiency and effectiveness of combination equivalence checking algorithms.

This paper carried on mechanics analysis and the research to the Curved Rake Tine Frame and Headstock of film recycling machine which could cut cotton stalk and recycle the used film simultaneously. This machine was developed by the Institute of Agriculture Machine Xingjiang Academy of Agricultural Sciences. This paper used servile methods to identify the structural deficiencies such as Visualization Virtual Design, Finite Element Method and Testing Method. These data provided a theoretical basis for the design of the Curved Rake Tine Frame and Headstock.

This paper is concerned with organic contamination from a partially fluorinated o-ring used in a furnace for a high-temperature process. The organic outgas was confirmed by Fourier transform infrared analysis of the furnace exhaust gas. Experiments from practical trench dynamic random access memory disclosed that outgassed organic contaminants from the nitride process would severely worsen the tunneling leakage current performance of the storage dielectric and lead to fatal yield loss even though the cell capacitance was almost uninfluenced. To eliminate this yield detractor requires several test runs prior to real production after installation of the partially fluorinated o-ring; otherwise, a fully fluorinated o-ring is needed. From a cost viewpoint, the latter is highly suggested.

A crosstalk effect leads to increases in delay and power consumption and, in the worst-case scenario, to inaccurate results. With the scale down of technology to deep-submicrometer level, the crosstalk effect between adjacent wires becomes more and more serious, particularly between long on-chip buses. In this paper, we propose a deassembler/assembler technique to eliminate undesirable crosstalk effects on bus transmission. By taking advantage of the prefetch process, where the instruction/data fetch rate is always higher than the instruction/data commit rate, the proposed method incurs almost no penalty in terms of dynamic instruction count. In addition, when the bus width is 128 b, the required number of extra bus wires is only 7 as compared to the 85 extra bus wires needed in the work of Victor and Keutzer.

Negative Bias Temperature Instability (NBTI) has become a major reliability concern in nanoscale designs. Although several previous studies have been proposed to address the NBTI effect during logic synthesis, their performance is limited because of focusing on a certain logic synthesis stage. Additionally, their complicated algorithms are not scalable to large designs. To tackle this, we propose a coordinated and scalable logic synthesis approach, which integrates techniques at different logic synthesis stages, ranging from subject graph to technology mapping and mapped netlist, to achieve an effective NBTI reduction. To our best knowledge, this is the first work that considers and mitigates NBTI impact in subject graphs, the earlier stage of logic synthesis. Experimental results on industry-strength benchmarks show that our approach can achieve 6.5% NBTI delay reduction with merely 2.5% area overhead on average, while a previous work barely gets NBTI delay reduction when the circuits are optimized beforehand, the circuit sizes are large, and standard cell libraries are richer.

Prior works have demonstrated opportunities for achieving more minimized combinational circuits by introducing combinational loops during the synthesis. However, they achieved this by using a branch-and-bound technique to explore possible cyclic dependencies of circuits, which may not scale well for complex designs. Instead of using exploration, this paper proposes a formal algorithm using logic implication to identify cyclifiable structure candidates directly, or to create them aggressively in circuits. Additionally, we also propose a SAT-based algorithm to validate whether the formed loops are combinational or not. The effectiveness and scalability of the identification and validation algorithms are demonstrated in the experimental results performed on a set of IWLS 2005 benchmarks. As compared to the state-of-the-art algorithm, our validation algorithm produces speedups ranging from 2 to 2350 times.

Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, no mapping approaches that consider the existence of defective nanowire segments were proposed. Thus, this paper presents the first defect-aware approach for mapping reconfigurable SET arrays. The experimental results show that our approach can successfully map the SET arrays with 20% width overhead on average in the presence of 5000 ppm defects.

A new approach to monitor the quality of an ultra-thin nitride film has been proposed. The nitride quality is monitored by observing the oxide thickness for the nitride film after wet oxidation since the resistance to oxidation strongly depends on its quality. To obtain a stable oxide thickness without interference from extrinsic factors for process monitoring, monitor wafers without dilute HF solution clean are suggested because the native-oxide containing surface is less sensitive to oxygen and therefore forms the nitride film with stable quality. In addition, the correlation between variable retention time (VRT) performance of a real dynamic random access memory (DRAM) product and oxide thickness from different nitride process temperatures can be successfully explained and this correlation can also be used to establish the appropriate oxide thickness range for process monitoring.