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Over the past decade, research in integrated circuit testing has broadened from digital test to include the testing of analog and mixed-signal devices. More recently, new test techniques for mixed-technology microelectromechanical systems (MEMS) are also receiving attention [1-5]. As MEMS rapidly evolve from single components to highly integrated systems for safety-critical applications, dependability is emerging as an important performance parameter. Fabrication techniques such as silicon micromachining lead to new types of manufacturing defects in MEMS [2]. Moreover, due to their underlying mixed technology and multiple energy domains (e.g., electric, mechanical, and fluidic), such composite microsystems exhibit failure mechanisms that are significantly different from those in electronic circuits. In fact, the 2003 International Technology Roadmap for Semiconductors (ITRS) recognizes the need for new test methods for disruptive device technologies that underly composite microsystems, and highlights it as one of the five difficult test challenges beyond 2009 [6]. [ABSTRACT FROM AUTHOR]

Next-generation system-on-chip designs are expected to be composite microsystems with microelectromechanical and microfluidic components [15,23]. These mixed-signal and mixed-technology systems monolithically integrate microelectronics with microsensors and microactuators, thereby leading to chips that cannot only compute and communicate, but also sense and actuate. This high level of integration is enabling a new class of microsystems targeted at health care, environmental monitoring, biomedical analysis, harmful agent detection for countering bio-terrorism, and precision fluid dispensing [13]. [ABSTRACT FROM AUTHOR]

Although complementary metal-oxide semiconductor (CMOS) chips are projected to continue their dominance for another 10—15 years [1], CMOS technology today faces a number of challenges. Quantum effects will soon make it nearly impossible to further scale devices. Deep sub-micron (DSM) technologies suffer from high leakage, and it is projected that stand-by power and active power for CMOS chips will soon become comparable [2]. Moreover, the high cost associated with chip masks and next-generation fabrication plants poses a formidable economic barrier to commercial nanometer-scale lithography. [ABSTRACT FROM AUTHOR]