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A 3.0 Gsymbol/s/lane receiver is proposed herein to acquire near-grounded high-speed signals for the mobile industry processor interface (MIPI) C-PHY version 1.1 specification used for CMOS image sensor interfaces. Adaptive level-dependent equalization is also proposed to improve the signal integrity of the high-speed receivers receiving three-level signals. The proposed adaptive level-dependent equalizer (ALDE) is optimized by adjusting the duty cycle ratio of the clock recovered from the received data to 50%. A pre-determined data pattern transmitted from a MIPI C-PHY transmitter is established to perform the adaptive level-dependent equalization. The proposed MIPI C-PHY receiver with three data lanes is implemented using a 65 nm CMOS process with a 1.2 V supply voltage. The power consumption and area of each lane are 4.9 mW/Gsymbol/s/lane and 0.097 mm2, respectively. The proposed ALDE improves the peak-to-peak time jitter of 12 ps and 34 ps, respectively, for the received data and the recovered clock at a symbol rate of 3 Gsymbol/s/lane. Additionally, the duty cycle ratio of the recovered clock is improved from 42.8% to 48.3%.

Second harmonic generation (SHG) characteristics of single and multilayer field-effect passivation (FEP) structures were investigated for CMOS image sensor application. By compensating the internal multiple reflection effect, the SHG characteristics of single and multilayer FEP structures were compared under equivalent conditions. Analysis of the time-dependent SHG intensity confirmed that the multilayer FEP structure has a 2.7 times higher SHG intensity than the single-layer structure, and the FEP layer is negatively charged from the initial state. In particular, when atomic layer deposition conditions were varied to control the Al2O3 composition ratio, the SHG demonstrated greater detecting sensitivity than conventional material analysis methods such as RBS and XPS, even though it cannot distinguish the elements. Moreover, SIMS composition analysis verified that the initial state SHG intensity increase under high oxygen ambient Al2O3 growth condition can be attributed to the change of impurities rather than the effect of oxygen areal density increase. [ABSTRACT FROM AUTHOR]

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved. [ABSTRACT FROM AUTHOR]

Summary: In the paper, a single‐slope analog‐to‐digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid‐mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single‐slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion time and achieve the optimal linearity. Owing to this, the pixel using a photodiode working in the integration mode achieves a linear photoconversion characteristics (irradiance to digital number), and the conversion period, which is determined by the darkest parts of a scene, is reduced by an order of magnitude comparing with known ADC solutions. The proposed conversion technique has been validated with the ASIC prototype of a CMOS imager containing photosensors integrated with the ADCs. The ASIC was fabricated in standard 0.18 μm CMOS technology. A specialized measurement system has been used to optimize linearity in the hybrid‐mode conversion (integral nonlinearity below 2 LSB). The conversion period has been reduced 15 times compared with the standard technique. Measurements confirm functionality of the proposed approach, implemented within a small pixel area. [ABSTRACT FROM AUTHOR]

This paper presents methodologies for suppressing the spatial and the temporal noise in a CMOS image sensor (CIS). First of all, it demonstrates by using a longer-length column bias transistor, both the fixed pattern noise (FPN) and temporal noise can be suppressed. Meantime, it employs column-level oversampling delta-sigma ADCs to suppress temporal noise as well as to facilitate the realization of the thermal compensation of dark signal non-uniformity (DSNU). In addition, the image pixels are re-configured as temperature sensors with inaccuracies within ±0.65 °C, between −20 and 80 °C. If the dark current and its non-uniformities are caused by thermal gradients, the obtained in-pixel thermal information can be employed to compensate for the measured dark current by 95 % and DSNU, up to 13 %. All the column-level 13 bit 2nd-order incremental delta-sigma ADCs are measured with SNR around 65 dB and INL around 1.5 LSB, when tested with a −8 dB input signal and sampling at 2 MHz with an oversampling ratio (OSR) of 128, when the full scale voltage is 2 Vp-p. The 4T Pinned Photodiode (PPD) CIS is measured to have a temporal noise of $34~\mu \text{V}$ rms (with an OSR of 128, or, an input referred temporal noise of 0.5 e− rms, with a conversion gain, CG, of $73~\mu \text{V}/ \text{e}^{-}$), a column gain FPN of 0.06 %, a dynamic range (DR) of 92 dB (with OSR = 512), as well as a linearity of 1 %. It has a measured DSNU of 3.2 %, after the thermal compensation using the in-pixel temperature sensors, a dark current of 290 pA/cm2 and 15 pA/cm2, measured at 60 °C, before and after the thermal compensation, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a high-linearity pixel readout circuit and a 10-bit ADC for using in CMOS image sensor. Nonlinearity, total input referred noise power, and power consumption of the proposed readout circuit are − 60 dB, 411 nV2, and 68 µW, respectively. The proposed pixel readout circuit is suitable for use in precision CMOS imagers. All circuits have been designed using TSMC 0.18 µm 1-poly 6-metal standard CMOS process. [ABSTRACT FROM AUTHOR]

The pinned photodiode (PPD) capacitance is an important parameter in CMOS image sensor design since it provides useful information on the charge handling capacity of the photodiode. The model of the dynamic capacitance of the PPD includes a fixed depletion capacitance and a variable diffusion capacitance. The variable component of the photodiode capacitance is estimated by measuring the feedforward voltage at the floating diffusion node. However, the estimated feedforward voltage is highly nonlinear at its full-well condition. In this article, the transfer gate (TG) channel potential is shown to be dependent on the number of charges integrated in the PPD. The nonlinear behavior of TG channel potential influences the effective potential barrier. The nonlinearity observed in the feedforward voltage is also explained using the nonlinear behavior of TG channel potential. In the literature, the influence of the effective potential barrier on the photodiode capacitance models is not taken into account. In this article, the influence of the effective potential barrier on the full-well capacity, feedforward effect, and PPD capacitance is studied. The improved photodiode capacitance model using the effective potential barrier is in good agreement with the measurement results. [ABSTRACT FROM AUTHOR]

This paper presents two low-light-level CMOS image sensors with capacitive transimpedance amplifier (CTIA) and digital correlated double sampling (CDS). In order to achieve high sensitivity for low-light-level CMOS image sensor, the CTIA pixel circuit with a small integration capacitor is used. In order to remove the noise of the low-light-level CMOS image sensor, a digital CDS is designed, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise, pixel fixed-pattern noise (FPN) and the column FPN can be greatly reduced by this digital CDS. Two test chips based on this method with 256 × 256 pixel array are fabricated in a 0.35 μm CMOS technology, one is based on DC-coupled CTIA pixel circuit, and the other one is based on AC-coupled CTIA pixel circuit. These two chips are designed with the same column sigma-delta analog-to-digital (∑∆ ADC), whose resolution is 15-bit. At a frame rate of 7 fps, the low-light-level CMOS image sensor with DC-coupled CTIA pixel circuit and digital CDS can capture recognizable images with the illumination down to 0.05 lux. The low-light-level CMOS image sensor with AC-coupled CTIA pixel circuit can reduce the dark current by reducing the reverse bias voltage of the photodiode. [ABSTRACT FROM AUTHOR]

This article presents an application-optimized QVGA image sensor for low-power, always-on object detection using histograms of oriented gradients (HOG). In contrast to conventional CMOS imagers that feature linear and high-resolution ADCs, our readout scheme extracts logarithmic intensity gradients at 1.5 or 2.75 bits of resolution. This eliminates unnecessary illumination-related data and allows the HOG feature descriptors to be compressed by up to $25\times $ relative to a conventional 8-bit readout. As a result, the digital backend-detector, which typically limits system efficiency, incurs less data movement and computation, leading to an estimated $3.3\times $ energy reduction. The imager employs a column-parallel readout with analog cyclic-row buffers that also perform arbitrary-sized pixel-binning for multi-scale object detection. The log-digitization of pixel gradients is computed using a ratio-to-digital converter (RDC), which performs successive capacitive divisions to its input voltages. The prototype IC was fabricated in a 0.13- $\mu \text{m}$ CIS process with standard 4-T 5- $\mu \text{m}$ pixels and consumes 99 pJ/pixel. Experiments using a deformable parts model (DPM) detector for three object classes (persons, bicycles, and cars) indicate detection accuracies that are on par with conventional systems. [ABSTRACT FROM AUTHOR]

This paper proposes various types of on-chip smart temperature sensors, intended for thermal compensation of dark current in CMOS image sensors (CIS). It proposes four different architectures of metal–oxide–semiconductor (MOS)-based and bipolar junction transistor (BJT)-based temperature sensors inside and outside the CIS array. Both of the MOS-based temperature sensors make use of the thermal dependence of MOS transistors working in the subthreshold region with ratiometric currents and are quantized by the 14-bit first-order incremental delta–sigma analog-to-digital converters (ADCs). Fabricated using 0.18- $\mu \text{m}$ CIS technology and measured on four chips, the proposed temperature sensors are compared, on their resolution and process variability, as well as on their effects on the neighboring image pixels implemented on the same chip. Experimental results show that the MOS-based temperature sensors inside and outside the array consume a power of 36 and $40~\mu \text{W}$ , respectively, both achieving 3-sigma ($\sigma$) inaccuracy less than ±0.75 °C on four different chips, over a temperature range from −20°C to 80 °C at a conversion time of 16 ms. The temperature sensors facilitate the digital thermal compensation of dark current in the CIS array, by at least 80%, in experiments. [ABSTRACT FROM AUTHOR]

In this study, a lens-free dual-color bio-imaging system is developed. This system utilizes a small CMOS image sensor chip as the imager. By coupling alternate lines of blue and yellowgreen filters coated on photodiodes, we can simultaneously detect cyan and yellow fluorescent lights using the device. By equipping the device with a hybrid filter made of a bandpass interference filter, a fiber optic plate (FOP), and a pale-yellow absorption filter, we can achieve an excitation light extinction ratio of approximately -57 dB. By using fluorescent beads of two different colors, we can confirm the operation of the image sensor. Individual images from the cyan and yellow channels can be obtained after data processing, and subsequently the yellow-tocyan image ratio can also be determined. The results show that our device can be used to study Förster resonance energy transfer (FRET) and can thus be applied to investigate the progression of diseases such as cancer. [ABSTRACT FROM AUTHOR]

A $192 \times 128$ pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCSPC) image sensor is implemented in STMicroelectronics 40-nm CMOS technology. The 13% fill factor, $18.4\,\,\mu \text {m} \times 9.2\,\,\mu \text{m}$ pixel contains a 33-ps resolution, 135-ns full scale, 12-bit time-to-digital converter (TDC) with 0.9-LSB differential and 5.64-LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219-ps full-width half-maximum (FWHM) impulse response function (IRF) and is operable at up to 18.6 kframes/s through 64 parallelized serial outputs. Cylindrical microlenses with a concentration factor of 3.25 increase the fill factor to 42%. The median dark count rate (DCR) is 25 Hz at 1.5-V excess bias. A digital calibration scheme integrated into a column of the imager allows off-chip digital process, voltage, and temperature (PVT) compensation of every frame on the fly. Fluorescence lifetime imaging microscopy (FLIM) results are presented. [ABSTRACT FROM AUTHOR]

This paper presents a low-power and small-size CMOS image sensor (CIS) which can be utilized as a power-efficient event detection system. Since high-resolution images are not required for most event detection purposes, power consumption and chip size of the CIS are optimized only for detection performance. The proposed reference voltage scaling with a multiple input sampling scheme allows the CIS to further minimize power consumption by removing a variable gain amplifier, which is commonly placed in a pixel readout channel. The CIS chip employing a 10 μm-pitch 3T active pixel occupies a die area of 0.98 mm × 0.84 mm. The CIS dissipates 181 μW from 3.0 V analog and 1.4 V digital supplies at the maximum frame rate of 252 fps. [ABSTRACT FROM AUTHOR]

A light field image sensor is fabricated on a standard complementary metal–oxide-semiconductor (CMOS) process. The sensor uses two grating layers of various layer-to-layer distances to take advantage of Talbot effect. The horizontal placement of the upper grating relative to the lower one has three types of configurations. By shifting the upper grating to the left or right or aligned position relative to the lower grating, light incident from left, right, and center can be differentiated. Furthermore, color selectivity is analyzed by varying grating slit spacing to favor a particular color’s wavelength to reach Talbot depth. We designed photodiodes each having area of $14\times15\,\,\mu {\mathrm{ m}}^{2}$. We used a 180-nm five-metal CMOS process and achieved an angle differentiation accuracy error within 1.8° for the direct incidence on aligned configuration and within 3.6° of the expected angle for the left- and right-shifted configurations. In addition, we experimented with applying various wavelengths of light even to sensor structures favoring other wavelengths to analyze their effects. Combining these sensor characteristics, we show that red, green, and blue lights, clustered together at three different locations, can be recognized by a set of light field sensors. The sensor set can differentiate 6 different combinations of 3 different color blink sequences per cluster location, thus totaling 18 types of spatial temporal signals. Moreover, repeated measurements showed good immunity to noise. The standard deviation of the measured results between each repetition was less than 5 mV. [ABSTRACT FROM AUTHOR]

Our latest advances in the field of miniaturized optical PM sensors are presented. This sensor combines a hybrid fluidic-optronic CMOS (holed retina) that is able to record a specific irradiance pattern scattered by an illuminated particle (scattering signature), while enabling the circulation of particles toward the sensing area. The holed retina is optically coupled with a monolithic, millimeter-sized, refracto-reflective optical system. The latter notably performs an optical pre-processing of signatures, with a very wide field of view of scattering angles. This improves the sensitivity of the sensors, and simplifies image processing. We report the precise design methodology for such a sensor, as well as its fabrication and characterization using calibrated polystyrene beads. Finally, we discuss its ability to characterize particles and its potential for further miniaturization and integration.

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

CIS221-X is a prototype monolithic CMOS image sensor, optimised for soft X-ray astronomy and developed for the proposed ESA THESEUS mission. A significant advantage of CMOS technology is its resistance to radiation damage. To assess this resistance, four backside-illuminated CIS221-X detectors have been irradiated up to a total ionising dose of 113 krad at the ESA ESTEC 60Co facility. Using unirradiated readout electronics, the performance of each sensor has been measured before and after irradiation. The gain, readout noise and dark current are shown to increase, while the image lag remains unchanged. These measurements are compared to that of similar CMOS image sensors and a possible physical explanation is provided for each result. [ABSTRACT FROM AUTHOR]

This paper demonstrates the simultaneous imaging of multiple wavelengths through realizing a filter-free wavelength image sensor and imaging system. The sensor can identify the center wavelength of the spectrum based on the current ratio using the optical absorption characteristics of silicon at different wavelengths and the potential peak formed at depth. A wavelength imaging system was fabricated and calibrated by evaluating the light intensity and wavelength characteristics of each pixel. First, an experiment was conducted assuming that fluorescence was emitted in part of the pixel region of the image sensor. The system successfully identified different fluorescence wavelengths only in the region irradiated by light corresponding to the fluorescence using the current ratio. Finally, experiments were conducted using fluorescent beads on actual cells and pathogen clusters. Red and green fluorescent beads were placed separately on the sensor, and we succeeded in simultaneously imaging the wavelengths of the three regions where only the excitation light and different fluorescence signals were emitted. These results suggest that multiplexed fluorescence imaging, which considers the interactions between sites or targets, can provide new insights into the biomedical [Display omitted] • Identified wavelength by centroid of spectrum for multiple fluorescences. • Calibration of the realized wavelength-imaging system for intensity and wavelength. • Demonstration of wavelength imaging of the excitation light and fluorescence. • Simultaneous imaging of wavelength differences for two types of fluorescent beads. [ABSTRACT FROM AUTHOR]

The experiments of the 0.18-μm pinned photodiode (PPD) CMOS image sensors (CISs) irradiated by energetic proton radiation with energies of 20, 40, 60, and 100 MeV are presented. The degradations of the mean dark signal, dark signal non-uniformity (DSNU), and fixed pattern noise (FPN) induced by protons are presented. The experimental results show that the mean dark signal degradations of the CISs decrease with increasing proton energy at the same fluence. The degradations induced by proton radiation at different fluence are also presented. The mean dark signals increase with increasing integration time at the same proton fluence. The degradation mechanisms of the CISs induced by energetic protons are analyzed. [ABSTRACT FROM AUTHOR]

This paper presents the design and characterization of high conversion-gain pixels in a 180-nm CMOS image sensor process. By reducing overlapping capacitance between a floating diffusion and transfer gate, output-referred pixel conversion gain as high as 118uV/eand read noise as low as 1.8erms are experimentally achieved without significant lag. A dark current of 38 pA/cm2 is measured at 60°C. Comparison between the proposed devices and a baseline pixel regarding device structure and characterization results is also presented.

A novel quanta image sensor (QIS) jot device with a CMOS compatible junction-field effect transistor (JFET) source follower (SF) is introduced. The device is proposed to further reduce the read noise of QIS jots and ultimately realize a read noise of 0.15e-r.m.s. for accurate photoelectron counting. We take advantage of the small gate capacitance in a p-channel JFET SF to reduce the total capacitance of the floating diffusion, which yields a greatly improved conversion gain of 1.38 mV/e- in TCAD simulation compared to MOSFET SF with the same pitch size. Lower 1/f noise is also anticipated yielding a low input-referred read noise. The device is designed in a 45 nm CMOS image sensor process. The fundamental working principles of this device are discussed, and important functionalities are analyzed with simulation and theory.

Even though computer vision has been developing, edge detection is still one of the challenges in that field. It comes from the limitations of the complementary metal oxide semiconductor (CMOS) Image sensor used to collect the image data, and then image signal processor (ISP) is additionally required to understand the information received from each pixel and performs certain processing operations for edge detection. Even with/without ISP, as an output of hardware (camera, ISP), the original image is too raw to proceed edge detection image, because it can include extreme brightness and contrast, which is the key factor of image for edge detection. To reduce the onerousness, we propose a pre-processing method to obtain optimized brightness and contrast for improved edge detection. In the pre-processing, we extract meaningful features from image information and perform machine learning such as k-nearest neighbor (KNN), multilayer perceptron (MLP) and support vector machine (SVM) to obtain enhanced model by adjusting brightness and contrast. The comparison results of F1 score on edgy detection image of non-treated, pre-processed and pre-processed with machine learned are shown. The pre-processed with machine learned F1 result shows an average of 0.822, which is 2.7 times better results than the non-treated one. Eventually, the proposed pre-processing and machine learning method is proved as the essential method of pre-processing image from ISP in order to gain better edge detection image. In addition, if we go through the pre-processing method that we proposed, it is possible to more clearly and easily determine the object required when performing auto white balance (AWB) or auto exposure (AE) in the ISP. It helps to perform faster and more efficiently through the proactive ISP.

Recent technology advances in CMOS image sensors (CIS) enable their utilization in the most demanding of surveillance fields, especially visual surveillance and intrusion detection in intelligent surveillance systems, aerial surveillance in war zones, Earth environmental surveillance by satellites in space monitoring, agricultural monitoring using wireless sensor networks and internet of things and driver assistance in automotive fields. This paper presents an overview of CMOS image sensor-based surveillance applications over the last decade by tabulating the design characteristics related to image quality such as resolution, frame rate, dynamic range, signal-to-noise ratio, and also processing technology. Different models of CMOS image sensors used in all applications have been surveyed and tabulated for every year and application.

The impact of hydrocarbon-molecular (C3H6)-ion implantation in an epitaxial layer, which has low oxygen concentration, on the dark characteristics of complementary metal-oxide-semiconductor (CMOS) image sensor pixels was investigated by dark current spectroscopy. It was demonstrated that white spot defects of CMOS image sensor pixels when using a double epitaxial silicon wafer with C3H6-ion implanted in the first epitaxial layer were 40% lower than that when using an epitaxial silicon wafer with C3H6-ion implanted in the Czochralski-grown silicon substrate. This considerable reduction in white spot defects on the C3H6-ion-implanted double epitaxial silicon wafer may be due to the high gettering capability for metallic contamination during the device fabrication process and the suppression effects of oxygen diffusion into the device active layer. In addition, the defects with low internal oxygen concentration were observed in the C3H6-ion-implanted region of the double epitaxial silicon wafer after the device fabrication process. We found that the formation of defects with low internal oxygen concentration is a phenomenon specific to the C3H6-ion-implanted double epitaxial wafer. This finding suggests that the oxygen concentration in the defects being low is a factor in the high gettering capability for metallic impurities, and those defects are considered to directly contribute to the reduction in white spot defects in CMOS image sensor pixels.

Fluorescence immunochromatographic assay (FICA) is a rapid immunoassay technique that has the characteristics of high precision and sensitivity. Although image FICA strip readers have the advantages of high portability and easy operation, the use of high-precision complementary metal oxide semiconductor (CMOS) image sensors leads to an increase in overall cost. Considering the popularity of CMOS image sensors in smartphones and their powerful processing functions, this work developed a smartphone-based FICA strip reader. An optical module suitable for the test strips with different fluorescent markers was designed by replacing the excitation light source and the light filter. An android smartphone was used for image acquisition and image denoising. Then, the test and control lines of the test strip image were recognized by the sliding window algorithm. Finally, the characteristic value of the strip image was calculated. A linear detection range from 10 to 5000 mIU/mL (R2 = 0.95) was obtained for human chorionic gonadotrophin with the maximum relative error less than 9.41%, and a linear detection range from 5 to 4000 pg/mL (R2 = 0.99) was obtained for aflatoxin B1, with the maximum relative error less than 12.71%. Therefore, the smartphone-based FICA strip reader had high portability, versatility, and accuracy.

This article presents in-pixel (of a CMOS image sensor (CIS)) temperature sensors with improved accuracy in the spatial and the temporal domain. The goal of the temperature sensors is to be used to compensate for dark (current) fixed pattern noise (FPN) during the exposure of the CIS. The temperature sensors are based on substrate parasitic bipolar junction transistor (BJT) and on the nMOS source follower of the pixel. The accuracy of these temperature sensors has been improved in the analog domain by using dynamic element matching (DEM), a temperature independent bias current based on a bandgap reference (BGR) with a temperature independent resistor, correlated double sampling (CDS), and a full BGR bias of the gain amplifier. The accuracy of the bipolar based temperature sensor has been improved to a level of ±0.25 °C, a 3σ variation of ±0.7 °C in the spatial domain, and a 3σ variation of ±1 °C in the temporal domain. In the case of the nMOS based temperature sensor, an accuracy of ±0.45 °C, 3σ variation of ±0.95 °C in the spatial domain, and ±1.4 °C in the temporal domain have been acquired. The temperature range is between −40 °C and 100 °C.

To meet the urgent market demand for small package size and high reliability performance for automotive CMOS image sensor (CIS) application, wafer level chip scale packaging (WLCSP) technology using through silicon vias (TSV) needs to be developed to replace current chip on board (COB) packages. In this paper, a WLCSP with the size of 5.82 mm × 5.22 mm and thickness of 850 μm was developed for the backside illumination (BSI) CIS chip using a 65 nm node with a size of 5.8 mm × 5.2 mm. The packaged product has 1392 × 976 pixels and a resolution of up to 60 frames per second with more than 120 dB dynamic range. The structure of the 3D package was designed and the key fabrication processes on a 12” inch wafer were investigated. More than 98% yield and excellent optical performance of the CIS package was achieved after process optimization. The final packages were qualified by AEC-Q100 Grade 2.

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).