589 results on '"Boeuf F"'
Search Results
152. Piezoelectric and electrostatic bimetal-based thermal energy harvesters
153. A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications
154. AlGaAs Bragg reflection waveguides for hybrid quantum photonic devices
155. Enhancement of vaccinia virus based oncolysis with histone deacetylase inhibitors
156. Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices
157. Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10nm width
158. High Speed Waveguide Integrated Lateral P-I-N Ge on Si Photodiode with very Low Dark Current
159. Low loss 40 Gbit/s silicon modulator based on interleaved junctions and fabricated on 300 mm SOI wafers
160. Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations
161. High speed silicon modulators on 300 mm SOI wafers
162. Non-replicating rhabdovirus-derived particles (NRRPs) eradicate acute leukemia by direct cytolysis and induction of antitumor immunity
163. 40Gbit/s Germanium Waveguide Photodiode
164. An innovative heat harvesting technology (HEATec) for above-Seebeck performance
165. A Comparative Study of Minimal Supply Voltage of 6T-SRAM at the 16nm node using MASTAR into a Conventional CAD Environment
166. P-I-N Ge on Si photodiodes for high speed and low power consumption receivers
167. On the understanding of mobility degradation mechanisms in advanced CMOS devices: FDSOI versus bulk Tech.
168. New parameter extraction method based on split C-V for FDSOI MOSFETs
169. Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology
170. Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates
171. Scale laws for enhanced power for MEMS based heat energy harvesting
172. Innovative thermal energy harvesting for zero power electronics
173. Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width
174. 28nm FDSOI technology platform for high-speed low-voltage digital applications
175. Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length
176. Analytical modeling of parasitics in monolithically integrated 3D inverters
177. Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology
178. Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width
179. An improved procedure to extract the limiting carrier velocity in ultra scaled CMOS devices
180. Origins of the short channel effects increase in III-V nMOSFET technologies
181. Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances
182. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
183. High speed silicon modulators and detectors
184. Accurate and Ready-to-use Parasitic Capacitances Models for Advanced 2D/3D CMOS Device Structure Comparison
185. Simple and Efficient MASTAR Threshold Voltage and Subthreshold Slope Models for Double Gate Structures
186. Transport characterisation of Ge pMOSFETS in saturation regime
187. Challenges and opportunity in performance, variability and reliability in sub-45nm CMOS technologies
188. Comparative study of circuit perspectives for multi-gate structures at sub-10nm node
189. Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased ground plane FDSOI high-k/metal gate technology
190. Performance of Localized-SOI MOS Devices on (110) Substrates: Impact of Channel Direction
191. UTBOX and ground plane combined with Al2O3 inserted in TiN gate for VT modulation in fully-depleted SOI CMOS transistors
192. Characterization and modeling of capacitances in FD-SOI devices
193. Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX
194. A solution for an ideal planar multi-gates process for ultimate CMOS?
195. Device Engineering to Improve SRAM Static Noise Margin
196. Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications
197. UT2B-FDSOI device architecture dedicated to low power design techniques
198. Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
199. Hybrid Localized SOI/bulk technology for low power system-on-chip
200. Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
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