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The effects of contact geometry and specific contact resistivity on In0.53Ga0.47As (InGaAs) and silicon (Si) nanoscale (18 nm channel length) n-channel FinFETs performance, and the effects of models thereof, are studied using a quantum-corrected semiclassical Monte Carlo method. Saddle/slot, raised source and drain (RSD), and reference end contacts are modeled. Both ideal perfectly injecting and absorbing contacts and those with more realistic specific contact resistivities are considered. Far-from-equilibrium degenerate statistics, quantum-confinement effects on carrier distributions in real-space and among energy valleys and on scattering, and quasiballistic transport are modeled. Silicon ⟨ 110 ⟩ channel and Si ⟨ 100 ⟩ channel FinFETs, multivalley InGaAs channel FinFETs with conventionally reported InGaAs energy valley offsets, and reference idealized Γ-valley-only InGaAs (Γ-InGaAs) channel FinFETs are simulated. Among our findings, InGaAs channel FinFETs are highly sensitive to modeled contact geometry and specific contact resistivity and to the band structure model, while Si channel FinFETs showed still significant but much less sensitivity to the contact models. For example, for idealized unity transmissivity contacts, Γ-InGaAs channel FinFETs performed best for all contact geometries, at least in terms of transconductance, and end contacts provided the best performance for all considered channel materials. For realistic contact resistivities, however, the results are essentially reversed. Silicon channel FinFETs performed best for all contact geometries, and saddle/slot and RSD contacts outperformed end contacts. [ABSTRACT FROM AUTHOR]

Surface passivation using intrinsic a-Si:H (i a-Si:H) films plays a key role in high efficiency c-Si heterojunction solar cells. In this study, we demonstrate improved passivation quality using i a-Si:H films with a gradient-layered structure consisting of interfacial, transition, and capping layers deposited on c-Si surfaces. The H2 dilution ratio (R) during deposition was optimized individually for the interfacial and capping layers, which were separated by a transition layer for which R changed gradually between its values for the interfacial and capping layers. This approach yielded a significant reduction in surface carrier recombination, resulting in improvement of the minority carrier lifetime from 1480 μs for mono-layered i a-Si:H passivation to 2550 μs for the gradient-layered passivation approach. [ABSTRACT FROM AUTHOR]

We investigated the epitaxial growth of Mg-doped Ga2O3 thin films on (0001)-sapphire substrates by pulsed laser deposition (PLD). The thin films were grown on sapphire at 900 °C, with a laser energy of ~ 80 mJ/cm2, under various oxygen partial pressures (PO = 0.01 mT, 10 mT, and 200 mT) using a Ga2O3:Mg(1 mol%) PLD target. The X-ray diffraction, X-ray photoelectron spectroscopy, kelvin probe force microscopy, photoelectron spectroscopy in atmosphere, ultraviolet–visible absorption spectrum, and transmission electron microscopy (TEM) were used to characterize the crystalline nanostructure and doping profile of the as-deposited thin films. The energy band diagram (obtained from the characterization data) reveals a strong shift in the Fermi level (EF) of the Ga2O3:Mg thin films with respect to the undoped Ga2O3 toward the valence band, exhibiting p-type semiconducting behavior. The TEM results show that the films are monocrystalline for both as-deposited pure and Mg-doped Ga2O3. Also, comparing the measured optical band gap between the pure Ga2O3 (EBG ~ 4.85 eV) and Ga2O3:Mg (EBG ~ 5.2 eV) indicates a band gap increase (ΔEBG ~ 0.35 eV) in the doped sample, which can be used for ultraviolet photodetectors and power electronic devices. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) crystalline growth of transition metal dichalcogenides (TMDs) by atmospheric pressure chemical vapor deposition (APCVD) is highly sensitive to any changes in growth parameters. At an optimized growth temperature and transition metal flux, 2D compact domains grow primarily triangular/hexagonal in shape that transform into dendritic structures at higher transition metal flux. With changes in the local flux (or, local chalcogen-to-transition metal vapor ratio), domain morphologies on the substrate vary with distance for locations away from the center. In this work, phase field simulations are carried out to emulate experimentally observed morphology evolution as a function of transition metal flux. Our model demonstrates the critical roles of precursor flux and attachment time in controlling the domain morphologies which is further established by fractal dimension analysis. Evolution of patterns simulated as a function of flux and attachment time can help to identify more precise combination of growth parameters leading to a specific growth mode. Consistent with the experimental observations, the model also reproduces the interaction among multiple domains. Our findings could be useful for achieving controlled growth of 2D domains with desired shape (compact or dendritic) as required for the next-generation electronic and optoelectronic devices, and efficient catalytic applications. [ABSTRACT FROM AUTHOR]

A novel trigate process is described for low-cost embedded CMOS-based one transistor-one capacitor (1T-1C) pseudo-static-random-access-memory (pseudo-SRAM) applications. This method is used for fabricating robust multifinger trigate 3-D capacitors by using a low-cost conventional CMOS trigate FET process with a high-[kappa] gate dielectric gate stack and metal gate, where the resulting cell size is smaller than its 6T SRAM counterparts.

Germanium-silicon (Si/HfSi[O.sub.x]) core-shell nanocrystal (NC) structures are fabricated to work as charge storage nodes in NC flash memories. A more robust interface with low trap density between the high-k dielectric and the NC is achieved, which has helped in suppressing the charges loss due to trap-assisted tunneling of electrons and has resulted in better device performance.

The achievement of significant reduction in P?N junction leakage on direct silicon bonding (DSB) wafers by H2 passivation implants was discussed. Findings reveal that the junction leakage reduction by appropriate passivation implants is useful for migrating to thinner DSB layers without excessive PMOS leakage penalty.

The crossover between ballistic and diffusive transport in III-V nanowire transistors is examined. It was seen that when the drain voltage is increased the ballistic-to-diffusive crossover can be more than nine times as long at room temperature.

A study was conducted to demonstrate that a chaperonin protein lattice could be used as a template to assemble nanocrystal (NC) arrays for Flash memory fabrication. The method provides a new approach that could incorporate different types of NCs from a colloidal suspension for flash memory fabrication.

The k.p bandstructure program is used to measure the full band structure of [110] uniaxially stressed Si, with tensile and compressive stress ranging from 50 MPa to 2GPa in order to study the response of hole mobility and thermal velocity for short channel devices. The results have shown that the increase in both thermal velocity and mobility with compressive stress have continued up to approximately the 4-GPa limit of the simulations where each finally appears near saturation.

A nonvolatile flash memory device is fabricated, using SiGe nanocrystal floating gate with new variable oxide thickness (VARIOT) tunnel barrier. It is found that the writing speed of VARIOT sample is almost hundred times faster at a low programming voltage of 5-8 V compared to the traditional flash memory with single-layer tunnel barrier. The results have shown that a long-charge retention time and a good endurance characteristic write/erase cycles can be achieved at 85 degrees Celsius.

A fast program with the modified Levenberg-Marquardt algorithm is presented for parameter extraction for the 45-nm CMOS technology node from measured gate capacitance and gate current data for nanometer-scale equivalent oxide thickness ultrathin Si[O.sub.2] and high-kappa gate stacks. This program is most effective in combination with information of physical layer thickness and high-kappa dielectric constants to reduce the number of model parameters.

Anomalous asymmetry between accumulation and strong inversion is observed in the measured capacitance-voltage (C-V) curves of metal gate nMOSFETs with Hf[O.sub.2] layers and it is analyzed and extrapolated to still smaller devices and to pMOS devices by using self-consistent Poisson-Schrodinger simulations. The simulations have suggested two mechanisms that result in greater capacitance when the quantum-confined surface carriers are electrons than when they are holes.