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Objective: This study was carried out to determine whether the rate of abnormal placentation is increasing in concurrence with the cesarean section and to assess risk factors and outcomes with multidisciplinary team interventions and anesthetic practices. Study design: Prospective cohort study. Material & Methods: A study was conducted in the department of anaesthesia from January 2014 to December 2017. All candidates under the spectrum of placenta accreta were observed for maternal age, parity, mode of anesthesia, blood loss, and outcome. Results: Out of 109 patients, the preoperative diagnosis of PAS was made up of 100 (91.74%) and intraoperative diagnosis of 9 (08. 26%) patients. According to the mode of anesthesia, 100 (91.74%) patients received GA, and 09 (08.26%) patients received spinal anesthesia. In 06 (05.49%) patients, spinal was converted to GA. Perioperative CPR was done in 05 (04.58%) cases. Out of 109 cases, 83 survived uneventfully, and 21 developed complications. 05 patients expired in the following days. (01 immediately postoperative period, 02 in 1st 24 hours and 02 in 1st 48 hours. Conclusion The rate of placenta accreta increased in conjunction with cesarean deliveries; the most important risk factors were previous cesarean delivery, placenta previa, and advanced maternal age and outcomes improved in a multidisciplinary team intervention.

Marketing plays an extremely significant role in the success of any business. In the hospitality and tourism industry, marketing is a key tool to introduce various destinations to customers and attract them to visit a place or stay in a particular hotel. The forms of marketing have considerably evolved during the past decades owing to enhancements in technology.

The Internet of Things (IoT) is a network of physical things, objects, or devices, such as radio-frequency identification tags, sensors, actuators, mobile phones, and laptops. The IoT enables objects to be sensed and controlled remotely across existing network infrastructure, including the Internet, thereby creating opportunities for more direct integration of the physical world into the cyber world. The IoT becomes an instance of cyberphysical systems (CPSs) with the incorporation of sensors and actuators in IoT devices. Objects in the IoT have the potential to be grouped into geographical or logical clusters. Various IoT clusters generate huge amounts of data from diverse locations, which creates the need to process these data more efficiently. Efficient processing of these data can involve a combination of different computation models, such as in situ processing and offloading to surrogate devices and cloud-data centers.

The hospitality industry is one of the data-rich industries that receives huge Volumes of data streaming at high Velocity with considerably Variety, Veracity, and Variability. These properties make the data analysis in the hospitality industry a big data problem. Meeting the customers’ expectations is a key factor in the hospitality industry to grasp the customers’ loyalty. To achieve this goal, marketing professionals in this industry actively look for ways to utilize their data in the best possible manner and advance their data analytic solutions, such as identifying a unique market segmentation clustering and developing a recommendation system. In this paper, we present a comprehensive literature review of existing big data clustering algorithms and their advantages and disadvantages for various use cases. We implement the existing big data clustering algorithms and provide a quantitative comparison of the performance of different clustering algorithms for different scenarios. We also present our insights and recommendations regarding the suitability of different big data clustering algorithms for different use cases. These recommendations will be helpful for hoteliers in selecting the appropriate market segmentation clustering algorithm for different clustering datasets to improve the customer experience and maximize the hotel revenue.

Convolutional neural networks (CNNs) require high throughput hardware accelerators for real time applications owing to their huge computational cost. Most traditional CNN accelerators rely on single core, linear processing elements (PEs) in conjunction with 1D dataflows for accelerating convolution operations. This limits the maximum achievable ratio of peak throughput per PE count to unity. Most of the past works optimize their dataflows to attain close to a 100% hardware utilization to reach this ratio. In this paper, we introduce a high throughput, multi-threaded, log-based PE core. The designed core provides a 200% increase in peak throughput per PE count while only incurring a 6% increase in area overhead compared to a single, linear multiplier PE core with same output bit precision. We also present a 2D weight broadcast dataflow which exploits the multi-threaded nature of the PE cores to achieve a high hardware utilization per layer for various CNNs. The entire architecture, which we refer to as NeuroMAX, is implemented on Xilinx Zynq 7020 SoC at 200 MHz processing clock. Detailed analysis is performed on throughput, hardware utilization, area and power breakdown, and latency to show performance improvement compared to previous FPGA and ASIC designs., Comment: To be published in ICCAD 2020

Current automotive radar systems are designed to detect objects within an area around the vehicle and provide alerts or other driving assistance features to the driver. The main goal of these driving assistance systems is to increase safety of not only the driver but also increase safety for pedestrians on and around roadways. In this paper, we propose an on-board terrain mapping system (OTMS), which is an automotive radar-based system that extends the automotive safety goals to include mapping and vehicle-to-everything (V2X) communication. The proposed system utilizes a 94 GHz 3-dimensional (3D) pulsed radar to sense the environment around the vehicle and create a 3D model of the environment that can be sampled into a global database for mapping purposes. Objects are also detected and tracked within the model and can be used to provide assistive driving to the user even in adverse weather conditions. The model generated by the system can then be stored locally on the automobile or transmitted to other vehicles or infrastructure for use in mapping, navigation, and/or safety applications. The results validate that the OTMS is a valid system for providing safety and mapping functions for advanced driver assistance systems (ADAS).

Deep neural network (DNN) training is generally performed by cloud computing platforms. However, cloud-based training has several problems such as network bottleneck, server management cost, and privacy. To overcome these problems, one of the most promising solutions is distributed DNN model training which trains the model with not only high-performance servers but also low-end power-efficient mobile edge or user devices. However, due to the lack of a framework which can provide an optimal cluster configuration (i.e., determining which computing devices participate in DNN training tasks), it is difficult to perform efficient DNN model training considering DNN service providers' preferences such as training time or energy efficiency. In this paper, we introduce a novel framework for distributed DNN training that determines the best training cluster configuration with available heterogeneous computing resources. Our proposed framework utilizes pre-training with a small number of training steps and estimates training time, power, energy, and energy-delay product (EDP) for each possible training cluster configuration. Based on the estimated metrics, our framework performs DNN training for the remaining steps with the chosen best cluster configurations depending on DNN service providers' preferences. Our framework is implemented in TensorFlow and evaluated with three heterogeneous computing platforms and five widely used DNN models. According to our experimental results, in 76.67% of the cases, our framework chooses the best cluster configuration depending on DNN service providers' preferences with only a small training time overhead.

In this paper, we propose a fog-assisted architecture for the hospitality industry in smart cities aimed at improving guest experience, building business insights, and increasing revenue. The proposed architecture integrates cloud services platform with the Internet of things (IoT) devices at the network edge through intermediary fog computing nodes to create an architectural paradigm with the benefits of low cost, high responsiveness, energy-efficient computing and communication, scalability, and local and global analytics. To demonstrate the effectiveness and utility of our proposed architecture for the hospitality industry, we present various use cases that can be implemented and/or enhanced by the proposed architecture. We also present a comparison of the proposed fog-assisted IoT architecture against contemporary cloud-IoT architectures in terms of average latency or timeliness. Results verify that offloading IoT tasks to fog nodes provide an improvement of 37% on average over offloading IoT tasks to cloud for the selected benchmarks. We also highlight research challenges and open research directions for fog-assisted architectures for hospitality industry.

The Internet of things (IoT) is leading the world into a future of ubiquitous connectivity. The heterogeneity within the IoT domain necessitates a highly flexible, secure, dependable, and energy-efficient IoT processor architecture. In this paper, we propose a novel processor architecture for IoT that renders energy efficiency, high-performance, flexibility, security, and dependability to meet the diverse application requirements. To address the stringent energy efficiency demands of IoT devices, we propose a two-tiered heterogeneous processor architecture that is composed of a high-performance optimized reconfigurable host processor which controls a number of low-power optimized interface processors. The proposed IoT architecture also incorporates reconfigurability in host processors' computing and communication parameters and co-processor extensions to impart flexibility and additional energy savings. The proposed IoT architecture contains various security co-processor extensions to support various security primitives including encryption and decryption, key generation, integrity verification, and device authentication. Finally, the proposed architecture incorporates reliability and dependability through various hardware-and software-based fault tolerance methods. Experimental results present and compare microarchitecture configurations for host and interface processors obtained through an efficient design space exploration methodology. We have implemented selected security and dependability primitives of our proposed IoT architecture on a Xilinx Spartan-6 field-programmable gate array (FPGA). Results reveal that our proposed IoT architecture can attain a speedup of 47.93x while consuming 2.4x lesser energy for furnishing security and dependability primitives as compared to an optimized ARM implementation of similar security and dependability primitives.

One of the most challenging problems in designing large caches is to devise efficient cache tag storage. Typical large last-level caches often require tens of megabytes of tag storage. Consequently, this large tag storage leads to high latency and energy consumption for a cache tag access, which adversely affect system performance and energy efficiency. In this paper, we propose CT-Cache that exploits the similarity in upper cache tag bits. Our proposed CT-Cache decouples a tag storage into a global tag table and delta tag arrays. The global tag table is a small fully-associative buffer that stores upper tag patterns, which can be shared between multiple cache lines, while the delta tag array stores lower tag bits for each cache line. By avoiding the redundant storage, the CT-Cache significantly reduces the cache tag storage size, which in turn reduces latency and energy consumption of a cache tag access. Evaluation results reveal that the CT-Cache reduces tag storage size by 87.8%, which significantly reduces tag access latency and energy. Owing to the tag storage reduction, the CT-Cache improves performance by 4.7%~16.2% and reduces last-level cache and main memory energy consumption by 20.0%~29.7% compared to the conventional caches that use non-compressed tag storage.

Technological advancements in the silicon industry, as predicted by Moore's law, have enabled integration of billions of transistors on a single chip. To exploit this high transistor density for high performance, embedded systems are undergoing a transition from single-core to multi-core. Although a majority of embedded wireless sensor networks (EWSNs) consist of single-core embedded sensor nodes, multi-core embedded sensor nodes are envisioned to burgeon in selected application domains that require complex in-network processing of the sensed data. In this paper, we propose an architecture for heterogeneous hierarchical multi-core embedded wireless sensor networks (MCEWSNs) as well as an architecture for multi-core embedded sensor nodes used in MCEWSNs. We elaborate several compute-intensive tasks performed by sensor networks and application domains that would especially benefit from multi-core embedded sensor nodes. This paper also investigates the feasibility of two multi-core architectural paradigms—symmetric multiprocessors (SMPs) and tiled many-core architectures (TMAs)—for MCEWSNs. We compare and analyze the performance of an SMP (an Intel-based SMP) and a TMA (Tilera's TILEPro64) based on a parallelized information fusion application for various performance metrics (e.g., runtime, speedup, efficiency, cost, and performance per watt). Results reveal that TMAs exploit data locality effectively and are more suitable for MCEWSN applications that require integer manipulation of sensor data, such as information fusion, and have little or no communication between the parallelized tasks. To demonstrate the practical relevance of MCEWSNs, this paper also discusses several state-of-the-art multi-core embedded sensor node prototypes developed in academia and industry. We further discuss research challenges and future research directions for MCEWSNs.

In this paper, we propose a new architecture for automotive ECUs that incorporates security and dependability primitives with negligible performance, energy, and resources overhead. We implement our proposed ECU architecture on Xilinx Automotive (XA) Spartan-6 FPGA. We demonstrate the effectiveness of our proposed architecture using a steer-by-wire (SBW) application over controller area network with flexible data rate (CAN FD) as a case study that considers major security-relevant use cases and constraints. We also optimize and implement a prior secure and dependable automotive work on the NXP quad-core iMX6Q SABRE automotive board. We further quantify performance, energy, and error resilience of our proposed architecture for our SBW case study. Results reveal that our proposed architecture can attain a speedup of 47.93× while consuming 2.4× lesser energy than optimized SABRE board implementation.

The increased production of electrical energy from various power sources, such as solar, wind, and nuclear, allows smart buildings to be connected with multiple power sources. In an effort to conserve environment, electrical energy usage is gradually shifting towards renewable and green energy sources, such as wind, hydro, and solar. Regardless of power sources, a user demands for continuous energy supply and also desires to minimize the electricity bill. Further, in a dynamic pricing environment, the price of electricity varies throughout the day. In such a dynamic pricing environment, appliance scheduling with multiple power sources tied to a smart home/building is an important research problem. In this paper, we propose a methodology to abet green environment by prioritizing green energy sources and to minimize the electricity cost for the user. Our proposed methodology leverages a smart grid architecture which employs a greedy strategy to select the most feasible power source amongst the available power sources tied to a smart home/building. Our proposed methodology further leverages a neural network-based approach for appliance scheduling that optimizes the use of power sources in a dynamic pricing environment to minimize the total cost of electricity usage.

In recent years, proliferation of the Internet of things (IoT) devices and applications like video processing have caused a paradigm shift in computation requirement and power management in these devices. Furthermore, processing huge amount of data generated by connected IoT devices and meeting real-time deadline requirement of IoT applications is also a challenging problem. To address these challenges, we propose a computation offloading scheme where computing services requested by an IoT device are processed by a relatively resourceful computing devices (e.g., personal computer) in the same local network. In our proposed scheme, both client and server devices tune their tunable parameters, such as operating frequency and number of active cores, to meet the application's real-time deadline requirements. We compare our proposed scheme with contemporary computation offloading models that use cloud computing. Results verify that our proposed scheme provides a performance improvement of 21.4% on average as compared to cloud-based computation offloading schemes.

Wireless sensor networks (WSNs) are distributed systems that have proliferated across diverse application domains (e.g., security/defense, health care, etc.). One commonality across all WSN domains is the need to meet application requirements (i.e., lifetime, responsiveness, etc.) through domain specific sensor node design. Techniques such as sensor node parameter tuning enable WSN designers to specialize tunable parameters (i.e., processor voltage and frequency, sensing frequency, etc.) to meet these application requirements. However, given WSN domain diversity, varying environmental situations (stimuli), and sensor node complexity, sensor node parameter tuning is a very challenging task. In this paper, we propose an automated Markov Decision Process (MDP)-based methodology to prescribe optimal sensor node operation (selection of values for tunable parameters such as processor voltage, processor frequency, and sensing frequency) to meet application requirements and adapt to changing environmental stimuli. Numerical results confirm the optimality of our proposed methodology and reveal that our methodology more closely meets application requirements compared to other feasible policies.

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multicore to exploit this high-transistor density for high performance. Embedded systems differ from traditional high-performance supercomputers in that power is a first-order constraint for embedded systems; whereas, performance is the major benchmark for supercomputers. The increase in on-chip transistor density exacerbates power/thermal issues in embedded systems, which necessitates novel hardware/software power/thermal management techniques to meet the ever-increasing high-performance embedded computing demands in an energy-efficient manner. This paper outlines typical requirements of embedded applications and discusses state-of-the-art hardware/software high-performance energy-efficient embedded computing (HPEEC) techniques that help meeting these requirements. We also discuss modern multicore processors that leverage these HPEEC techniques to deliver high performance per watt. Finally, we present design challenges and future research directions for HPEEC system development.

The third-generation partnership project (3GPP) and 3GPP2 have standardized the IP multimedia subsystem (IMS) to provide ubiquitous and access network-independent IP-based services for next-generation networks via merging cellular networks and the Internet. The application layer Session Initiation Protocol (SIP), standardized by 3GPP and 3GPP2 for IMS, is responsible for IMS session establishment, management, and transformation. The IEEE 802.16 worldwide interoperability for microwave access (WiMax) promises to provide high data rate broadband wireless access services. In this paper, we propose two novel interworking architectures to integrate WiMax and third-generation (3G) networks. Moreover, we analyze the SIP-based IMS registration and session setup signaling delay for 3G and WiMax networks with specific reference to their interworking architectures. Finally, we explore the effects of different WiMax-3G interworking architectures on the IMS registration and session setup signaling delay.

Networked embedded systems typically leverage a collection of low-power embedded systems (nodes) to collaboratively execute applications spanning diverse application domains (e.g., video, image processing, communication, etc.) with diverse application requirements. The individual networked nodes must operate under stringent constraints (e.g., energy, memory, etc.) and should be specialized to meet varying application requirements in order to adhere to these constraints. Phase-based tuning specializes system tunable parameters to the varying runtime requirements of different execution phases to meet optimization goals. Since the design space for tunable systems can be very large, one of the major challenges in phase-based tuning is determining the best configuration for each phase without incurring significant tuning overhead (e.g., energy and/or performance) during design space exploration. In this paper, we propose phase distance mapping, which directly determines the best configuration for a phase, thereby eliminating design space exploration. Phase distance mapping applies the correlation between the characteristics and best configuration of a known phase to determine the best configuration of a new phase. Experimental results verify that our phase distance mapping approach, when applied to cache tuning, determines cache configurations within 1 % of the optimal configurations on average and yields an energy delay product savings of 27 % on average., 26 pages, Springer Design Automation for Embedded Systems, Special Issue on Networked Embedded Systems, 2014

This chapter introduces distributed embedded wireless sensor networks (EWSN) from an optimization perspective and explores optimization strategies employed in EWSNs at different design levels to meet application requirements. It first presents a typical WSN architecture and architectural-level optimizations. The chapter describes sensor node component-level optimizations and tunable parameters. Next, it discusses data link-level medium access control (MAC) optimizations and network-level routing optimizations, and operating system (OS)-level optimizations. After presenting these optimization techniques, the chapter focuses on dynamic optimizations for WSNs. There exists much previous work on dynamic optimizations, but most previous work targets the processor or cache subsystem in computing systems. WSN dynamic optimizations present additional challenges because of a unique design space, stringent design constraints, and varying operating environments. The chapter also discusses the current state of the art in dynamic optimizations such as dynamic voltage and frequency scaling (DVFS) and dynamic network reprogramming.

This chapter proposes an application-oriented dynamic tuning methodology for embedded sensor nodes in distributed embedded wireless sensor networks (EWSNs) based on Markov decision process (MDP). MDP-based dynamic optimization methodology gives a policy that performs dynamic voltage, frequency, and sensing (sampling) frequency scaling (DVFS2) and specifies good quality solution for embedded sensor node parameter tuning for EWSN lifetime. The MDP-based dynamic tuning methodology adapts to changing application requirements and environmental stimuli. The chapter provides implementation guidelines for the proposed dynamic tuning methodology in embedded sensor nodes. The implementation guidelines describe the mapping of MDP specifications (e.g., state space, reward function) in the problem formulation to actual sensor node hardware. The computational complexity focuses on the convergence of the policy iteration algorithm and the data memory analysis for the MDP-based dynamic tuning methodology. The prototype implementation of the MDP-based tuning methodology on hardware sensor platforms is the focus of future work.

To enable in situ autonomous embedded wireless sensor network (EWSN) dynamic optimizations, this chapter proposes an online EWSN optimization methodology that extends static design time parameter tuning. It first presents a review of related work and then provides an overview of dynamic optimization methodology. The chapter also presents online lightweight optimization algorithms/heuristics for the dynamic optimization methodology. The dynamic optimization module determines the sensor node's operating state (tunable parameter value settings) using an online optimization algorithm, such as greedy and a simulated annealing algorithms. The dynamic profiler module records profiling statistics (e.g., wireless channel condition, number of dropped packets, packet size, radio transmission power), and the profiling statistics processing module performs any necessary data processing. The chapter gives experimental results for online optimization algorithms. These results evaluate the greedy and SA algorithms in terms of solution quality and the percentage of state space explored.

This chapter proposes a heterogeneous hierarchical multicore embedded wireless sensor networks (MCEWSN) and the associated multicore embedded sensor node architecture. The multicore embedded sensor node comprises a sensing unit, a processing unit, a storage unit, a communication unit, a power unit, an optional actuator unit, and an optional location finding unit. The chapter elaborates several computation-intensive tasks performed by sensor networks that would especially benefit from multicore embedded sensor nodes. These tasks include information fusion, encryption, network coding, and software-defined radio (SDR). The chapter outlines wireless sensor networking application domains, such as wireless video sensor networks (WVSNs), wireless multimedia sensor networks (WMSNs), satellite-based sensor networks, space shuttle sensor networks (3SNs), aerial-terrestrial hybrid sensor networks (ATHSNs), and fault-tolerant sensor networks, that benefit from MCEWSNs. It also discusses several state-of-the-art multicore embedded sensor node prototypes developed in academia and industry. Finally, the chapter describes research challenges and future research directions for MCEWSNs.

The high-performance energy-efficient embedded computing (HPEEC) domain addresses the unique design challenges of high-performance and low-power/energy embedded computing. This chapter focuses on high-performance and energy-efficient techniques that are applicable to embedded systems (chip multiprocessors (CMPs), systems-on-chip (SoCs), or multiprocessor systems-on-chip (MPSoCs)) to meet particular application requirements. The HPEPEC domain benefits from architectural innovations in processor core layouts, memory design and interconnection networks. The chapter discusses various characteristics of embedded system applications and presents novel architectural approaches to increase performance and reduce energy consumption in parallel embedded systems. It also discusses hardware-assisted middleware techniques for performance and energy optimization of parallel embedded systems and describes software approaches for improving performance and power efficiency of a parallel embedded platform. In addition, it addresses some prominent multicore-based parallel processors and emphasizes on their HPEEC features. Finally, the chapter highlights research challenges and future research directions for HPEPEC.

This chapter presents a novel, queueing theory-based modeling technique for evaluating multicore embedded architectures that do not require architectural-level benchmark simulation. This modeling technique enables quick and inexpensive architectural evaluation, with respect to design time and resources, as compared to developing and/or using existing multicore simulators and running benchmarks on these simulators. Based on a preliminary evaluation using the models, architectural designers can run targeted benchmarks to verify the performance characteristics of selected multicore architectures. The chapter proposes a method to quantify computing requirements of real benchmarks probabilistically. The modeling technique provides performance evaluation for workloads with any computing requirements as opposed to simulation-driven architectural evaluation that can provide performance results for specific benchmarks. The queueing theoretic modeling approach can be used for performance per watt and performance per unit area characterizations of multicore embedded architectures, with varying number of processor cores and cache configurations, to provide a comparative analysis.

This chapter proposes a lightweight dynamic optimization methodology for embedded wireless sensor networks (EWSNs), that intelligently selects appropriate initial tunable parameter value settings by evaluating application requirements, the relative importance of these requirements with respect to each other, and the magnitude in which each parameter effects each requirement. This one-shot operating state obtained from appropriate initial parameter value settings provides a high-quality operating state with minimal design space exploration for highly constrained applications. The chapter presents a dynamic optimization methodology to iteratively improve the one-shot operating state to provide an optimal or near-optimal operating state for less constrained applications. The chapter addresses a lightweight online greedy algorithm that leverages intelligent parameter arrangement to iteratively explore the design space, resulting in an operating state within 2% of the optimal operating state while exploring only 0.04% of the design space.

Next generation of automobiles (also known as cybercars) will escalate the proliferation of electronic control units (ECUs) to implement novel distributed control applications such as steer-by-wire (SBW), brake-by-wire, etc. Although the use of electronic embedded systems improves performance, driving comfort, safety, and economy for the customer; this electronic control of automotive systems makes these systems susceptible to soft errors, which can significantly reduce the availability of these systems. Enhancing reliability and availability at a minimum additional cost is a major challenge in automotive systems design. In this paper, we propose D2CyberSoft—a design automation tool for cybercars that facilitate cybercar designers in selecting designs with minimum cost overhead to make safety-critical automotive functions less vulnerable to soft errors. D2CyberSoft aids designers by providing built-in models, easy to specify inputs, and easy to interpret outputs. We elaborate Markov models that form the basis of D2CyberSoft using SBW as a case study. We further provide evaluation insights obtained from D2CyberSoft.

The next generation of automobiles (also known as cybercars) will increasingly incorporate electronic control units (ECUs) in novel automotive control applications. Recent work has demonstrated vulnerability of modern car control systems to security attacks that directly impact the cybercar's physical safety and dependability. In this paper, we provide an integrated approach for the design of secure and dependable cybercars using a case study: a steer-by-wire (SBW) application over controller area network (CAN). The challenge is to embed both security and dependability over CAN while ensuring that the real-time constraints of the cybercar applications are not violated. Our approach enables early design feasibility analysis by embedding essential security primitives (i.e., confidentiality, integrity, and authentication) over CAN subject to the real-time constraints imposed by the desired quality of service and behavioral reliability. Our method leverages multi-core ECUs for providing fault-tolerance by redundant multi-threading (RMT) and also further enhances RMT for quick error detection. We quantify the error resilience of our approach and evaluate the interplay of performance, fault-tolerance, security, and scalability for our SBW case study.

The Internet of Things (IoT) makes use of ubiquitous internet connectivity to form a network of everyday physical objects for purposes of automation, remote data sensing and centralized management/control. IoT objects need to be embedded with processing capabilities to fulfill these services. The design of processing units for IoT objects is constrained by various stringent requirements, such as performance, power, thermal dissipation etc. In order to meet these diverse requirements, a multitude of processor design parameters need to be tuned accordingly. In this paper, we propose a temporally efficient design space exploration methodology which determines power and performance optimized microarchitecture configurations. We also discuss the possible combinations of these microarchitecture configurations to form an effective two-tiered heterogeneous processor for IoT applications. We evaluate our design space exploration methodology using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH2 benchmarks. The results show that our methodology determines microarchitecture configurations which are within 2.23–3.69 percent of the configurations obtained from fully exhaustive exploration while only exploring 3–5 percent of the design space. Our methodology achieves on average 24.16× speedup in design space exploration as compared to fully exhaustive exploration in finding power and performance optimized microarchitecture configurations for processors.

Convulvularis arvensis is an important weed found in wheat, maize, rice, sugarcane and cotton growing fields. It caused major yield losses in crop plants through competition for water, minerals and nutrients. Prescribed study was conducted to evaluate Convulvularis arvensis for it morphological traits under five different environmental locations. It was found that there was a positive and significant correlation among most of the study traits, fresh plant weight, plant length, leaf length, leaf width leaf area and moisture percentage. The highly contributing trait for fresh weight was found as plant dry weight. From GGE biplot it was found that the location 4 was highly suitable place for better growth and development of Convulvularis arvensis plants. It was suggested that the timely removal or control of Convulvularis arvensis is much necessary to minimize the yield losses of crop plants.

Euphorbia helioscopia is a weed plant that grow in the filed of cop plants and caused yield losses through competition for water, mineral salts and nutrients. It is also grown as medicinal plant to extract various drugs. Prescribed study was conducted to access the genetic variability for morphological traits of Euphorbia helioscopia under four different locations/environmental conditions. It was found that the higher and better performance was predicted under location 4 a compared with other locations. Higher and significant correlation was recorded between fresh weight, leaf area and plant height. Regression analysis predicted that higher contributing traits were fresh inflorescence weight and dry weight. It was suggested from results that the plant population of Euphorbia helioscopia should be controlled to minimize yield losses in crop plants.

Rumex dentatus is an important crop plant weed and also serves as medicinal plant through out the world. Present study was conducted to access the genetic variability and association among morphological traits of Rumex dentatus under four different locations. The results indicated that the fresh plant weight was significant related with dry weight and moisture contents/percentage in Rumex dentatus plants. The location 3 serves as the best place for growth and development of Rumex dentatus. Hence, it was suggested that the growth and development of Rumex dentatus should be controlled through proper techniques to reduce yield losses in crop plants.

Lepidium draba is a weed plant usually grown where the conditions are moist like road side, ditch banks, rang lands and pastures. It is a fast growing weed plant that competes with crop plants for water, mineral nutrients, light and plays as a hiding place for insects. The prescribed study was carried out to evaluate morphological traits of Lepidium draba under four different locations. It was found from results that plant fresh weight and moisture contents were relatively higher for under studied locations. There was a strong and significant correlation among fresh weight, dry weight, moisture contents and plant height. From regression analysis it was predicted that plant dry weight and moisture contents played an important role in improving fresh plant weight. GGE biplot showed location 4 as best environmental area for propagation of Lepidium draba. It was suggested from current study that the plant population of Lepidium draba to minimize yield losses in crop plants and reducing competition between Lepidium draba and crop plants.

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, there exists a plethora of multi-core architectures and the suitability of these multi-core architectures for different embedded domains (e.g., distributed, real-time, reliability-constrained) requires investigation. Despite the diversity of embedded domains, one of the critical applications in many embedded domains (especially distributed embedded domains) is information fusion. Furthermore, many other applications consist of various kernels, such as Gaussian elimination (used in network coding), that dominate the execution time. In this paper, we evaluate two embedded systems multi-core architectural paradigms: symmetric multiprocessors (SMPs) and tiled multi-core architectures (TMAs). We base our evaluation on a parallelized information fusion application and benchmarks that are used as building blocks in applications for SMPs and TMAs. We compare and analyze the performance of an Intel-based SMP and Tilera's TILEPro64 TMA based on our parallelized benchmarks for the following performance metrics: runtime, speedup, efficiency, cost, scalability, and performance per watt. Results reveal that TMAs are more suitable for applications requiring integer manipulation of data with little communication between the parallelized tasks (e.g., information fusion) whereas SMPs are more suitable for applications with floating point computations and a large amount of communication between processor cores.

Technological advancements in wireless communications and embedded systems have led to the proliferation of wireless sensor network (WSN) applications, each with varying application requirements (i.e., lifetime, throughput, reliability, etc.). Sensor node tunable parameters enable WSN designers to specialize/tune a sensor node to meet application requirements, but however, parameter tuning is a challenging process that requires designer expertise to consider sensor node complexities and changing environmental stimuli. In this paper, we develop lightweight, online optimization algorithms for sensor node parameter tuning, which enables dynamic optimizations to meet application requirements and adapt to changing environmental stimuli. Results reveal that our online optimizations quickly converge to a near optimal solution using minimal computational and storage resources, and are thus amenable for implementation on resource and energy-constrained sensor nodes.

Advancements in silicon technology, micro-electro-mechanical systems (MEMS), wireless communications, and digital electronics have led to the proliferation of wireless sensor networks (WSNs) in a wide variety of application domains including military, health, ecology, environment, industrial automation, civil engineering, and medical. This wide application diversity combined with complex sensor node architectures, functionality requirements, and highly constrained and harsh operating environments makes WSN design very challenging. One critical WSN design challenge involves meeting application requirements such as lifetime, reliability, throughput, delay (responsiveness), etc. for myriad of application domains. Furthermore, WSN applications tend to have competing requirements, which exacerbates design challenges. For example, a high priority security/defense system may have both high responsiveness and long lifetime requirements. The mechanisms needed for high responsiveness typically drain battery life quickly, thus making long lifetime difficult to achieve given limited energy reserves. Commercial off-the-shelf (COTS) sensor nodes have difficulty meeting application requirements due to the generic design traits necessary for wide application applicability. COTS sensor nodes are mass-produced to optimize cost and are not specialized for any particular application. Fortunately, COTS sensor nodes contain tunable parameters (e.g., processor voltage and frequency, sensing frequency, etc.) whose values can be specialized to meet application requirements. However, optimizing these tunable parameters is left to the application designer. Optimization techniques at different design levels (e.g., sensor node hardware and software, data link layer, routing, operating system (OS), etc.) assist designers in meeting application requirements. WSN optimization techniques can be generally categorized as static or dynamic. Static optimizations optimize a WSN at deployment time and remain fixed for the WSN’s lifetime. Whereas static optimizations are suitable for stable/predictable applications, static optimizations are inflexible and do not adapt to changing application requirements and environmental stimuli. Dynamic optimizations provide more flexibility by continuously optimizing a WSN/sensor node during runtime, providing better adaptation to changing application requirements and actual environmental stimuli. This chapter introduces WSNs from an optimization perspective and explores optimization strategies employed in WSNs at different design levels to meet application requirements 13