Search

Three-phase inverters for grid-connected applications typically require some form of grid voltage phase detection in order to properly synchronize to the grid and control real and reactive power. This phase detection is usually based upon some type of grid voltage sensing. However, in this work, a method is proposed, whereby the phase angle of the grid can be accurately identified solely via the grid current feedback. In the proposed current-control scheme, the only measurement is the output inverter current, and no phase-locked loop (PLL) exists within the scheme. This phase observer is incorporated into a current controller, which can manage the injected power to the grid. The design of this combined observer/controller system is motivated and validated via a Lyapunov stability analysis. The performance of the proposed control scheme has been compared with the conventional PI PLL-based control scheme that needs both a grid voltage and a current sensors. Experimental results utilizing a Controller+ Hardware-in-the-Loop test bed have been presented in order to validate the proposed observer/controller scheme under normal operation, weak grid, distorted grid, and faulty grid conditions. To summarize, this scheme archives current control for a grid-connected inverter using only current feedback. In comparison, traditional methods require voltage and current feedback along with a PLL to synchronize with the grid creating a cascaded closed-loop control system.

This article presents the analytical modeling of synchronous class E rectifiers with the load-independent operation, which achieves zero-phase-angle input impedance, soft-switching over the entire load range with a constant voltage gain. The optimal design of the synchronous class E rectifier is proposed to realize both zero-voltage-switching turn- on and zero-current-switching turn- off at the expected output power. An $ LCC$ - $S$ compensated MHz-WPT topology, which comprises the push–pull class E inverter and rectifier with the load-independent operation, is proposed to achieve the fully soft-switching and a nearly constant voltage gain over the entire load range. The efficiency improvement of the compensation network is also investigated to provide a design methodology for the proposed topology. A $ 6.78$ -MHz WPT prototype, along with an alternative phase detector using an auxiliary coil to realize phase detection, is built to validate the analytical model and the proposed methodology. The system efficiency reaches $ \text{86.7}\%$ at $ 214$ -W output. The synchronous push–pull class E rectifier maintains soft-switching over the load range, and the rectification efficiency reaches $ 94.6\%$ .

The AC fault ride-through and support capability of line commutated converter based high voltage direct current (LCC-HVDC) have significant influence on the safe operation of power system. The ability of phase locked loop (PLL) to synchronize with the voltage phase under AC faults would affect the recovery performance of LCC-HVDC systems. This paper analyzes the influence of the conventional PLL on the subsequent commutation failure (SCF) of LCC-HVDC systems and points out that the conventional PLL has some problems such as slow dynamic response, significant frequency fluctuation, and coupling of phase and frequency detection under fault conditions. A novel PLL is proposed to address the problems. Cascade delayed signal cancellation operators are combined with a mathematical filter, forming a hybrid pre-filter to extract fundamental positive sequence voltage for the PLL. To reduce the fluctuation of PLL's frequency during AC faults, the estimated frequency is fixed when the fault is detected by a fault detector. As a consequence, the decoupling between phase detection and frequency detection is realized, and the proposed PLL's dynamic response performance is enhanced. Simulation results show that the proposed PLL can provide accurate phase reference for the DC control system and reduce the probability of SCFs of LCC-HVDC system.

A significant part of all types of measurements performed in modern industry and science are measurements of gas, liquid or other media. This is important because there are many processes where you need to clearly control the parameters of the environment - pressure, density, etc. The object of research are MEMS gas density sensors. The subject of the research is to eliminate the shortcomings of existing similar systems, increase the accuracy of measurement and range of measured gas pressures and safe operation of the system in critical conditions. The aim of the work is to implement a gas density sensor based on a crystal, using auxiliary functional modules, to monitor the operation of the system and to obtain a sophisticated functional device that will be easy to use. Several prototypes are considered, where a miniature cantilever is used as a sensitive element. The disadvantage of such systems is that the accuracy of measurement depends on the support of the cantilever and the gas pressure. Also in the prototype [3] it is noted that the measurement time of one sample lasts about 2 minutes, which is very significant. In the course of work the methods of determination of thermophysical parameters of the environment with use of primary converters on MEMS technology which are made on structure of a heater, a sensitive element and passive components are analyzed. Calculations for determination of gas density are also described. The implementation of a complete, functional sensor for measuring gas parameters based on a programmable system on a crystal based on Cypress PSoC 5 is considered. This system allows us to implement a complex measuring device on almost one crystal because this system has in its structure a certain set of already built-in analog and digital units. The main advantage of PSoC5 is the ability to dynamically reconfigure the system during operation. That is, having one set of elements, we can build on it a number of different schemes without stopping the measurement process. PSoC Designer software configures built-in units such as DAC, iDAC, ADC. The configuration of these units and connection to them of external elements, such as thermistors and a thermal heater are given. Simulation of the given scheme is carried out and results in a graphic kind are resulted. The main principle of the device is the dependence of temperature attenuation on the environment. The idea is to compare the phase shift between two harmonic signals. One signal is a reference signal, and the other is a signal that is recorded by a thermal sensor after the temperature wave passes through the measuring medium. Since this signal will pass with a certain delay then the phases of the reference signal and the measured will be shifted. Therefore, the phase difference between these signals will depend on the density of the medium through which the heat wave passes. In the conclusion of work both advantages and lacks of the offered method which have been proved on the basis of comparison with other already known similar methods are considered., Об’єктом дослідження є МЕМС сенсори густини газу. Предметом дослідження є усунення недоліків вже існуючих схожих систем, збільшення точності вимірювання і діапазону вимірюваних тисків газу і безпечне функціонування системи в критичних умовах. Метою роботи є реалізація датчику вимірювання густини газу на основі одного кристала, з використанням допоміжних функціональних модулів, для контролю роботи системи і отримати довершений функціональний прилад, який буде легкий у використанні. В ході роботи аналізуються методи визначення теплофізичних параметрів середовища з використанням первинних перетворювачів по технології МЕМС, які виготовляються по структурі нагрівач, чутливий елемент і пасивні компоненти. Також описуються розрахунки для визначення, густини газу. Розглядається реалізація повного, функціонального датчика вимірювання параметрів газу на основі програмованої системи на кристалі на основі Cypress PSoC 5. У висновках роботи розглядаються як переваги так і недоліки запропонованого методу, які були обґрунтовані на основі порівняння з іншими вже відомими схожими методами.

Purpose The purpose of this paper is to present gait analysis for five different terrains: level ground, ramp ascent, ramp descent, stair ascent and stair descent. Design/methodology/approach Gait analysis has been carried out using a combination of the following sensors: force-sensitive resistor (FSR) sensors fabricated in foot insole to sense foot pressure, a gyroscopic sensor to detect the angular velocity of the shank and MyoWare electromyographic muscle sensors to detect muscle’s activities. All these sensors were integrated around the Arduino nano controller board for signal acquisition and conditioning purposes. In the present scheme, the muscle activities were obtained from the tibialis anterior and medial gastrocnemius muscles using electromyography (EMG) electrodes, and the acquired EMG signals were correlated with the simultaneously attained signals from the FSR and gyroscope sensors. The nRF24L01+ transceivers were used to transfer the acquired data wirelessly to the computer for further analysis. For the acquisition of sensor data, a Python-based graphical user interface has been designed to analyze and display the processed data. In the present paper, the authors got motivated to design and develop a reliable real-time gait phase detection technique that can be used later in designing a control scheme for the powered ankle-foot prosthesis. Findings The effectiveness of the gait phase detection was obtained in an open environment. Both off-line and real-time gait events and gait phase detections were accomplished for the FSR and gyroscopic sensors. Both sensors showed their usefulness for detecting the gait events in real-time, i.e. within 10 ms. The heuristic rules and a zero-crossing based-algorithm for the shank angular rate correctly identified all the gait events for the locomotion in all five terrains. Practical implications This study leads to an understanding of human gait analysis for different types of terrains. A real-time standalone system has been designed and realized, which may find application in the design and development of ankle-foot prosthesis having real-time control feature for the above five terrains. Originality/value The noise-free data from three sensors were collected in the same time frame from both legs using a wireless sensor network between two transmitters and a single receiver. Unlike the data collection using a treadmill in a laboratory environment, this setup is useful for gait analysis in an open environment for different terrains.

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of operation up to 30 GHz, and the dead zone equal to 1 ps. Compared to the conventional PFD based on CMOS technology, its dead zone and power consumption are lower. In addition, the effects of blocks’ parameters including the phase detector, which affect the operation of the phase locked loop, or delay locked loop, are systematically analyzed.

This brief presents an auxiliary feed-forward noise cancellation (AFFNC) technique that can be applied to a generic Type-II ring oscillator (RO) PLL. The AFFNC technique uses a stand alone sub-sampling phase detector (SSPD) embedded into an alignment loop to extract and cancel noise from the RO output. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also presented. By using both the reference edges, higher cancellation bandwidth is achieved in DS-AFFNC. The phase-domain model developed for AFFNC and DS-AFFNC show a 2.9x and 3.9x integrated jitter reduction respectively.

The satellite laser ranging method is based on measuring the transit time of a laser pulse from the transmitter to the satellite and back to the receiver. A special feature of the TPL telescope is that the laser signal is transmitted and received by the same telescope. This requires auxiliary equipment to separate these signals. In addition, this telescope is also used for visual tracking of the object, which adds complexity to the optical design. In most cases, the signals are separated mechanically using rotating mirrors. In one position, the mirrors transmit the signal to a specific channel, and they reflect the optical signal into another channel in the other position. The rotational speed of the mirrors corresponds to the frequency of the laser transmitter. Both mirrors rotate at the same frequency but with a different phase. A logic circuit built on two D-triggers and one 2-input NAND element is used as a phase detector. The paper discusses the scheme and principle of operation of the device for mirror synchronization by signals of the control computer and mirror position sensors. This device has been successfully used at the Riga-1884 laser location station of the University of Latvia.

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB.

A new topology that generates a DC voltage whose value is depending on the phase difference of two input RF signals is presented. It is implemented by the mixer concept. With the use of microwave photonics, the mixer-based phase detector can be operated over a very wide frequency range. It also has the advantages of high phase detection resolution, small phase detection error, and small DC offset and phase offset. The phase detector can be constructed using off-the-shelf components including a single integrated optical modulator and a low-speed balanced detector. Measured results on the phase detector demonstrate a 0° to 180° RF signal phase difference detection range for 3.5 GHz to 18 GHz input RF signal frequencies, less than ±3° phase detection error and 2° phase detection resolution.

Frequency-modulated continuous-wave (FMCW) interference, as a new technology of laser interferometry, has the advantages of length traceability, large range, high accuracy, simple structure, and optical fiber transmission. Based on the formula of FMCW laser interference displacement, a zero-crossing phase detection algorithm is proposed, which can accurately calculate the initial phase of a cosine signal in a modulation period, and it is successfully applied to the contact laser interference displacement sensor. The experimental results show that the FMCW technology based on the zero-crossing phase detection algorithm can achieve the technical specifications of the contact displacement sensor with a measurement range greater than 15 mm and the standard deviation is less than 0.01 μm. The conversion of noncontact measurement to contact measurement can realize the direct measurement of workpieces with complex surface conditions on the production line, breaking through the limitation of optical measurement and expanding the application of optical fiber interferometry.

This paper analyses the noise performances of coupled phase-locked loops, providing closed-form expressions for the transfer functions of the various noise sources, and presents a novel coupling topology, whose goal is the reduction of both in-band and out-of-band phase-noise. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. It will be demonstrated that in this architecture the impact of the main PLL noise sources, the oscillator and the reference buffer, is efficiently traded with the power dissipation without resorting to lossy and area-consuming passive coupling networks. The work then shows how to derive the set of design parameters that grant the desired performance for a given case study. The entire procedure is verified by simulations.

A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm2. The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from −71.4% to −18.5% at 3.0GHz.

In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB.

A 180-GHz minimum shift keying (MSK) receiver (RX) using a phase-locked loop (PLL), which self-synchronizes the carrier frequency, is demonstrated. The mixer-first RX is fabricated in a 65-nm CMOS process. A double-balanced anti-parallel-diode-pair sub-harmonic mixer performs the phase detection, reducing the frequency of local oscillator (LO) by half. Tunable zeros realized by series inductors are used to improve the stability and to increase the data rate handling capability. Without external LO synchronization, the RX demodulates MSK signals at 10 Gb/s with a bit error rate (BER) $\times $ 10−5. The BER at 10 Gb/s is the lowest and the data rate of 12.5 Gb/s is the highest for PLL RXs.

In this article, we develop the theory of a special type of optoelectronic phase-locked loop (PLL). The output signal of this type of PLL is in the electrical domain and its reference oscillator, typically a mode-locked laser, operates in the optical domain. The PLL uses a balanced optical microwave phase detector (BOMPD). In order to model the optoelectronic PLL, the nonlinear characteristic function and the gain of the BOMPD are derived analytically. Using the results of the phase detector analysis, the theory of an optoelectronic PLL using such a phase detector is developed. Based on the theoretical analysis, a broadband optoelectronic frequency synthesizer with a programmable frequency range from 2 to 20 GHz is designed and implemented. Phase noise measurements show that the optoelectronic PLL frequency synthesizer achieves an integrated rms-jitter (1 kHz–100 MHz) of less than 4 fs in the frequency range from 5 to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband PLL frequency synthesizer achieving sub-10-fs integrated rms-jitter (1 kHz–100 MHz) in the frequency range from 3 to 20 GHz. A comparison with best-in-class laboratory-grade frequency synthesizers in this frequency range shows that this synthesizer achieves lower phase noise than any electronic frequency synthesizer for offset frequencies larger than 2 kHz.

Frequency-domain diffuse optical imaging (fd-DOI) systems require accurate phase and amplitude measurement of the modulating signal for precise calculation of optical properties of a medium. To reach this accuracy, the current time-resolved DOI methods are prohibitively complex, bulky, and expensive, and generally not compatible with the vision of compact wearable devices. In this dissertation, for the first time, a complete fd-DOI transceiver unit is implemented on a chip. Using only standard CMOS technology to reduce the cost, this transceiver paves the way for complete integration of a time-resolved DOI SoC. Novel methods for measuring phase and amplitude are introduced to enable accurate measurement over more than a decade of frequencies and 60 dB input dynamic range. The systems reaches an optical sensitivity of -57 dBm at 400 MHz modulation frequency with phase and amplitude measurement accuracy of 2 degree and 1dB, respectively. Works like this along with the advances in the vertical cavity surface emitting lasers (VCSELs) and CMOS-integrated photodiodes will enable the development of new methods and devices with the accuracy, precision, and power of time-resolved techniques, but the simplicity, low cost, and wearability of CW devices.

Purpose A high-precision gyroscope is an important tool for accurate positioning, and the amplitude stability and frequency tracking ability of the drive control system are important and necessary conditions to ensure the precision of micro-electro-mechanical systems (MEMS) gyroscopes. To improve the precision of MEMS gyroscopes, this paper proposes a method to improve the amplitude stability and frequency tracking ability of a drive control system. Design/methodology/approach A frequency tracking loop and an amplitude control loop are proposed to improve the frequency tracking ability and amplitude stability of the drive control system for a MEMS gyroscopes. The frequency tracking loop mainly includes a phase detector, a frequency detector and a loop filter. And, the amplitude control loop mainly includes an amplitude detector, a low-pass filter and an amplitude control module. The simulation studies on the frequency tracking loop, amplitude control loop and drive control system composed of these two loops are implemented. The corresponding digital drive control algorithm is realized by the Verilog hardware description language, which is downloaded to the application-specific integrated circuits (ASIC) platform to verify the performances of the proposed method. Findings The simulation experiments in Matlab/Simulink and tests on the ASIC platform verify that the designed drive control system can keep the amplitude stable and track the driving frequency in real time with high precision. Originality/value This study shows a way to design and realize a drive control system for MEMS gyroscopes to improve their tracking ability. It is helpful for improving the precision of MEMS gyroscopes.

Phase rotator-based digital clock and data recovery (CDR) using multi-level bang-bang phase detector (ML-BBPD) and time to digital converter (TDC) is analyzed at system and circuit level. A model is proposed for calculating the quantization noise and bit error rate (BER), in order to evaluate the important parameters in CDR design. The jitter analysis is done based on the probability density function achieved from the quantization noise error of the BBPD and TDC. The analysis of ML-BBPD is shown that by increasing the number of sampling clocks, the quantization noise and consequently the jitter and BER are significantly reduced. Also, it is shown that by improving the resolution of the TDC and increasing number of delay cells for the purpose of keeping fixed the dynamic range, the output jitter of TDC is decreased. In the proposed model and also simulation, it is approved that by increasing the ratio of RMS input Gaussian jitter to the quantization step, the output jitter reaches to its saturated value. To prove the jitter model, the goodness of fit test based on Kolmogorov–Smirnov test is used and in addition, the simulation is provided for circuit level CDR. The circuit level simulation is done in TSMC 65 nm CMOS technology. The CDR is worked under 1 V supply voltage at 480Mbit/s bit rate useful for USB2 applications. The CDR dissipates 913 µW power and generates 0.258 ps RMS jitter, while it occupies 166 µm × 104 µm chip area.

Step detection is very important for the foot-mounted Pedestrian Dead Reckoning (PDR) system. To deal with the false detection caused by variant stepping modes and occasional disturbance, a novel robust step detection algorithm is proposed. The proposed algorithm detects the number of steps and zero-velocity phase using data from inertial sensors mounted on the user’s foot. It includes two parts: a novel anti-fault detection algorithm and a novel zero-velocity detection method, which are used to reduce the over-detection and miss-detection of steps, respectively. Field tests show that the proposed approach is robust under varying motion speeds in different step modes for different persons and the average accuracy of the proposed algorithm is 99.94% in all motion modes, which significantly exceeds conventional estimation approaches in terms of step detection accuracy.

Objectives: To design and develop a simple, robust, and novel SOGI based frequency lock loop approach with DC-offset elimination capability for extracting precise phase angle of the grid voltage. As the additional objective of the work is to utilize the unused capacity of the PV system for providing reactive power support to the grid. Method: The second-order generalized integrator (SOGI)-Frequency Look loop (FLL) is implemented to achieve precise phaseangle for the control system, filtering capability for the adaptive frequency tuning as well as an orthogonal signal generation. The DC blocker is designed to eliminate the dc-offset generated during analog to digital conversion without compromising the dynamics of the system. To achieve the second objective, the virtual two-axis current control is simulated and experimented on in a single-phase grid-assisted system. Synchronous-frame current controllers are designed to inject active power to the grid and also ensure the unity power factor by providing reactive power support to the grid. The developed system is simulated using MATLAB /Simulink and implemented on the experimental stepup. Findings: The precise phase-angle is extracted from the grid voltage during the abnormal grid conditions like frequency shift, distorted by harmonics, and dc-offset. The DC-offset can be eliminated without adopting high-order FLLs by choosing the appropriate control parameter and DC cancellation block (DBC). Novelty: This study presents simple, efficient, novel SOGI based control that provides assurance of power quality as well as injection of active power injection into the grid using the virtual two-axis reference frame power control. The experimental and simulation results confirm that the presented control approach provides fast and accurate phase angle extraction in the grid synchronization with DC-offset cancellation. Keywords: Grid synchronization; STM32F407VG microcontroller; WAIJUNG Blockset; phase detection; Phase Locked Loop (PLL); virtual two axis reference frame power control

Gait phase analysis is widely used in disease diagnosis, rehabilitation training, and other fields by studying the characteristics of human gait. It systematically evaluates human body’s skeletal muscles and nerves with combined disciplines. Microelectromechanical system (MEMS) inertial sensors are extensively used in attitude detection because of its high-precision, portability, and good real-time performance in time-domain analysis. In this article, we presented a multi-degree-of-freedom MEMS gait detection method, which resolved the problems of single sensor and limited gait phase. We designed a sensor-based gait signal acquisition system, in which gait data acquisition program and feature analysis algorithm were compiled to verify the feasibility of the proposed method. We performed coordinate transformation and corrected position information to eliminate the gait phase detection error caused by random noise interference. Acceleration and angular velocity information were collected from 20 experimenters. We applied an adaptive threshold gait phase detection algorithm to classify the gait information collected by single sensor. To improve the results of gait phase classification, we used multisensor redundant measurement to analyze characteristics of five gait phases. The acceleration and angular velocity information collected by the three sensors placed at instep, ankle, and thigh were input into support vector machine (SVM). The classification results of the five gait phases are approximately 90%. Lastly, we built a human body structure model to simulate human motion in real time, realizing the real-time gait phase detection, which proves effectiveness of the proposed algorithm.

In this paper, a novel closed-loop synchronization algorithm is proposed based on the linear phase angle detection. The linear phase detection is performed by the inverse tangent (atan2) trigonometric function, while the frequency tracking is performed by a proportional-integral (PI) loop filter and phase integrator. By using the linear phase detection, the linear phase-locked loop (PLL) is employed, which is simpler to implement and to tune, and which also performs better for large frequency and phase variations when compared to conventional PLL algorithms. Also, the novel technique operates consistently for a whole range of designated PLL crossover frequencies when compared to existing PLL techniques, which makes it a better candidate when higher filtering is required of higher harmonics and measurement noise. When compared with existing algorithms that use atan function for phase angle estimation, the novel algorithm enables the frequency estimation that does not include differentiation, which improves the resulting algorithm immunity to measurement noise and higher harmonics. The novel PLL is tested by simulation and experimental runs.

This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with −12 bit-error rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm2 in a 28-nm CMOS technology.

Microwave measurement system, which acquires the microwave parameters including frequency, phase, and amplitude information, is one of the backbone parts in modern radio frequency (RF) systems. In this article, a simple and novel optical approach is proposed to perform broadband in-phase/quadrature (I/Q) downconverter and is applied in Doppler frequency shift (DFS) and phase measurement. In the proposed approach, a Mach–Zehnder modulator (MZM) is used to modulate both RF and local oscillator (LO) signals. A Sagnac loop structure and optical coupler are used to suppress the optical carrier. A dense wavelength division multiplexer (DWDM) and two photodiodes (PDs) are used to build I/Q channels. The proposed approach has an all-optical structure and no frequency-dependent electronic devices are needed. In the experimental demonstration, the I/Q downconverter achieves low phase imbalance ( $\text {dB}\cdot \text {Hz}^{2/3}$ ) over an ultrawide operating frequency. When DFS measurement is implemented using the I/Q downconverter, the microwave DFS is measured with a maximum measurement error of 8 Hz, and a clear direction can be obtained. When the system is applied for phase detection, the phase shift is successfully estimated with a measurement error of less than 7°.

This letter proposes a mm-wave fractional-N reference-oversampling (ROS) all-digital phase-locked loop (ADPLL) for 5G wireless applications utilizing a relatively low but standard reference frequency. The $4\times $ ROS phase detector (PD) increases the phase-detection rate $4\times $ in a power-efficient manner in order to reduce the in-band phase noise contributed from the PD. This improves the overall figure of merit (FoM) and locking speed. A class-F3 oscillator generates both ~10GHz and its third harmonic. The former is fed to the feedback divider, while the latter is extracted to generate the ~30-GHz output. The fractional phase and reference distortions are compensated in digital with the assistance of DACs. The proposed ROS-ADPLL is implemented in 28-nm CMOS. Using a standard 50-MHz reference frequency, it achieves 237-fs rms jitter while consuming only 11.9mW, reaching best-in-class FoMjitter-N of −269.3dB.

Due to the noncontact, nonradiative, and low-cost features, magnetic induction tomography (MIT) is highly applicable in conductive medium imaging. To meet the demands of low-conductivity medium imaging in industrial and biomedical applications, a portable, flexible, and extensible MIT system with high-phase detection precision is proposed. The proposed system is designed with different modules. Therefore, it is flexible to extend and meet different applications. The sensor modules can be used as both the excitation and the detection. The detected signal is directly demodulated at the sensor end, which avoids the external interference that may be introduced into the transmission of the detected signal. A phase demodulation part is designed which can achieve 0.0068° phase detection precision. Furthermore, the designed system does not need to rely on other instruments to realize the signal generation and demodulation, which makes the MIT system independent and portable in the practical application. The sensing coils have high consistency, and the signal-to-noise ratio (SNR) of the demodulated signal is over 60 dB. To illustrate the performance of the system, the capability of reconstructing low-conductivity saline solutions is studied. The images of conductivity distribution are obtained using the Tikhonov regularization method. The minimum detectable volume of saline solution is 10 mL, with a spatial resolution of 16.6%. The minimum detectable conductivity is 0.1 S/m, and the maximum detectable depth is 40 mm. The reconstructed results indicate the feasibility of low-conductivity medium imaging in the industrial and biomedical applications by the proposed MIT system.

Conventional sub-sampling PLLs suffer from unstable problems under external interference due to potential long relock time in some cases. To solve this issue, a novel quadrature sub-sampling phase detector (QSSPD) is proposed in this brief to eliminate phase error ambiguity and compensate gain non-linearity. Hence, relock time under external interference is dramatically reduced while maintaining the low in-band noise characteristics simultaneously. Moreover, a study on the dynamics of sub-sampling PLL is carried out based on dynamic equations of the sub-sampling loop. A 2.3-2.5 GHz integer-N SSPLL has been prototyped in a 65nm CMOS process to show the superiority of the proposed QSSPD, which reduces the relock time from $16.3{\mu }{s}$ to $4.8{\mu }{s}$ and even $1.1{\mu }{s}$ compared to conventional SSPD while suffering 5.4MHz frequency interference.

Linear Kalman-filter-based phase-locked loop (LKF-PLL) has been widely applied in grid synchronization and other power system fields. It receives considerable attention for its fast startup transient which is superior to the traditional PLL. However, when the KF reaches its steady state, the Kalman gains will converge to constant values, which makes it degrade into the traditional synchronous reference frame phase-locked loop. The main aim of this article is to analyze the steady state of LKF-PLL and make a good use of its adaptive process. Based on the analysis, a design guideline of the LKF is introduced, which can help tune the Kalman gains separately to meet the engineering requirements. Besides, to enhance the dynamic performance under phase jump condition, a dynamic tracking algorithm-based LKF is proposed in this article. Comparative tests about phase detection in power system are conducted, and the results show that the proposed algorithm can greatly improve the dynamic response under phase jump condition without degrading its steady-state performance inherited by the traditional PLL.