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Reference point of applicability (RPA) is a predefined point in a distribution network that determines performance requirements for multi- distributed energy resource (DER) circuits compliant to international grid codes. As RPA response is often not directly controlled, it requires an aggregate response of multiple DER, which becomes a challenge in complex meshed network environment. This paper presents a multiagent-based distributed dynamic voltage support (DDVS) method for coordinated aggregate response of multiple DER units to support RPA voltage profile during and after fault-ride though in such networks. DDVS implements a multiagent based leader target tracking scheme with velocity matching and flock centering features to avoid uncoordinated current injections of cooperative DERs. The DDVS is an event-based approach based on the RPA requirements. Two-dimensional voltage support objective is handled: (i) coordinated positive sequence current injection for voltage magnitude boosting and (ii) coordinated negative sequence current injection for unbalance voltage mitigation. The results demonstrate that the proposed DDVS algorithm addresses emerging coordinated DVS requirement of DERs.

This paper outlines a novel approach for simulating general nonlinear circuits in the time-domain. The proposed approach can be considered as the generalization of the numerical inversion Laplace transform (NILT) which has been used for circuits with only linear elements. The new approach enables the well-known advantages of NILT such the guaranteed numerical stability and the high-order approximation, to be carried to the domain of nonlinear circuit. A numerical example is given to demonstrate the validity of the proposed method.

In vivo electronic monitoring systems for underwater applications are promising technologies for obtaining information about aquatic animals. State-of-the-art devices are constrained by limits on the number of integrated sensors, large dimensions and weight, and short device longevity. Here, we report the Labon-a-Fish: the world's first biotelemetry tag that combines edge computing with wireless sensing of in vivo physiology [electrocardiogram (ECG) and electromyogram (EMG)], behavior [activity level and tail beat frequency (TBF)], and ambient environment (temperature, pressure, and magnetic field). The Lab-on-a-Fish has a miniaturized form (dry weight: 2.4 g; wet weight: 0.8 g; and dimensions: 5.5 mm x 6.5 mm x 37 mm) for studying small animals. Engineering efforts spanning improvements in battery chemistry, electronic circuit efficiency, and power-saving algorithms extend the longevity of the device to as much as eight months. The designed piezoelectric transducer and its driving circuit enable underwater wireless communication of multiplexed digital sensor data over a distance up to 400 m. The Lab-on-a-Fish can also store the raw data using flash memory for use in locations that are challenging for acoustic communications or when more complex data postprocessing is needed. Long-term in vivo validation in three species-rainbow trout (Oncorhynchus mykiss), white sturgeon (Acipenser transmontanus), and walleye (Sander vitreus)-demonstrated the device's sensing potential for biological and environmental applications. DOE [DE-AC05-76RL01830] Published version This work was conducted at Pacific Northwest National Laboratory (PNNL), which is operated by Battelle for DOE under Contract DE-AC05-76RL01830. Fish care and use for the study were approved by Pacific Northwest National Laboratory's Institutional Animal Care and Use Committee (protocol No. 2019-02) following the 8th Edition Guide for the Care and Use of Laboratory Animals (NRC 2011). The authors acknowledge M. Myjak and R. Lundy for the PCB layout, A. Dao for the ECG algorithm, and R. Elsinghorst and A. Salalila for the manufacturing.

The paper presents a new approach to automate the set-up of the design equations of the manual analog design process. Its main contribution is a comprehensive hierarchical performance equation library (HPEL) for op-amps. The HPEL makes the set-up of design equations independent of the topology. Based on the library and the functional block recognition method in [1], analytical performance models for various op-amp topologies are automatically instantiated. The method is currently designed for basic op-amps. In this paper, we use the method to size different op-amp topologies. Experimental results featuring four circuits are presented. The HPEL has also been integrated into a structural synthesis method featuring several thousand op-amp topologies [2]., (C) 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information. This is the author's version which has not been fully edit. Content may change prior to final publication. Citation information: DOI

Owing to its fast transient response, the V2 control technique for switching converters has wide potential application prospects. In this paper, we present a digital V2 controller integrated circuit (IC) for DC-DC switching converters to improve the transient response. The controller IC consists of two compensators and some ancillary circuits, specifically a proportion-integral-differential (PID) compensator and a predictive control compensator, as well as an analog-to-digital converter (ADC) and a digital pulse width modulator (DPWM). The PID compensator is designed based on the delta operator instead of the conventional shift operator, which can improve the stability of the converter and reduce hardware costs. The predictive control compensator uses an improved average predictive control strategy to enhance the transient response. A 6-bit delay-line window ADC with a differential bias circuit is proposed to improve the ADC linearity. An 11-bit hybrid DPWM, which consists of a counter and a segmented delay line with a delay-locked loop, is proposed to relieve the conflict between the die area and DPWM linearity. A prototype of the digital V2 controller IC was fabricated using the 180-nm CMOS process, which was applied to a buck DC-DC switching converter to verify its performance. The experimental results show that an excellent transient response was achieved.

High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

This article develops an equivalent circuit-based model to perform power and emission tracing in power grids. By relying on the proposed model, a power network can be readily converted into a series of equivalent acyclic circuits so that the contributions of generators to a specific load can be clearly and unequivocally traced from a circuit point of view without making any assumptions on how nodal power inflows contribute to the outflows. The effectiveness of the proposed method is discussed through both power flow and optimal power flow simulations on three case studies, including a simple two-generator network, and the IEEE standard 14-bus and 118-bus systems. Furthermore, the proposed power flow tracing method is used in estimating the electricity-associated emissions from the customer side.

This paper proposes a method for generating RSFQ logic circuits utilizing special RSFQ gates in logic synthesis. It is suited for the standard technology mapping flow used in logic synthesis tools and enables generating RSFQ circuits utilizing confluence buffers (CBs) and resettable DFFs (RDFFs), to reduce the number of clocked gates by reduction of logic depth. A library of supergates, each consisting of several gates, is used to compose a resultant circuit in the technology mapping. In this paper, a library containing supergates including those special gates is generated and is utilized to design circuits with the gates. First, a generation of a supergate library is proposed to introduce CBs and RDFFs, which realize logic OR without clock pulses and a fused function of logic AND and NOT, respectively. The generated library contains supergates including the special gates and they are used to compose the resultant circuits with the special gates. A mapping approach is also proposed. It distinguishes non-clocked gates such as CBs and clocked gates. It takes the number of inserted DFFs for path balancing into account to reduce the number of clocked gates. The method was implemented into the state-of-the-art academic EDA tool, i.e., ABC, and was evaluated. Evaluation results show that the number of clocked gates is reduced by about 30% from the original ABC with path-balancing DFFs.

There is a clear trend in the aircraft industry to use more electrical systems in propulsion and electromechanical and electrohydraulic actuators to comply with environmental sustainability and to improve reliability and maintenance processes. The increase of electrical consumption requires an increase of the rated voltages to supply power to these so called More Electrical Aircraft (MEA). Unfortunately, this voltage rise, currently up to 540 Vdc, can lead to ionization processes within the electric wiring due to the lower air density at high altitudes. As a consequence, a degraded insulation can create extremely hazardous events in flight such as arcs between wires (serial) or between wires and fuselage (parallel). Serial arcs in DC bus circuits are specially dangerous for the aircraft operation, so its detection within fractions of seconds is required to ensure a reliable operation. However, during a sustained serial arc the rated current can be passing through air deceiving the protections and avoiding their tripping. In this work, it has been found that arcing introduces high frequency current pulses superimposed to the DC component that can be identified to detect the occurrence of an arc. The frequency components of these pulses depend on the line characteristics and can be detected with inductive sensors. This manuscript also designs and tests a light and inexpensive sensor for arc detection in aircraft applications.

The snappy reverse recovery (SRR) and failure of high-voltage non-punch-through (NPT)-PIN diodes under extreme working conditions is of great significance to the reliability evaluation of operating diodes in actual power electronic devices. In this paper, the analysis of the physical mechanism of the diode SRR and the restrictions of the traditional PT-PIN diode model are made. Then, the traditional model for soft recovery is improved in order to accurately describe the diode SRR characteristics. Simulations of key dynamic performances of the established model agree well with the testing results. Furthermore, a suppression method for diode SRR based on the optimal RC snubber circuit is proposed. A high-voltage NPT-PIN diode used in the DC-DC converter with different RC snubber circuits is simulated using the proposed diode snappy model and tested. The comparison results show good consistency between the simulated and measured voltage and current peaks and the diode SRR can be suppressed effectively. The model developed and the results are of much importance to the prediction of the safe operation area of the diode and to the reliability improvement of power electronic device.

This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm² and consumes 15.9 μ W, resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

The Stretched-FrOnt-Leg (SFOL) pulse is a high-accuracy distance measuring equipment (DME) pulse developed to support alternative positioning and navigation for aircraft during global navigation satellite system outages. To facilitate the use of the SFOL pulse, it is best to use legacy DMEs that are already deployed to transmit the SFOL pulse, rather than the current Gaussian pulse, through software changes only. When attempting to transmit the SFOL pulse in legacy DMEs, the greatest challenge is the pulse shape distortion caused by the pulse-shaping circuits and power amplifiers in the transmission unit such that the original SFOL pulse shape is no longer preserved. This letter proposes an inverse-learning-based DME digital predistortion method and presents successfully transmitted SFOL pulses from a testbed based on a commercial legacy DME that was designed to transmit Gaussian pulses., Submitted to IEEE Transactions on Aerospace and Electronic Systems

Josephson junctions (JJs) with non-hysteretic I-V characteristic and high critical parameters are required for many applications; in particular, they are needed to create tunable THz range oscillators. We fabricated and studied shunted superconductor-insulator-superconductor (SIS) Nb-AlOx-Nb tunnel junctions with an area of about 1m2, estimated their parameters, and compared them with theoretical models. To assess the performance of shunted junctions in the terahertz range, their characteristics were studied under the influence of a high-frequency signal; the estimated value of the characteristic voltage for the shunted junction at a high frequency is about 1 mV. To improve the circuit parameters, a new type of the shunting based on application of NIS junctions was proposed, which reduces the influence of parasitic inductance, expands the frequency range of the generator, and decreases the size of the structure. The JJs with a new type of shunting have been fabricated and studied. The niobium integrated circuits intended for matching the superconducting oscillator and an SIS junction as a microwave detector were designed, fabricated, and tested. Such structures are required for studying the spectral characteristics and analyzing the operation of the oscillator. The developed circuits have demonstrated efficient operation at frequencies from 300 to 700 GHz; the experimental results are in good agreement with the simulated characteristics. The results obtained will be implemented for further development of the THz range oscillators.

High-frequency electromagnetic linear machine is one major component for linear eletro-hydraulic actuator that in turn is extrimely important for the flight control of more-electrical or all-electrical aircrafts. The employment of high-frequency linear machine helps to achieve high reliability and dynamic performance of the actuators. However, the capability of heat dissipation of the linear machine unavoidably constrains the input current, which in turn depresses its output performance. Therefore, this paper proposes a novel electromagnetic linear machine based on the self-powered direct oil-cooling windings. Specifically, the windings are immersed into the oil directly, which helps to decrease the temperature of the linear machine significantly and thus increase its output performance. In addition, the oil is pushed by the motion of the mover itself. No additional pump is required. The design concept of high-frequency electromagnetic linear machine along with its operating principle is presented. A high-precision three-dimensional (3D) piecewise modeling method is proposed to simultaneously consider axial, radial and circumferential equivalent thermal circuits. Numerical simulation is conduced to validated the analytical model. A research prototype of the machine based on direct oil-cooling windings is developed and empolyed for experimental study, and the experimental result verifies the mathematical model of the thermal field well.

Inductive power transfer (IPT) systems are appropriate for electric vehicles charging applications because of the advantages of safety and convenience. However, due to the considerable influence of pad misalignment, improving misalignment tolerance is important for IPT systems. Besides, constant current (CC) and constant voltage (CV) output characteristics are usually required for electric vehicles battery charging. Therefore, to fulfill both features, a hybrid IPT system implementing high misalignment tolerance with inherent CC-CV output is proposed for electric vehicles charging applications in this paper. Two coils connected reversely in series are applied in transmitter side while two coils respectively compensated by a capacitor and an inductor-capacitor-capacitor are applied in receiver side. Hence, without extra DC-DC converter or complicated control strategy and corresponding circuits, CC-CV output can be naturally achieved with high misalignment tolerance which obviously increase the system reliability. Besides, zero-voltage switching and zero phase angle condition can be easily achieved. A 1kW experimental prototype is built. The experimental results show that the fluctuations of the constant charging current and the constant charging voltage are less than 5% when the proposed system operates within the predetermined misalignment range.

Harnessing energy from the environment promotes the rapid development of micro-power generators and relevant power management modules of alternating current (AC) line-filtering to obtain a stabilized direct current (DC) output for storage and use. Micro-supercapacitors (MSCs) with miniaturized volume and high-frequency response are regarded as a critical component in filtering circuits for microscale power conversion. Here, we reported the fabrication of the wafer-sized planar MSCs (M-MSCs) based on 2D Ti3C2Tx MXene using a photolithography technique. The M-MSCs exhibited an areal capacitance of 153 μF cm−2 and a frequency characteristic (f0) of 5.6 kHz in aqueous electrolyte. Moreover, by employing suitable ionic liquid as electrolyte, the voltage window was expanded to 2 V and the f0 could be pushed to 6.6 kHz relying on the electrical double-layer mechanism and lower adsorption energy while maintaining quasi-rectangular cyclic voltammogram curves at 5000 V s−1. Furthermore, the integrated MSCs pack was constructed and exhibited excellent rectifying ability by filtering various high-frequency 5000 Hz AC signals with different waveforms into stable DC outputs. Such ultrahigh-rate and high-voltage M-MSCs module for kHz AC line-filtering would be potentially integrated with customizable electronics to realize on-chip rectifiers in high-density integrated circuit.

Power Supply Noise (PSN) in CPU cores or any integrated circuit (IC) chips is a problem of power line voltage degradation impelled due to the parasitic components (viz., resistance, capacitance and inductance) across the packaging. This lowers the operating frequency of the silicon chip during high volume manufacturing and thereby affects the overall performance. After numerous attempts to minimize the parasitic impacts of power delivery networks (PDN) in IC packages, researchers also started to look for circuital configurations that can curb down the coefficients of PSN (i.e., the instantaneous current i(t) and the current ramp di(t)dt during OFF to ON switching of packaged CPU/IC). Though variable frequency clock (VFC) has emerged as a potential solution, its design is found to be complex and power hungry. Hence, a novel and simple configuration of VFC embedded with leakage control transistor based clock gating (LCT-CG) is tendered in this article, where the pertaining circuits and integrated system have been designed using UMC 65nm CMOS with a supply of 1.1V. The performance of the design is tested on Master-Slave Flip-Flop (MSFF) and a few prominent benchmark circuits (viz., ISCAS’89 s27, s820, s832, s1196, s9234 and ITC’99 b02 and an IEEE 754 complaint single precision FPU) considering the PDN of existing CPU OLGA package. The system level validation of our proposed IC on A-Z80 CPU chip offers the average power and PSN to be mitigated by 30.06% and 42.63% against the conventional clocking.

Powerful electronic design automation tools have enabled the rapid development of electronic Integrated Circuits (ICs). Similar to electronic ICs, silicon photonics technology has sufficiently matured, and large-scale photonic circuits can now be implanted into a single chip. Design tools have also evolved from primary devices to complex photonic circuits. In this paper, we review the current state of photonic design automation in terms of device modeling methods and circuit simulation methodologies, and compare the photonics design flow with mature electronic design automation design flows. Key challenges and opportunities are also discussed.

Doppler ultrasound techniques are currently employed in several industrial, consumer, and biomedical applications. They are implemented in electronic systems of different complexity: from simple low-cost embedded boards to high-end echographs. The development, implementation, and periodic verification of such systems involve complex tests carried out through flow-rigs and phantoms. Unfortunately, these hydraulic circuits are affected by several issues, like the huge dimensions and the lack of an accurate reference for the velocity distribution developed by the fluid. In this work we present an innovative Flow Emulator Board (FEB). The FEB is compact and does not need moving fluids or pumps. Moreover, it produces a signal that mimics a programmable velocity profile with known characteristics. The FEB can replace the flow-rigs in most of the tests where Pulsed Wave Doppler (PWD) methods and PWD electronics systems are involved. The presented experiments show that the proposed FEB synthetizes arbitrary flow velocity profiles with programmable clutter, white noise, propagation attenuation, and sample volume extension; and show how FEB is employed for testing an industrial sensor and a research echograph.

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance. In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.

A very high-light-load-efficiency, low-ripple-voltage pulse-frequency modulation (PFM) buck converter for IoT applications is presented in this paper. The PFM buck converter is widely used because of its higher light-load efficiency. However, it has a higher ripple voltage than its pulse-width modulation counterpart. Although the ripple voltage of a PFM buck converter can be reduced by increasing the output capacitance, we find that this leads to a decrease in the light-load efficiency due to increased controller loss. This problem is analyzed and verified by IC measurements in this work. The proposed PFM buck converter remarkably reduces the controller loss even at low ripple voltages by replacing the static comparator with a dynamic comparator, which provides a high voltage gain, fast evaluation speed, and low power consumption. In addition, to further reduce the controller loss, a dynamic shut-down control method, which selectively turns off control circuits, is used. The proposed PFM buck converter was fabricated with 0.35 m CMOS technology. The magnitude and variation of the output ripple voltage are 3 and 2 mV, respectively, and the light-load and peak efficiencies are 81.1% and 94.8%, respectively.

The Hidden Weighted Bit function plays an important role in the study of classical models of computation. A common belief is that this function is exponentially hard for the implementation by reversible ancilla-free circuits, even though introducing a small number of ancillae allows a very efficient implementation. In this paper, we refute the exponential hardness conjecture by developing a polynomial-size reversible ancilla-free circuit computing the Hidden Weighted Bit function. Our circuit has size $O(n^{6.42})$, where $n$ is the number of input bits. We also show that the Hidden Weighted Bit function can be computed by a quantum ancilla-free circuit of size $O(n^2)$. The technical tools employed come from a combination of Theoretical Computer Science (Barrington's theorem) and Physics (simulation of fermionic Hamiltonians) techniques., 20 pages, 4 figures

This paper proposes an efficient thermoelectric temperature control system based on an improved proportional integral differential algorithm in which energy feedback technology is used to enhance thermoelectric cooling. In the proposed power management system, two groups of batteries are efficiently and alternatingly charged and discharged such that the information of the circuit can be monitored in real time. The PID algorithm is improved by using the idea of a state machine to control the thermoelectric coolers through an H-bridge circuit with pulse-width modulation. Finally, the energy feedback circuit combined with improved synchronous switching technology is designed to recycle the energy to drive the sensor. By inputting current of 3.1A, a wide range of temperature control from 1.437 to 60.187 was implemented. While targeting a temperature of 10 at an ambient temperature of 22, the proposed temperature control system had a control time of 30.5s, compared with 287s when using the conventional method, with an accuracy of 0.1, and an error of only 0.35. The results confirm that electric energy at a peak voltage of 1.2V and current of 24A can be recovered. The proposed energy feedback system can thus improve the efficiency of energy utilization of TEC from peripheral circuits.

As the safety-critical applications (e.g. automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects four benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions.

Neurophysiological observations confirm that the brain not only is able to detect the impaired synapses (in brain damage) but also it is relatively capable of repairing faulty synapses. It has been shown that retrograde signaling by astrocytes leads to the modulation of synaptic transmission and thus bidirectional collaboration of astrocyte with nearby neurons is an important aspect of self-repairing mechanism. Specifically, the retrograde signaling via astrocyte can increase the transmission probability of the healthy synapses linked to the neuron. Motivated by these findings, in the present research, a CMOS neuromorphic circuit with self-repairing capabilities is proposed based on astrocyte signaling. In this way, the computational model of self-repairing process is hired as a basis for designing a novel analog integrated circuit in the 180-nm CMOS technology. It is illustrated that the proposed analog circuit is able to successfully recompense the damaged synapses by appropriately modifying the voltage signals of the remaining healthy synapses in the wide range of frequency. The proposed circuit occupies 7500- [Formula: see text] silicon area and its power consumption is about [Formula: see text]. This neuromorphic fault-tolerant circuit can be considered as a key candidate for future silicon neuronal systems and implementation of neurorobotic and neuro-inspired circuits.

To fully take the high-frequency advantage of gallium nitride (GaN) devices, this article presents a face-up integrated power module based on the printed circuit board (PCB) embedding technology to tackle the challenges caused by conventional discrete solutions. The proposed GaN module highly integrates a GaN-bare-dies-based full bridge, driving circuits, and decoupling capacitors, in which the advanced bismaleimide-triazine (BT) material is used as the packaging material and the copper-filled laser microvias are used for low-parasitic-inductance and high-thermal-conductivity interconnection. Careful electro-thermal co-design and optimization of power loop is conducted to make the trade-off between power loop inductance and thermal performance. The proposed full bridge power module achieves the lowest power loop inductance of about 0.305 nH in power modules with the same power level. The maximum thermal resistances from the embedded GaN bare dies to top and bottom surface are 3.39 /W and 0.42 /W, respectively. Benefitting from the ultra-low power loop parasitic inductances, the switching speed of GaN devices reaches to 57.5 V/ns, while the voltage overshoot is not higher than 5.35% of the DC bus voltage. The superior performance of the proposed integrated GaN module makes it a promising application prospect in high frequency high power density converters.

This paper proposes and implements a novel wireless power and drive transfer (WPDT) system using orthogonal bipolar couplers and separately excited modulation (SEM). Specifically, two bipolar coils are orthogonally integrated and naturally decoupled to form a compact magnetic coupler which will be utilized in the transmitter and receiver, respectively. The key is to employ the SEM to alternatively energize bipolar coils in the transmitter while self-driven circuits in the receiver can directly extract the drive information to control receiver-side switches. Consequently, the concurrent wireless power transfer (WPT) and wireless drive transfer (WDT) can be skillfully realized via the shared transfer channel at the single resonant frequency. Moreover, the proposed system can effortlessly achieve the wireless DC motor drive with the capability of bidirectional motion, or the wireless AC motor drive with the variable-voltage variable-frequency (VVVF) control. Besides driving the DC and AC motors, a 200-W prototype is constructed with the transmission efficiency of 89.5 % over the transfer distance of 100 mm for a resistive load of 40 . Both theoretical and experimental results are provided to validate the feasibility and flexibility of the proposed system.

Through Silicon Via (TSV) is considered as the near-future solution to realize low-power and high-performance 3D-Integrated Circuits (3D-ICs) and 3D-Network-on-Chips (3D-NoCs). However, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault-rate, is one of the most critical challenges. Meanwhile, most current works focus on detecting and correcting TSV defects after manufacturing without considering high-temperature nodes’ impact on lifetime reliability. Besides, the recovery for defective clusters is also challenging because of costly redundancies. In this work, we present HotCluster: a hotspot-aware self-correction platform for clustering defects in 3D-NoCs to help understand and tackle this problem. We first give a method to predict normalized fault rates and place redundant TSV groups according to each region’s fault rate. In our particular medium fault-rate (normalized to the coolest area), HotCluster reduces about 60% of the redundancies in comparison to the uniformly distributed redundancies while having a higher ratio of router working in a normal state. Furthermore, HotCluster integrates both online (weight-based) and offline (max-flow min-cut offline method) mapping algorithms to help the system correct the faulty TSV clusters. The experimental results show that both the max-flow min-cut offline method and weight-based online mode with a redundancy of 0.25 exhibits less than 1% of routers disabled under 50% defect-rates.

This paper introduces a new mathematical procedure for the calculation of power cable ampacities in the case of water-cooled circuits. Both, internal and external cooling installations are considered. The algorithm permits a non-iterative calculation of the water temperature along the cooling length of the cables, evaluation of the heat absorbed and emitted by the cooling pipes as well as the effect of the water flow on the cable conductor temperature. Numerical examples show the effect of the direct and the indirect cooling on the ampacity of a 230 kV XLPE cable circuit.

It is known that rapid single-flux-quantum (RSFQ) circuit technology and its energy-efficient derivatives are considered as one promising technology in superconducting digital applications. In this paper, given the placement result of a multiple-stage pipelined architecture with n gate columns and m gate components in an RSFQ circuit inside a rectangular layout, it is assumed that signals can be propagated from the primary inputs on the left boundary to the primary outputs on the right boundary. Firstly, a lower bound on the routed width of one PTL region can be defined as the estimated width of one PTL region. Furthermore, the sum of the estimated widths of all the PTL regions in an RSFQ circuit can be defined as the estimated region width in an RSFQ circuit and the estimated width can be used as the objective function for the design of the clock distribution in an RSFQ circuit. Based on the flexibility of using the clock splitters (SPLs) inside the gate components for the propagation of clock signals, an iterative assignment algorithm can be proposed to complete the assignment of the tree-based clock connections with minimizing the estimated width of an RSFQ circuit. From viewpoint of numerical experiments, the experimental results show that the reduction of the estimated region width can lead to the reduction of the final width of the PTL regions in an RSFQ circuit. Compared with the design of Kito’s tree-based clock distribution for 5 tested RSFQ circuits, the experimental results show that the design of our proposed tree-based clock distribution with two capability parameters, 2 and 3, on a clock SPL can use reasonable CPU time to reduce 47.03% and 54.33% of the estimated region width and 44.83% and 45.25% of the final width for 5 tested RSFQ circuits on the average, respectively.

In this article, a novel 13-level inverter Single source, Switched-Capacitor Multi-Level Inverter (SSC-MLI), is proposed. This topology is suitable for renewable energy applications using less input voltage source magnitude. This structure is capable of boosting the input voltage six times with the help of switched capacitors. The capacitors are automatically balanced without any control algorithms, complex circuits, or closed-loop controllers. The advantages of the proposed structure are high power density and high efficiency by use of only switches. Since, there is no diodes there is no forward conduction loss, and no reverse recovery delay. The maximum blocking voltage across individual switch is three times the input voltage. The functionality of the SSC-MLI is described in detail. The capacitance calculation and optimum value of capacitors are discussed. A suitable comparison is presented for the proposed structure with the existing literature to check the inverter performance. The power loss for exiting a 13-level inverter is presented. The simulation is carried out for both pure resistive and inductive load. Later, the experimental results are presented for variation in frequency, dynamic change in load, variation in modulation index, and step-change in input voltage to validate the proposed topology performance and feasibility.

LLC half-bridge converters have been extensively studied in low power industrial applications. However, the phase shift angle between the voltage and current of the LLC resonant network makes the converter have power circulation, that is, backflow power. The increase of the backflow power will increase the converter conduction loss, which restricts the improvement of the converter efficiency. The existing literature often improves the backflow power from the control aspect, which greatly increases the control complexity. To solve this problem, this paper proposes an LLC half-bridge resonant converter analysis method that takes the backflow power into account. Based on the analysis of operating mode and AC equivalent model of the converter, backflow power is indirectly characterized by the phase-shift angle of the resonant network voltage and current. Based on this, this paper analyzes the internal relationship between resonant parameters and backflow power to reduce backflow power by optimizing resonant parameters. Under the setting operating conditions, converter can achieve ZVS switching, voltage gain conditions and minimum backflow power. Compared with the existing methods, the proposed optimization method avoids additional auxiliary circuits and control complexity, improves the stability of the circuit. Experimental results verify the accuracy and feasibility of the theoretical analysis.

In this paper, we present the investigation and design of high-performance transitions from coplanar waveguide (CPW) to the single-conductor, corrugated waveguides, namely terahertz spoof Surface Plasmon Polariton Waveguides (SSPP WGs). In contrast with the previous studies in the literature on the CPW to SSPP WG transitions, we propose a novel methodology to examine the relationship between the guided wavenumber and momentum matching, which is based on analytical calculations, together with the effects of the flaring grounds on the transition performance. This novel methodology allows us to design a low-loss transition circuit for any given CPW and SSPP dimensions, which is demonstrated for the first time in the literature. We verify the proposed methodology by the design, fabrication, and measurement of several transition circuits. The measurement results show that the insertion losses of the proposed transition circuits can be as low as -1.2, -1, and -2.4 dB at 0.25, 0.275, and 0.3 THz, respectively, which brings a significant improvement of 0.6 to 2.3 dB in 0.25-0.3 THz band, compared to the previously reported studies in the literature for the terahertz band.

In this article, we explore the design of energy-efficient intermittently powered systems (IPSs) using reconfigurable-ferroelectric transistors (R-FEFETs). Utilizing the dynamic tunability between volatile and nonvolatile modes of operation in R-FEFETs, we design nonvolatile flip-flops (NVFFs) and memory (NVM) suitable for IPS. We present two variants of R-FEFET-based NVFFs (RNVFFs): 1) with automatic backup and 2) with need-based backup. While the former offers high backup energy efficiency, the latter offers low normal operation energy. We also present an IPS-specific R-FEFET-based NVM (3T-R) with high energy efficiency compared with FEFET-based 2T NVM. Leveraging these nonvolatile circuits, we map the microcontroller unit (MCU) core registers of an IPS to RNVFFs and its on-chip memory to 3T-R. Subsequently, we analyze system-level implications of improving NVFFs and NVM individually by using R-FEFETs compared with existing FEFET-based designs. Our system-level simulations demonstrate that although we improve the register energy by 55%-67%, the total memory and system-level energy savings obtained from just improving the NVFFs (registers) in the microcontroller core are only 0.60%-5.78% and 0.31%-3.18%, respectively. However, improving the NVM by using 3T-R results in a much larger total memory and system-level energy savings in the range of 37%-40% and 20%-22%, respectively, in the context of a state-of-the-art IPS.

An quasi-online equivalent series resistance (ESR) identification method that considers the impact of capacitance based on variational mode decomposition (VMD) of forward converters is proposed in this paper. Firstly, the capacitance impact is included in ESR derivation. Subsequently, VMD is adopted to process characteristic signals for harmonic analysis, filter out noise and simplify circuits design. The experiments and simulation are employed to verify the proposed method. In addition, in order to overcome the disadvantages of using ideal capacitors in traditional simulation, fractional-order capacitors are constructed to describe the non-ideal characteristics of the capacitor. Meanwhile, the identification result is compared with the LCR meter measurement. Thus, the superiority of the proposed ESR quasi-online identification method and the construction method of fractional-order capacitors are confirmed through comparative analysis.

Series-connected multi-pulse rectifiers (MPRs) are used to provide high quality electric power for high-voltage and high-power occasions. Due to conventional MPRs have limited harmonic reduction ability that cannot fulfill the related harmonic standard, some effective DC side harmonic reduction methods have been proposed to further improve power quality of the MPRs. This paper gives a comprehensive review on DC link harmonic reduction methods of series-connected MPRs. Passive and active harmonic reduction mechanisms are respectively analyzed based on two typical topologies, which are theoretical foundations for understanding and constructing novel harmonic reduction circuits (HRCs). Some useful DC side HRCs are presented and compared from aspects of their performances, complexity of overall structure, magnetic device capacity and power losses, etc. The necessary simulation results are given to verify and compare the effectiveness of some involved harmonic reduction methods. Based on these topologies, the advantages, drawbacks and future trends of the passive or active methods are concluded; besides, the hybrid harmonic reduction methods are also considered. This article aims to provide useful guidance for the researches of harmonic elimination and multi-pulse rectification technology.

With the development of artificial intelligence research, the convolutional neural networks (CNN) triumphantly continue to conquer diverse visual tasks, with lots of technical and practical problems emerging. When the detection networks need to meet the high-speed processing requirement and the low power consumption constraint in edge computing, dedicated circuits and algorithm optimization are necessary. In this brief, we propose a non-maximum suppression (NMS) coprocessor that cooperated with a Vision Processor(VP) to speed up the detection. It contains a parallel process unit and dynamic memory management to accelerate NMS processing. Meanwhile, the software workflow provides a comprehensive method to convert the one-stage detection network to our processor in a post-training manner. The experimental results show that our co-design solution reaches 166 FPS to run a MobileNet-SSD, promising to deploy in edge-computing scenarios. Moreover, the detection accuracy on the Airbus dataset is 88.6%, favorable in practical applications.

This paper investigates the intelligent fault detection problem for a class of Takagi-Sugeno fuzzy Markov jump systems. The considered systems are modeled by a set of fuzzy rules and membership functions. With the help of deep learning technique, an intelligent fault detection method based on long short-term memory (LSTM) neural network with an attention mechanism is proposed. The improved LSTM model can accurately capture the fault features by making full use of previous information. Finally, the proposed approach is applied to the tunnel diode circuits and corresponding experiments are conducted to demonstrate its effectiveness, which achieves better performance in comparison with other conventional method for detection.