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Monte Carlo technique is applied to simulate the synchronization between neighboring kinetic oscillators of nanoscaled supported platinum particles. Non-isothermal kinetics caused by local overheating provides an extra thermal conduction channel for synchronization between oscillators. Kinetic oscillation is produced when fast carbon monoxide oxidation is accompanied with slow subsurface oxygen formation and removal. Different effects are investigated on synchronization, including thermal conduction efficiency, heat dissipation efficiency, and distance between the two oscillators. Decreasing thermal conduction efficiency isolates each kinetically oscillating catalyst and results in complicated oscillation patterns. Heat dissipation has the opposite influence on synchronization comparing to thermal conduction. Low heat dissipation from the substrate to the environment maintains the temperature of the system and thus promotes synchronization. In addition, synchronization is destroyed when the distance between two oscillating particles becomes several-fold longer than the platinum particle size.

Efficient fluorescent blue, green, and red (RGB) organic light-emitting devices (OLEDs) were fabricated using a blue host material of pyrimidine-containing spirobifluorene derivative 2,7-bis[2-(4-tert-butylphenyl)pyrimidine-5-yl]-9,9′-spirobifluorene (TBPSF) doped with blue dye perylene, green dye 10-(2-benzothiazolyl)-1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-benzo[l] pyrano[6,7,8-ij] quinolizin-11-one (C545T), and red dye 4-(dicyanomethylene)-2-t-butyl-6-(1,1,7,7-tetramethyljulolidyl-9-enyl)-4H-pyran (DCJTB), respectively. The brightness and current efficiency of the perylene doped blue device reached 10117 cd/m2 and 2.97 cd/A. Green emission of the C545T doped device reached 8500 cd/m2 and 13.0 cd/A. Red emission of the DCJTB doped device can be as high as 9000 cd/m2 and 2.0 cd/A, respectively. High color purity of the blue (Commission Internationale de L′Eclairage (CIEx,y) coordinates (CIE, x = 0.27, y = 0.24)), green (CIE, x = 0.19, y = 0.63) and red (CIE, x = 0.62, y = 0.37) emissions were achieved for RGB dyes doped TBPSF OLEDs. High brightness, large current efficiency, and good color purity of TBPSF-based RGB OLEDs were obtained by the configuration optimization device, such as inserting the hole and electron-injection materials, and suitable dopant content and light emitting layer thickness.

Theoretical calculation and simulation of FEM were proposed to explain the decline of change in resistance in Cu-Sn microbumps during the electromigration test. The IMC transformation from Cu 6 Sn 5 to Cu 3 Sn was supposed to be the reason. Being aware that the dimension keeps shrinking, the behavior for various solder diameters was also investigated.

In 3D integration, die stacking together with underfilling by capillary-type underfill are the principal processes within whole conventional assembly process. How to integrate and shorten the total process steps during assembly and increase the die-stacking yield especially for thin die stack to improve the throughput that can meet the requirement from industry will be a crucial issue. In this investigation, we proposed the high throughput adhesive bonding scheme by using wafer-level underfill material for the die-to-interposer stacking with 30µm-pitch micro interconnections. The reliability characterization of the die-to-interposer stack by such bonding scheme was implemented and confirmed.

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

A series of AlCrFeCoNiCu High-entropy Alloys added Al-5Ti-B-RE grain refiner were prepared by vacuum arc furnace. The microstructures of the series of as-cast AlCrFeCoNiCu alloys are typical dendrites and are constituted by two kinds of solid solution (αphase andβphase). αphase is body-centered cubic (bcc) structure composed of Al, Cr, Co, Fe, Ni and a few Cu, and βphase is face-centered cubic (fcc) which enriches Cu. With the increase of Al-5Ti-B-RE, the region ofαphase becomes larger. When the content of Al-5Ti-B-RE is 0.4%(wt), the volume ratio values of α phase increases, moreover, α phase and β phase evenly distribute, and either the compressive strength (2.28GPa) or the compressive ratio (20.95%) is maximized. Fan pattern appears in the fracture morphologies of these alloys, and it is cleavage fracture. These alloys belong to brittle materials.

Three kinds of diamond-like carbon (DLC) films, which contain different metals (Ti, Cr, Zr) and different interface designs, were deposited on biomedical titanium alloy (Ti–6Al–4V, ASTM F136) by using a cathodic arc evaporation system. Preliminary results showed that the DLC films are hydrogenated, amorphous and dense in structure. Scratch tests and Rockwell indentation tests reveal that the graded structures can improve the adhesion of DLC films. The Raman analyses showed that the Cr-containing DLC films possess lower I D / I G ratio, lower G-peak positions, and higher coating hardness. The pin-on-disk wear test in different environments (air and simulated body fluid) revealed that all the DLC films improve the wear performance of the substrates, and the wear coefficient is lower in simulated body fluid than that in air. In addition, the Cr-containing DLC films exhibited the lowest friction coefficient of 0.06 in simulated body fluid and 0.16 in air with the counterface of UHMWPE. Because of their dense structure, good adhesion and superior corrosion resistance in SBF, the Cr-C:H/CrN films exhibited significantly low friction in SBF. The ICP-MS analysis revealed the release of Cr ion is 2.22–10.03 ppm from the Cr-contained DLC films, which is less than that from Co–Cr–Mo alloy (106.17 ppm), showing that the Cr-containing DLC films meet the requirement of biomedical applications. The potentiodynamic test revealed that the corrosion resistance of the ASTM F136 titanium alloys is increased substantially by the metal-containing DLC coating.

Saving consumable energy and maintaining the thermal comfort level are two main topics in the heating, ventilating and air conditioning (HVAC) control field. The reliability of the controller is important as well. This paper proposes a least enthalpy estimator (LEE) that combines the definition of thermal comfort level and the theory of enthalpy into a load predicting way to provide timely suitable settings for a fan coil unit (FCU) fuzzy controller used in HVAC. According to the settings, including temperature and relative humidity, the fuzzy controller can make decisions and adjust the output of the FCU system. From actual experiments, the LEE-based FCU fuzzy controller can achieve the requirements of the FCU control system such as thermal comfort, energy efficiency and reliability.

In this paper we introduce Hidden Lion, a Location Based Service(LBS) APP game which is related to sword lion culture in Anping, Taiwan. Sword Lion symbolizes the protector god in Anping. Many local people built sword lions in front their houses because they believed that these stone plated statues will keep evil spirits away. Nowadays these statues decay with time and weather and leave a few in Anping. Recently, with the promotion of Government, many travelers are attracted to come here and find out remaining sword lions and experience local cultural stories. However, sword lion searching has some problems: (1) Sword lions are hard to be found. (2) Sword lion searching may disturb local people. (3) Visitors do not truly realize the cultural story of sword lions. Therefore, we develop Hidden Lion which has a storyline and theme that has a connection with sword lion. In the game, visitors can follow the maps and the precise positions of sword lions to find them easily. What's more, Hidden Lion includes interactive mission games for visitors to play. These games are related to the background story of sword lions. While playing the interactive games at each sword lion site with this APP, visitors can find sword lions and experience the background story of each sword lion. Furthermore, Hidden Lion creates a service system in Anping. From the support from Anping district office, more and more visitors can come here and play the Hidden Lion. After completing all the interactive games, the visitors will receive a coupon of sword lion model coloring from Sword Lion School as a reward, which gradually forms a business cycle and culture connection. These visitors may be encouraged to come to Anping again and again, enhancing cultural and commercial development in Anping.

In this study, we use the Cu/SnAg/Ni/Cu joint with a thickness of 7μm/8μm/2μm /5μm and 7μm/16μm/2μm /5μm. The diameter of the solder joint is about 30 μm and the UBM opening is 18 μm in diameter with 60 μm pitches. In order to measure the resistance changes, it was fabricated which constitute four probes. By using this method we can measure the resistance changes in microbump excluding the resistance changes in the wiring trace to make it more sensitive to subtle microstructure changes. We investigated the mechanisms of electromigration in microbumps with different stages when resistance increased 20%, 50% and 100% of the initial resistance. Solder joints were stressed with 0.56 A on 150°C hot plate. The average current density is 8 × 104 A/cm2, calculated based on the UBM opening. We ground the samples with 1000, 2000, and 4000 sand paper and then polished them with 1 μm, 0.3 μm, and 0.05 μm Al 2 O 3 We observed their morphologies with SEM and measured their component with EDX. In the bump with electron flow upward, we observed that microbumps were transformed into Cu 6 Sn 5 IMCs and Cu 3 Sn IMCs joints. In addition, voids were formed at the interface between nickel and solder. We found that both void formation and UBM dissolution were occurred. In the bump with electron flow downward, microbumps were transformed into IMC joints without void formation. To sum up, this study provides a better understanding on the relationship between the behavior of resistance curve and the morphology changes in microbumps.

In this paper, field coverage generated by antenna locating in rectangular tunnel is studied. Ray tracing method is utilized to simulate the wave propagation in tunnel environment, the correctness of the method is validated by FDTD method and measurement. After verification, the influence of antenna position, beam direction and beam width on the field distribution is analyzed and discussed. The effect mechanism of antenna pattern on the field distribution in tunnel is studied. A hybrid approach which contains ray tracing method and particle swarm optimization (PSO) algorithm is proposed to optimize the antenna radiation pattern, orientation and location in the tunnel environment, the objective is to generate uniform field coverage in the tunnel.

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Three dimensional integration circuits technology has received much attention recently since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are essential. In the current types of interconnects, solder micro bumps have been widely used and thermocompression bonding process are well adopted to form the connection between bumps. However, the prefect joint contour is difficult to obtain and control by such kind of bonding process in solder micro bump joints. For fine-pitch solder micro bump interconnections, the effect of joint shape on the reliability performances of the solder micro bump joints is not concluded yet till now and needs to be clarified. In this study, the effect of joint shape controlled by thermocompression bonding on the reliability performance of solder micro bump interconnections with a pitch of 60 um was discussed. The chip-to-chip test vehicle having more than 4000 solder micro bump interconnections with a bump pitch of 60 um was used in this study. A solder micro bump structure of Cu/SnAg having a thickness of 7 um/10 um was fabricated in both the silicon chip and substrate. To evaluate the effect of joint shape, four types of joint shape were controlled and made. The first type had a conventional shape of micro joint. Compared to the first one joint structure, the second type of joint structure showed the compressed shape. The third type of joint structure was the pillar-like micro joint while the fourth type of joint structure presented a neck shape having the highest joint height among all the joint structures tested. We used the fluxless thermocompression bonding process to form these four types of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of joint shape on the reliability properties of those four types of solder micro bump interconnections. The reliability results presented that all the types of joint structures could pass TCT of 1000 cycles and HTS of 1000 hours but high variation of daisy chain resistance more than 15% would happen in the neck-shape micro joint after TCT. For the neck-shape micro joint, the high variation of daisy chain resistance after TCT resulted from the cracking propagated along the interface of Cu UBM/Cu 6 Sn 5 IMC and across the tin solder. The cracking situation was more serious as compared to the other three tested micro joints. The results of HTS revealed that resistance variation mainly depended on the micro structural evolution within micro joints tested. Electromigration test was conducted under the testing condition of 0.56 A/150°C. A daisy chain structure was adopted. For both the pillar-shape and neck-shape micro joints, Cu UBM consumption and formation of large void were the major microstructure evolutions within the micro interconnections during EM testing. The conpressed-shape showed the longer electromigration lifetime among all the types of micro joints tested.

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500µm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 µm after thinning and the total thickness variation is around 1 µm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.

A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation.

Recently, three dimensional integration circuits technology has received much attention since the demands of functionality and performance in microelectronic packaging for electronic products are rapidly increasing. For high-performance 3D chip stacking, high density interconnections are required. In the current types of interconnects, solder micro bumps have been widely adopted. For fine pitch solder micro bump joints, selections of bump height and UBM structure are the important issues that would show the significant effects on the reliability performances of solder micro bump interconnection. In this study, effects of bump height and UBM structure on the reliability properties of lead-free solder micro interconnections with a pitch of 60µm were discussed. The chip-to-chip test vehicle having more than 4290 solder micro bump interconnections with a bump pitch of 60µm was used in this study. To evaluate the effects of bump height and UBM structure on the reliability performance of micro joints, two groups of solder joint were made. The first group of micro joints had a total bump height of 29µm. In this group, Cu/Sn/Cu joint with a thickness of 7µm/15µm/7um, Cu/Sn/Ni/Cu joint having a thickness of 7µm/15µm/2µm/5µm and Cu/Ni/Sn/Ni/Cu joint with a thickness of 5µm/2µm/15µm/2um/5µm were selected. The second group of micro joints had a total bump height of 24µm. In this group, Cu/Sn/Cu joint having a thickness of 7µm/10µm/7um, Cu/Sn/Ni/Cu joint with a thickness of 7µm/10µm/2µm/5µm and Cu/Ni/Sn/Ni/Cu joint having a thickness of 5µm/2µm/10µm/2um/5µm were chosen. We used the fluxless thermocompression bonding process to form these two groups of micro joints. After bonding process, the chip stack was assembled by capillary-type underfill. Reliability tests of temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were selected to assess the effect of bump height and UBM structure on the reliability properties of those two groups of solder micro bump interconnections.

In this paper, EtherCAT slave module design and implementation based on Cortex-M0 is carried out. This paper designs a slave module with EtherCAT slave controller (ESC) and Cortex-M0 microcontroller. The slave module has eight 16-bits input ports and eight 16-bits output ports. The experimental results show that performance of the slave module can meet the real-time requirements in industrial automation. Combining with other modules, it could satisfy the varieties of control functions needed. It is easy to be made and operated.

Chip embedded technology enables advanced integration of modern electronic package structures due to its characteristics of small size, higher performance, lower overall cost and reduction of time to market. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. Comparing to 3D interconnection by through silicon via (TSV), device embedded module can have relevant effects by using PCB compatible process though the size and transmitting path is slightly higher than 3D IC modules. However, warpage issue is one of the significant factors that affect the manufacturing of device embedded products due to the asymmetric package form. A strong and robust substrate or core layer, such as high Tg FR4 substrate, BT substrate or Cu lead frame, is often required to provide a stiffening effect for the structure to prevent from severe warpage. In order to acquire even thinner package form, finer L/S specifications, and higher density of interconnection, coreless substrate may be one of the solution to meet the demand. But the asymmetric characteristic of embedded package structure may be regarded as a challenge when applied in coreless structure without a core layer. In this paper, a new type dielectric material with the characteristic of low CTE is disclosed. When it was applied in an asymmetric package structure with embedding chip, warpage behavior was found suppressed comparing to conventional dielectric materials. Moreover, when it was applied in a coreless structure with chip embedded, the structure can still maintain considerable flatness. The process feasibility of laser via forming, Cu plating was evaluated, while tensile strength of the plated Cu and reliability of the laminated structure were examined. An additional PI material was coated as the release layer in the forming of the coreless structure. The concept of asymmetric built-up coreless structure was brought up according to the materials' characteristics and regarded as a potential solution for 3D System-in-Package in this study.

Recently, three dimensional integration circuits technology has received much attention because of the demands of gradually increasing functionality and performance in microelectronic packaging for different types of electronic devices. For 3D chip stacking, high density interconnections are required in high-performance electronic products. Though the bumping process used could be either electroplating or electroless plating for fine pitch solder micro bumps, its process effect on the reliability performances of micro joints still needs to be clarified from the microstructural point of view, especially for the fine pitch solder micro bump interconnections. In this study, we discussed the effect of Ni/Au metal finishing fabricated by electro- and electroless plating on the reliability properties of 30μm-pitch lead-free solder micro interconnections. Palladium layer was chosen to evaluate its influence on the reliability response of fine-pitch solder micro joints with electroless Ni/Au surface finishing. The chip-to-chip test vehicle having more than 3000 solder micro bumps with a bump pitch of 30μm was used in this study. Two types of metal finishing, electroplating Ni/Au and electroless plating Ni/Pd/Au, were chosen and fabricated on the silicon carrier. In silicon carrier, the thickness of Ni layer was 2~3 μm while that of electroplating and electroless plating Au layer was 0.5μm and 0.02μm respectively. The thickness of Pd layer within the electroless Ni/Pd/Au structure was 0.05~0.1μm. The silicon chip with a solder micro bump structure of Cu/Ni/SnAg having a thickness of 5μm/3μm/5μm was used for C2C bonding. We adopted the fluxless thermocompression process for both types of micro joints and then the chip stack was assembled by capillary-type underfill. Temperature cycling test (TCT) and electromigration test (EM) were conducted to assess the effect of metal finishing on the reliability properties of those solder micro bump interconnections. The reliability results revealed that the thickness of Au layer would apparently influence the microstructure evolution within the solder micro bump interconnection after bonding process though the micro joints with thick Au layer could pass the 1000 cycles TCT. The micro joints with complicated interface reaction resulted from the thicker Au layer might lead a negative effect on the long-term reliability properties while the Pd layer would enhance the wetting ability of solder micro bump during joining. The results of EM reliability test displayed that both types of the micro joints had excellent electromigration resistance under the testing condition of 0.08A/150°C. The activated IMC growth within the micro joint during EM testing was the major reason for this superior property. This investigated completely presented the effect of metal finishing by electro- and electroless bumping processes on the reliability properties of fine pitch solder micro bump joints.

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

In this study, serveal different density functionals were applied to study the CO adsorption on Pt(111) clusters. When adding more contribution of HF exchange energy, it can be found that the HOMO energy is decreased and LUMO energy is increased, thus increasing the HOMO-LUMO energy gap. The accuracy of S-T excitation energy can also be largely improved when increasing the ratio of HF exchange energy. For CO adsorption at Pt7–3 cluster, most functionals predict that CO favors to adsorb at fcc site. Only when adding more than 40 % HF exchange energy, the M06HF, BMK, wB97 and M06-2X functionals can predict the top-site preference. For CO adsorption at Pt9–9–9 cluster, when adding more than 40 % HF exchange energy, the CO prefers to adsorb at top site than fcc site. Among these functionals, the M06HF strongly predicts the top-site preference. The chemical bonding analysis shows that the effects of σ-repulsion are reduced as the CO S-T excitation energy increasing, and the effect of reduction for CO at top site is more remarkable than that for CO at fcc site. Therefore, CO would more favor to adsorb at top site in those functionals which can give better CO S-T excitation energy. Although the opposite trend can be found for the π-attraction, the overall effect also supports CO favoring to adsorb at top site.

This chapter presents a load balancing method for dual CAN bus to maximize the use of network bandwidth. The CAN (controller area network) is a serial communication protocol gaining widespread acceptance in automotive and automation industry. The network uses dual bus to improve network bandwidth and performance. The data traffic of CAN bus is degraded on high-load conditions. This chapter proposes a load balancing allocation algorithm using fuzzy control to obtain the maximum data traffic. The load balancing allocation algorithm introduced in the chapter is validated on a four-node dual CAN bus system. Each CAN node uses a LPC2119 ARM development board as hardware platform. The chip LPC2119 is based on the ARM7 CPU core with 2 CAN channels. Experiment results show that the fuzzy control is quite suitable for the load balancing control to improve the performance of dual CAN bus at high-load conditions.

The present study evaluated the dementia risk after carbon monoxide poisoning (CO poisoning). Using the National Health Insurance Research Database of Taiwan, a total of 9041 adults newly diagnosed with CO poisoning from 2000 to 2011 were identified as the CO poisoning cohort. Four-fold (N = 36,160) of non-CO poisoning insured people were randomly selected as controls, frequency-matched by age, sex, and hospitalization year. Incidence and hazard ratio (HR) of dementia were measured by the end 2011. The dementia incidence was 1.6-fold higher in the CO exposed cohort than in the non-exposed cohort (15.2 vs 9.76 per 10,000 person-years; n = 62 vs 174) with an adjusted HR of 1.50 (95% CI = 1.11-2.04). The sex- and age-specific hazards were higher in male patients (adjusted HR = 1.74, 95% CI = 1.20-2.54), and those aged

As the demands for high density 3DIC stacking increase, a fine-pitch chip-to-chip interconnects is becoming imperative. In conventional flip-chip technology, anisotropic conductive film (ACF) has been used in place of solder and underfill for chip attachment to substrates in some applications, because it provides many advantages. Generally speaking, ACF consists of an adhesive polymer matrix with randomly dispersed conductive particles, which establish the electrical contacts between the interconnections. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles in the bottom layer of the film was prepared. The 30µm-pitch chip-to-chip (C2C) bonding technology was presented and the chip with 3264 I/Os was bonded onto the substrate using the ACF material. After ACF lamination process, conductive particles capture rate and attach status were calculated and observed from the optical microscope (OM). Therefore, the ACF lamination condition was determined. After bonding process, the effects of bonding pressure and bonding temperature were discussed by considering particle deformation, electrical performance and adhesive flow status. After optimizing the lamination and bonding parameters, the reliability of C2C was evaluated by precondition test (125°C/24hrs backing, 30°C/60%RH/178hrs soaking, and 3times/265°C reflow). Cross-sectioned inspection of ACF joints by Scanning electron microscopy (SEM), the interface between adhesive and silicon observed by Scanning Acoustic Tomography (SAT), and adhesion strength test of ACF film after bonding and precondition were conducted to determine the failure modes. Moreover, after precondition test, the variation of near 70% of the C2C daisy chain resistance was found less than 15%. The stable electrical resistance and high reliability of ACF joints could be obtained. On the other hand, no any obvious delamination or failed joints could be observed within failure samples by SEM or SAT. Otherwise, the adhesion strength measured by shear test did not show any relations after the precondition test. We assumed that during the reflow process the entrapped adhesive matrix expanded much more than the conductive particles because of its higher coefficient of thermal expansion (CTE). Thus, induced thermal stress would separate the ACF joints and decrease the contact area of the conductive path.

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chip-stacking technology have received a great number of attentions. Solder micro bumps are widely applied in high density interconnections packaging, but its bonding temperature is still high during process. During chip stacking process, high bonding temperature would lead chip damage and chip warpage induced by the mismatch of coefficient of thermal expansion among each structure within the chip. Also, warpage would cause stress concentration happened within the chip and damage the device and micro interconnections. In order to meet the purpose of low temperature bonding, we demonstrated the chip-to-chip stacking module with a bump pitch of 30um by using non-conductive film in this study. The reliability of the chip-stacking module produced by such low temperature bonding approach was also estimated. A chip-on-chip (COC) structure was used as the test vehicles. There were about 3000 bumps totally in this test vehicle. For evaluating the feasibility of adhesive bonding by NCF in fine pitch micro bumps, Cu/Ni/Au micro bumps joined with Cu/Sn solder micro bumps was conducted by using NCF in this study. After assembly process, thermal cycling test, thermal humidity storage test and high current test were carried out to evaluate the reliability performance of the micro interconnections by such low temperature bonding approach. In this investigation, the chip-on-chip stacking module with a bump pitch of 30μm by using non-conductive film was achieved. The bonding results revealed that the contact resistance of micro joints was about 100 ∼ 350 MΩ. The high deviation of contact resistance was due to the non-melting contact between joined micro bump by soft tin solder. The reliability results revealed that the chip-stacking module produced by NCF could pass the reliability test of 1000 cycles of TCT and 1000 hours of THST. The results of high current test also showed that the NCF joint had excellence endurance against high current density of 5×104 A/cm2 for more than 1300 hours with an increase of contact resistance less than 2%. This study displayed that the NCF material had great potential to be applied in fine-pitch 3D chip stacking. The multi-chip stacking module with a TSV pitch of 20μm produced by NCF will also be presented in this investigation.

For evaluating the feasibility of adhesive bonding by NCF (non-conductive film) in micro bump joints, three types of micro joints were adopted in this study. The structure of the type I micro joints was Cu/Ni/Au while that of the type II micro joints was Cu/Ni/Au micro bump joined with Cu/Sn solder micro bump. Both the type I and type II micro joint were bonded by using NCF. The structure of the type III micro joints were the same, but the type III micro joints were produced by eutectic bonding. For the type III micro joints, the micro gap between chips was wrapped by a capillary underfill. The bonding results revealed that the contact resistance of the NCF joints was in the range of 100 Qm ∼ 400 Qm which was higher than that of eutectic joints. Electrical continuity of micro bump interconnection was monitored by measuring the contact resistance of four-point Kelvin structure and daisy chain during reliability test. Thermal cycling test and thermal humidity storage test were conducted to evaluate the reliability performance of these three types of micro interconnections. The reliability test displayed that the reliability performance of eutectic joints was better than that of the NCF joints. The study showed that NCF joints have great potential to be applied in low temperature bonding of fine pitch 3D IC stacking.

Flip chip assembly technology is an attractive solution for high I/O density and fine-pitch microelectronics packaging. Recently, high efficient GaN-based light-emitting diodes (LEDs) have undergone a rapid development and flip chip bonding has been widely applied to fabricate high-brightness GaN micro-LED arrays [1]. The flip chip GaN LED has some advantages over the traditional top-emission LED, including improved current spreading, higher light extraction efficiency, better thermal dissipation capability and the potential of further optical component integration [2, 3]. With the advantages of flip chip assembly, micro-LED (μLED) arrays with high I/O density can be performed with improved luminous efficiency than conventional p-side-up micro-LED arrays and are suitable for many potential applications, such as micro-displays, bio-photonics and visible light communications (VLC), etc. In particular, μLED array based selif-emissive micro-display has the promising to achieve high brightness and contrast, reliability, long-life and compactness, which conventional micro-displays like LCD, OLED, etc, cannot compete with. In this study, GaN micro-LED array device with flip chip assembly package process was presented. The bonding quality of flip chip high density micro-LED array is tested by daisy chain test. The p-n junction tests of the devices are measured for electrical characteristics. The illumination condition of each micro-diode pixel was examined under a forward bias. Failure mode analysis was performed using cross sectioning and scanning electron microscopy (SEM). Finally, the fully packaged micro-LED array device is demonstrated as a prototype of dice projector system.

In this research, thousands of 20 μm pitch microbumps with a diameter of 10 μm and a structure of pure Sn cap on Cu pillar were electroplated on 8 inch wafers, and those wafers were then respectively singularized to be top chip (5 mm × 5 mm) and bottom Si interposer (10 mm × 10 mm) for stacking. Two methods including conventional reflow and solid-liquid interdiffusion (SLID) bonding were chosen to interconnect the microbumps on the chip and on the interposer. In the former case, the as-plated Sn caps were fluxed with Senju Metal's WF-6400 paste, and the chip was then placed on a Si interposer using a SUSS FC-150 bonder at room temperature. Afterwards, the Sn caps on the chip and on the Si interposer were melted and interconnected at a peak temperature of 250°C in an ERSA's reflow oven (Hotflow 7). The flux residues were cleaned after reflow, and the microgap between the chip and the Si interposer were fully sealed by a Namics' capillary underfill with an average filler size of 0.3 um. Regarding the SLID bonding, the oxides on the as-plated Sn caps were removed by a plasma etcher first, and then the chip was placed on the interposer by the SUSS FC-150 bonder as well, subsequently, the Sn caps were heated up to 260°C to react with Cu to form Cu 6 Sn 5 completely. In the final, the intermetallic microjoints were also protected by the same capillary underfill. After assembling, the JEDEC preconditioning test was used to screen the test vehicles for reliability assessment, and then a temperature cycling test was performed to predict the lifespan of the microjoints. The test results showed that the microjoints formed by SLID bonding provided a superior reliability performance to those assembled by reflow. According to the images of focus ion beam (FIB), the intermetallic phases of Cu 6 Sn 5 and Cu 3 Sn coexisted at the interface between the Sn cap and the Cu pillar after reflow once, and some Kirkendall voids were found at the Cu 3 Sn / Cu pillar interface concurrently. When the microjoints undergone 3 times more reflow in the preconditioning test, the Kirkendall voids accumulated and was going to speed up the failure of microjoints as experienced just hundreds of temperature cycles. On the other hand, the microjoints produced by SLID bonding have not failed when thousands of temperature cycles passed. Based on those evidences, it is claimed here that SLID is an efficient bonding method to form reliable intermetallic microjoints for chip stacking.

3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2 at an ambient temperature of 150°C.

Computational visual attention (CVA) model is one of the methods which focus on finding region of interesting (ROI) in an image or in a scene. Similarity attention is one important task in CVA. If there are many objects in a scene, people will pick up the most abnormal one, which perhaps the similar one or dissimilar one, according to the composition objects of the scene. Capability of similarity attention enables human vision to promptly focus on similar or dissimilar regions in a scene. This paper implements this capability in the CVA model by attaching a high-level similarity comparison function to find ROI in the scene. The output of the model simulates the serial search mode and more approach to human visual behavior. Experimental results show that the function of similarity attention can be achieved successfully.

As high-speed, high-density, and high-performance are the primary IC development targets, packaging technologies play a key role to bring out the best performance of those ICs. In this paper, an active component formed by an active chip embedded technology is developed for the package of a high speed DDR2 memory device. Embedding of semiconductor chips into an organic substrate provide a solution to miniaturize the size of the package. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. In addition to wire bonding or w-BGA technologies, embedded package structure provides an alternative means to form redistribution circuits and electrical bonding pads. Meanwhile the electrical performance can be enhanced due to the wafer level package-like structure. Superior electrical performance is provided by forming shorter electrical path from chip pad to outer. In this study, a chip-in-substrate package (CiSP) with a real 50 um thick DDR2 memory IC is achieved using built-up technologies such as dielectric layer lamination, micro via drilling, and redistribution layer forming to implement the JEDEC-compliant DDR2 component. The PCB compatible process is a low-cost, high-yield, and versatile technology. Electrical performance similar to wafer level package and even better than wire bonding or w-BGA package can be achieved by adopting this proposed solution. The DDR2 component is assembled on a dual in-line memory module (DIMM) to study the feasibility and electrical performance of this developed package. Subsequent reliability test such as thermal cycle test (TCT) and thermal humidity storage test (THST) are examined. And electromigration (EM) of this test vehicle under high current density is simulated and tested.

We demonstrate an all-THz fiber-based swept-source imaging radar system. Our experiment shows that this radar can be used in real time to nondestructively detect and locate the concealed living objects with high stability and sensitivity.

The development of portable and flexible liquid crystal displays (LCDs) has led to a change in the substrate panel material. In the driver integrated circuit (IC) packaging process, ultra-thin chip on plastic (UTCOP) bonding is required to impart flexibility to plastic LCDs. In his study, the performance of 50-μm-thick ultra-thin chips on transparent polyimide (PI) substrate was investigated. To study the temperature distribution effect of bonding structures on the contact resistance during the anisotropic conductive adhesive (ACA) bonding process, three kinds of structures were evaluated: (1) a chip thickness of 670 μm, (2) a chip thickness of 50 μm, and (3) a 50-μm-thick chip with a 420-μm carrier IC of attached by thermo-release film. To determine the relationship between daisy-chain resistance and ACA-chip interface temperature, in-situ daisy-chain resistance and temperature during the bonding process were measured. The effect of the bonding structures on the UTCOP temperature distribution was analyzed using 3-D finite element (FE) modeling. The reliability of UTCOP was evaluated by thermal humidity storage testing (THST) at 85°C and 85% RH, thermal cycle testing (TCT) from −55°C to 125°C, and static bending testing at 10 mm radius of curvature. Scanning electron microscopy (SEM) cross sections of ACA joints and profiles of chip backs after bonding were analyzed to determine the failure reasons. Our results indicate that the temperature distribution of the bonding structure affected the electrical conductivity and reliability of the ACA joints. Structures with the lowest thermal conductivity had the best electrical contact resistance and reliability because that the structure-induced temperature distribution affects the ACA flow during bonding process. Optimizing this process made it possible to develop a highly reliable UTCOP assembly with ACA interconnections, greatly enhancing its potential for use in flexible LCDs in the near future.

Intention-oriented computational visual attention (ICVA) model attempts to imitate human vision by computational intelligence. This paper contributes to enabling the ICVA model with learning ability so as to acquire or change intention according to assigned image samples. This innovative design is called the self-learning ICVA model which contains a neuro-fuzzy network to learn intention from image samples. A well-trained self-learning ICVA model can find interested objects in images by extracting attentive areas and matching them with intention expressed by fuzzy rules. By extracting fuzzy rules from image samples, the self-learning ICVA model acquires or changes the intention. The whole design is verified by constructing an intelligent road sign detection system. Experimental results show the system succeeds in learning and seeking image content with rectangular road signs.

In this work, the porous Pd/SiO2/GaN Schottky diode was fabricated by thermal evaporation (TE) for hydrogen sensing. The current-voltage (I-V) characteristics of the studied device were measured under hydrogen concentrations of 15 - 9970 ppm H2/air and temperatures of 303 - 515 K. Furthermore, the hydrogen sensing performances of this device were investigated via the steady-state and transient detections. From experimental results, the studied device demonstrated excellent sensing performances with low detection limit (about ppb level), wide detection range (15 -9970 ppm), high sensitivity, and fast response and recovery rates (within several seconds for detection of 9970 ppm H2/air). For the detection of 15 ppm at 423 K, the relative sensitivity even reached to 490%. In addition, the relative sensitivity was increased as either the hydrogen concentration or the detection temperature was incresaed. As compared with the dense structured device, the porous structured Pd/ SiO2/GaN Schottky diode exhibited more superior sensing characteristics, especially at low hydrogen concentration with a relatively high sensitivity.

A sensitive, specific and accurate method for determination of arbidol in human plasma was developed. Arbidol and internal standard were extracted from plasma samples by liquid–liquid extraction with diethyl ether. The chromatographic separation was accomplished on a Shiseido C18 3 amp;956;m analytical column (100 mm × 2.0 mm i.d.) at a flow rate of 0.3 mL/min isocratically. Detection was performed on a single quadrupole mass spectrometer by selected ion monitoring (SIM) mode via electrospray ionization (ESI) source. The method had a chromatographic run time of 6 min and a good linear relationship over the range 1–1000 ng/mL. The limit of quantitation for arbidol in plasma was 1 ng/mL. The intra-day and inter-day precision (R.S.D.) was lower than 7 and accuracy ranged from 95 to 105. The proposed method enables unambiguous identification and quantification of arbidol in vivo and has been successfully applied to study the pharmacokinetics of arbidol in healthy male Chinese volunteers .

Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass substrate is hard to compete with. Herein, we focused on the packaging approach by adopting the newly development technology of rigid-flex packaging by introducing flexible interconnect. There are two packaging approaches we explore the concept for flexible FPDs. One is the stretchable interconnect and the other is ultra thin die attached method. The results show we can achieve the 25% stretchable metal trace on flexible substrate, such as PU or PDMS and the resistance is keeping as low as 5 ohm/cm without any deformation. Besides, by choosing the suitable adhesives, we can also demonstrate the strong reliable interface during the bending test. The reliability test shows the intriguing structure can be applied for the flexible panel displays.

High density packaging increasingly dominates the market share in LCD highlighting the need not only to decrease the pitch of bonding joints, but also to increase the I/O numbers of driver IC for high-end display applications. However, the shortage between two adjacent electrodes is a major problem when using conventional packaging technologies. Non-conductive film (NCF) is one of the interconnection materials which are increasingly used in LCD package and flip chip technology. There are many advantages using NCF in package, such as low cost, simplified process, and low temperature process. On the contrary, NCF bonded faces a challenge of yield. In this paper, we have developed a multi-points compliant bump (MPCB) using in NCF-bonded chip-on-flex (COF) process. Evaluating the effect of temperature, time, and load on electric resistance and peeling strength. A higher peeling strength is obtained at higher bonding load, temperature, and time. This indicated that the NCF with high curing degree is sufficient to hold the interconnection joints. The changes in daisy chain after 85degC/85%RH thermal humidity storage test (THST) for 500 hrs are measured. Due to MPCB deforms in bonding process, and releases counterforce in reliability test. Experimental results show that low bonding load, high bonding temperature and high bonding time is good for reliability.

This paper implements a wireless ARM-based automatic meter reading and control system (WAMRCS) for distribution automation. The WAMRCS is designed based on a 32-bit ARM microprocessor to deal with power data processing and relay control. In order to provide a cost-effective, wireless, always-connected, two-way data link between utility company and WAMRCS, the WAMRCS sends information of utility usage, power quality and outage alarm to utility company via GPRS network. Compared with analog utility meter reading by manpower, WAMRCS is more accurate, reliable, cost-effective, quick and free from man-made errors. It can provide extra capabilities such as distribution automation, load management and time-of-use rate.

In this paper, a new method for determining composition ratio of complexes was studied with ratio of double peak values at double wavelengths by UV spectrophotometry. The ratio of the maximum peak value to the minimum peak value and the composition ratio of complexes are the same. The calculation formula for the composition of complexes is deduced in accordance with beer's law and the theory of dissociation equilibrium of complexes: N = (deltaA2epsilonlambda1(MR) - deltaA1epsilonlambda2(MR)/(deltaA2epsilonlambda1(R) - deltaA1epsilonlambda2(R). The calculated value and that obtained by traditional method are agreeable. The method is reliable, simple, visual and quick.

This paper implements a GPRS-based embedded system for load management system in real time remote operation to power equipments in general applications. The proposed system is designed using a 32-bit ARM-7 embedded microprocessor system to carry on power data processing and relay control through GPRS mobile communication. In order to provide a cost-effective, wireless, always-connected, two-way data link function capability, the proposed system establishes a remoter monitor and control center to manage power equipment operation data, power parameters and outage signals. To activate the data flow, GPRS is used to handle real time message in two ways, from equipments to the control server, and from operator to the equipments. In this paper, the proposed system is successfully built up, and a full function of real time remote operation is tested with data collection, especially at a system outage. This paper verifies the proposed system is useful and effective to power equipment monitor and control in a real time and mobile condition

This study was designed to examine the optimal timing of intravenous lidocaine in attenuation of increase of intraocular pressure in response to laryngoscopy and tracheal intubation during induction of anesthesia.One hundred and thirty five adult patients of ASA class I, aged between 20-35 years, undergoing surgical procedures irrelevant to ophthalmology were enrolled for study. Patients were randomly assigned to one of five groups. In group II, III, IV and V the patients received intravenous injection of lidocaine (2 mg/kg), 1, 3, 5, 10 min before tracheal intubation, respectively. Group I in which patients did not receive lidocaine served as the control group.In patients of groups I, IV and V, the intraocular pressure increased significantly after intubation, whereas in those of groups II and III, the intraocular pressure did not. All patients in the five groups showed concomitantly a surge of blood pressure, but the magnitude of increase was smallest in group III in comparison with the other groups. The values of systolic and diastolic pressures 1 min after intubation were significantly less in groups III and IV than in the control group.In healthy patients aged between 20 and 35 the most optimal time of administration of intravenous lidocaine to attenuate the increase of intraocular pressure seemed to be the space between 1 to 3 min before laryngoscopy and tracheal intubation.