842 results on '"Yu, Shimeng"'
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102. Carbon-wrapped four-component Na–Ni–Ti–Co oxides via sol–gel process for NIB anode material with superior cycling stability
103. Outlook for RRAM’s Applications
104. Metal Oxide Resistive Switching Memory
105. Editorial: Novel materials, devices and solutions for brain-inspired sensing and computing
106. A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor
107. Direct Quantitative Extraction of Internal Variables from Measured PUND Characteristics Providing New Key Insights into Physics and Performance of Silicon and Oxide Channel Ferroelectric FETs
108. Scalable In-Memory Clustered Annealer with Temporal Noise of FinFET for the Travelling Salesman Problem
109. Total Ionizing Dose Effect in Tri-gate Silicon Ferroelectric Transistor Memory
110. MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine
111. Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter
112. Guest Editorial Memristive Circuits and Systems for Edge-Computing Applications
113. Design-Technology Co-optimization for Cryogenic Tensor Processing Unit
114. Performance and mechanism of illite in removing graphene oxide from aqueous solution
115. Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators
116. (Invited) Impact of Polarization Variation on Ferroelectric Field-Effect Transistor and Compute-in-Memory
117. Characterizing HfO2-Based Ferroelectric Tunnel Junction in Cryogenic Temperature
118. RRAM-Based Hardware Security Primitives
119. Weight Tuning of Resistive Synaptic Devices and Convolution Kernel Operation on 12 × 12 Cross-Point Array
120. Impact of Nonideal Resistive Synaptic Device Behaviors on Implementation of Sparse Coding Algorithm
121. Peripheral Circuit Design Considerations of Neuro-inspired Architectures
122. Introduction to Neuro-Inspired Computing Using Resistive Synaptic Devices
123. Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication
124. Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures
125. A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling
126. A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References
127. Spiral Compensation of Surface Error in Ultra-Precision Micro-milling of Spherical Micro Lens Array with a tilt spindle
128. Local Epitaxial Templating Effects in Ferroelectric and Antiferroelectric ZrO2
129. A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators
130. Improved Endurance with Electron-Only Switching in Ferroelectric Devices
131. Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving
132. Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling
133. Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide
134. A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays
135. Low-Frequency Noise Characteristics of BEOL-Compatible IWO Transistor
136. A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect
137. An Algorithm-Hardware Co-Design for Bayesian Neural Network Utilizing SOT-MRAM’s Inherent Stochasticity
138. GP3D: 3D NAND Based In-Memory Graph Processing Accelerator
139. Sensory neuron–expressed TRPC3 mediates acute and chronic itch
140. In-Memory 3D NAND Flash Hyperdimensional Computing Engine for Energy-Efficient SARS-CoV-2 Genome Sequencing
141. Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators
142. Standby Bias Improves the Endurance in Ferroelectric Field Effect Transistors due to Fast Neutralization of Interface Traps
143. Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation
144. BEOL-Compatible Superlattice FEFET Analog Synapse With Improved Linearity and Symmetry of Weight Update
145. Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators
146. RRAM Array Architecture
147. Introduction to RRAM Technology
148. Resistive Random Access Memory (RRAM)
149. RRAM Device Fabrication and Performances
150. Outlook for RRAM’s Applications
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