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Standby power frequently dominates the power budget of battery-operated ultralow power sensor nodes. Reducing standby power is therefore a key challenge for further power reduction. Applying known circuit techniques for standby power reduction is challenging since standby power of state-of-the-art sensor node systems is now on the order of nanowatts or less. Hence, the overhead of any leakage reduction technique quickly overshadows any gains. This brief proposes an efficient implementation method for super cutoff CMOS that exploits the unique conditions of power gating to enable a highly efficient charge pump design. The proposed techniques are applied to logic blocks and memory devices. For a very low initial standby power value of tens of picowatts, standby power reduction of up to 19.3 × and 29% is achieved for logic blocks and memory, respectively.

Process scaling has resulted in an exponential increase of the number of transistors available to designers. Meanwhile, global interconnect has not scaled nearly as well, because global wires scale only in one dimension instead of two, resulting in fewer, high-resistance routing tracks. This paper evaluates the use of three-dimensional (3D) integration to reduce global interconnect by adding multiple layers of silicon with vertical connections between them using through-silicon vias (TSVs). Because global interconnect can be millimeters long, and silicon layers tend to be only tens of microns thick in 3D stacked processes, the power and performance gains by using vertical interconnect can be substantial. To address the thermal issues that arise with 3D integration, this paper also evaluates the use of near-threshold computing---operating the system at a supply voltage just above the threshold voltage of the transistors. Specifically, we will discuss the design and test of Centip3De, a large-scale 3D-stacked near-threshold chip multiprocessor. Centip3De uses Tezzaron's 3D stacking technology in conjunction with Global Foundries' 130 nm process. The Centip3De design comprises 128 ARM Cortex-M3 cores and 256MB of integrated DRAM. Silicon measurements are presented for a 64-core version of the design.

Accurate measurement of synchronization cycle time is required for ultra-low power wireless sensor nodes with stringent power budgets. A multi-stage gate-leakage-based timer with boosted charging is proposed to address the high jitter of prior-art gate-leakage-based timers. The key approaches are faster load capacitor charging, wider voltage swing, and an improved gain sensing inverter. The proposed timer reduces RMS jitter by 8.1× and synchronization uncertainty by 4.1×, which allows hourly tracking with 200 ms uncertainty while consuming 660 pW. A novel closed-loop temperature compensation scheme with dynamic leakage adjustment is also proposed to achieve temperature sensitivity of 31 ppm/°C.

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.

A 1.0 mm3 general-purpose sensor node platform with heterogeneous multi-layer structure is proposed. The sensor platform benefits from modularity by allowing the addition/removal of IC layers. A new low power I2C interface is introduced for energy efficient inter-layer communication with compatibility to commercial I2C protocols. A self-adapting power management unit is proposed for efficient battery voltage down conversion for wide range of battery voltages and load current. The power management unit also adapts itself by monitoring energy harvesting conditions and harvesting sources and is capable of harvesting from solar, thermal and microbial fuel cells. An optical wakeup receiver is proposed for sensor node programming and synchronization with 228 pW standby power. The system also includes two processors, timer, temperature sensor, and low-power imager. Standby power of the system is 11 nW.

We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS. Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is >; 3x improvement over traditional operation at full supply voltage. This project demonstrates the feasibility of large-scale 3D design, a synergy between 3D and NTC architectures, a unique cluster-based NTC cache design, and how to maximize performance in a thermally-constrained design.

A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drive (SSD) applications, where standby mode efficiency with 100 mA load. To enhance efficiency in light load condition and to achieve wide operation load range, loss minimization by balancing conduction and switching loss is adopted and dynamic power gating scheme is applied for PFM mode operation. Moreover, robust dual mode operation is implemented with time-based control scheme, which enables operation with lower peak current for optimal loss balancing. The proposed converter is fabricated in 130 nm CMOS process with an area of 1.7 mm2. The measured efficiency for supplying 12 V output from 5.5 V input is 91% at its peak and 85% with extremely light load of 200 μA. It also achieves wide load range of 34.6 dB for > 85% efficiency and 18.8 dB for > 90% efficiency.

Since the emergence of the first computers in the 1940s, many different classes of computing systems, such as workstations, desktop PCs, and laptops, have been introduced to meet the ever-changing market needs, as predicted by “Bell’s Law.” Light-weight mobile computing devices were introduced in the early 2000s, and we expect to be surrounded by millions or trillions of small sensing/computing systems in the upcoming internet of things (IoT) era.

This paper presents a complete, autonomous, wireless temperature sensor, fully encapsulated in a 10.6mm3 volume. The sensor includes solar energy harvesting with an integrated 2 μAh battery, optical receiver for programming, microcontroller and memory, 8GHz UWB transmitter, and miniaturized custom antennas with a wireless range of 7 meters. Full, stand-alone operation was demonstrated for the first time for a system of this size and functionality.

Advancements in low power circuits and batteries have enabled the design of miniature sensors with tiny batteries. In such systems, implementing dynamic voltage scaling (DVS) is crucial for maximizing system lifetime. In this paper, a new switched capacitor (SC) converter that is capable of handling a wide range of load currents and output voltages is presented for on-chip DVS implementation. The proposed converter consists of multi-ratio multi-leaf SC stages and reconfigurable interconnect, enabling fine voltage resolution. The stage interconnect scheme enables cascaded or parallel connection of stages. The multi-leaf structure allows load-dependent switch size selection, offering a better trade-off between losses over a wide load range. A limited-voltage-swing switch-driving scheme allows efficient down-conversion from high battery voltage input. A prototype was fabricated in a 180 nm process, providing an output voltage with effective resolution of 16 mV over a load current range of 300 nA to 300 &mu, A (1000&times, ) from a 4 V battery. Efficiency greater than 62% and a peak efficiency of 77% are achieved under a light load (500 nA) over a voltage range of 400 mV to 1.6 V. Efficiency greater than 64% and a peak efficiency of 72% are achieved under a heavy load (200 &mu, A) over a voltage range of 700 mV to 1.6 V.

Recent progress in ultra-low-power circuit design is creating new opportunities for cubic millimeter computing. Robust low-voltage operation has reduced active mode power consumption considerably, but standby mode power consumption has received relatively little attention from low-voltage designers. In this work, we describe a low-voltage processor called the Phoenix Processor that has been designed at the device, circuit, and architecture levels to minimize standby power. A test chip has been implemented in a carefully selected 0.18 mum process in an area of only 915 times 915 mum2. Measurements show that Phoenix consumes 35.4 pW in standby mode and 226 nW in active mode.

With continuous miniaturization of electronic systems, mm-scale sensors are emerging as a future sensor system platform. Recent advancements in mm-scale sensor design is reviewed in this paper. A mm-scale sensor platform and its characteristics are presented and prototype implementation for diverse applications on recent literature are introduced.

This paper presents a complete, autonomous, wireless temperature sensor, fully encapsulated in a 10.6mm3 volume. The sensor includes solar energy harvesting with an integrated 2 μAh battery, optical receiver for programming, microcontroller and memory, 8GHz UWB transmitter, and miniaturized custom antennas with a wireless range of 7 meters. Full, stand-alone operation was demonstrated for the first time for a system of this size and functionality.

Moore's Law has received much attention over the last decades. However, the lesser known “Bell's law” has potentially had equal impact on the transformation of electronic systems. Bell's law dictates that every decade the size of a complete computing system shrinks in volume by 100x while the number of such devices per person increases. Bell's law has driven the transformation of gigantic mainframes in the 1960s to small handheld devices in the new millenium. It is generally held, that the next class of computing systems on the trajectory of Bell's law are miniature sensing systems that will instrument numerous aspects of our daily lives. In particular, we focus on millimeter sized systems which, being nearly invisible, will open up a host of new application areas in computing such as medical implantable devices for monitoring vital signs and disease, surveillance and entry detection, and environmental monitoring.

We present a 2×4×4mm 3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.

Low power electronic circuitry, including wirelessly interconnected sensor nodes, is a transformational technology that can be applied to a broad range of applications. These low power systems still require electrical power, ideally from ambient energy sources. Ambient sources of light can provide sufficient energy for these applications. Stray sunlight is more than adequate, though it is not available in all locations. Indoor lighting may also provide a sufficient energy source, though the characteristics of the spectrum are significantly different than the solar spectrum, where irradiance is confined to a narrower window in the visible spectrum. Energy-autonomous operation in mm-scale sensors have been achieved using photovoltaics based on silicon CMOS [1,2]. Improvements in energy harvesting are necessary to increase the duty cycle of the microsystem and to facilitate wireless transceivers. Photovoltaic cells consisting of materials with larger bandgap energy, such as GaAs, provide a better match to the indoor light spectrum, reducing thermalization losses and increasing power generation. The larger voltage provided by higher bandgap materials such as GaAs can also improve the efficiency of the overall system, where higher voltages are beneficial for the battery storage system and DC-DC converter. While the cost of GaAs photovoltaics is significantly higher than for silicon, and is currently prohibitive for large area solar energy production, the small power requirements and associated size requirements for photovoltaic cells makes GaAs an affordable option. Requirements for active and standby power are 10μW and 0.5nW, respectively[1,2], where perpetual operation may be achieved using a photovoltaic cell with area on the order of 1 mm 2 .

An ARM-based sensing platform powered entirely by small-scale benthic microbial fuel cells (MFCs) for oceanic sensing applications is presented. The ultra-low power chip featuring an ARM Cortex-M0 processor, 3kB of SRAM, and power management unit (PMU) with energy harvesting from MFCs is designed to consume 11nW in sleep mode for perpetual sensing operation. A small-scale micro-MFC with 21.3cm 2 anode surface area was connected to the on-chip PMU to charge a thin film battery of 1mAh capacity. A 49.3-hour long-term experiment with 8-min sleep interval and 1 sec wake-up time demonstrated the sustainability of chip-on-mud concept. During sleep mode, the system charges the 4V battery at 380nA from the micro-MFC generating 5.4μW of power, which can support up to 20mA of active mode current.

Recent advances in low-power circuits have enabled mm-scale wireless systems [1] for wireless sensor networks and implantable devices, among other applications. Energy harvesting is an attractive way to power such systems due to limited energy capacity of batteries at these form factors. However, the same size limitation restricts the amount of harvested power, which can be as low as 10s of nW for mm-scale photovoltaic cells in indoor conditions. Efficient DC-DC up-conversion at such low power levels (for battery charging) is extremely challenging and has not yet been demonstrated.

Electrocardiography (ECG) is a critical source of information for a number of heart disorders. In arrhythmia studies and treatment, long-term observation is critical to determine the nature of the abnormality and its severity. However, even small body-wearable systems can impact a patient's everyday life and signals captured using such systems are prone to noise from sources such as 60Hz power and body movement. In contrast, implanted devices are less susceptible to these noise sources and, while having closer-spaced electrodes, can obtain similar quality ECG signals due to their proximity to the heart [1]. In addition, implanted devices enable continuous monitoring without affecting patient quality of life. As in other implantable systems, low power consumption is a critical factor; in this case to provide a sufficiently long operating time between wireless recharge events.

True random number generators (TRNGs) use physical randomness as entropy sources and are heavily used in cryptography and security [1]. Although hardware TRNGs provide excellent randomness, power consumption and design complexity are often high. Previous work has demonstrated TRNGs based on a resistor-amplifier-ADC chain [2], oscillator jitter [1], metastability [3-5] and other device noise [6-7]. However, analog designs suffer from variation and noise, making them difficult to integrate with digital circuits. Recent metastability-based methods [3-5] provide excellent performance but often require careful calibration to remove bias. SiN MOSFETs [6] exploit larger thermal noise but require post-processing to achieve sufficient randomness. An oxide breakdown-based TRNG [7] shows high entropy but suffers from low performance and high energy/bit. Ring oscillator (RO)-based TRNGs offer the advantage of design simplicity, but previous methods using a slow jittery clock to sample a fast clock provide low randomness [1] and are vulnerable to power supply attacks [8]. In addition, the majority of previous methods cannot pass all NIST randomness tests.

In this demo, we explore the critical role that power plays in the development of a mm-scale system. We argue that any practical deployment of a mm-scale system must have a significant energy harvesting component. We demo the newest M3 system, a self-contained, 1 mm3, energy-harvesting computing platform capable of short-range (order cm) wireless transmission. Finally, we present some of the M3's innovations that enable its current basic operation and discuss some of the open problems that remain before a smart dust network becomes operable.

Novel ultra low-leakage ESD power clamp designs for wireless sensor applications are proposed and implemented in 0.18μm CMOS. Using new biasing structures to limit both subthreshold leakage and GIDL, the proposed designs consume as little as 43pW at 25 C and 119nW at 125 C with 4500V HBM level and 400V MM level protection, marking an 18-139× leakage reduction over conventional ESD clamps.

We present a self-adapting power management unit (PMU) for ultra-low power wireless sensor nodes. The PMU uses 1.03nF of on-chip MIM capacitance in a reconfigurable switched-capacitor network (SCN) that automatically adapts to different battery voltages for down-conversion and different harvesting sources/harvesting conditions for up-conversion. The PMU achieves 63.8% / 60.7% down-conversion efficiency at 17.9μW active mode / 12.8nW sleep mode power loading. With the adaptive down-conversion ratio, load power range is improved by 3.76× and 5.48× in sleep and active mode, respectively. We show how the proposed adaptation method enables harvesting with solar, microbial fuel cell, and thermal energy sources, increases harvesting efficiency by 1.92× and achieves the peak extraction efficiency of 99.8% for solar cell.

We propose an ultra-low power optical wake-up receiver with a novel front-end circuit and communication scheme suitable for miniature wireless sensor node applications. Named “FLOW” for Free-space Low-Power Optical Wake-up, the receiver consumes 695pW in standby mode, which is ∼6,000× lower than previously reported RF and ultrasound wake-up radios. In active mode, it consumes 140pJ/bit at 91bps. A pulse width modulated communication encoding scheme is used, and chip-ID masking enables selective batch-programming and synchronization of multiple sensor nodes.

Ultra-low voltage design makes signal level conversion a critical component in modern low power designs. This paper proposes a static level converter operating in the subthreshold regime, called SLC (Split-control Level Converter). Using a novel circuit structure, SLC effectively eliminates the high leakage and short circuit currents in previous approaches. Designed for 300mV to 2.5V conversion and fabricated in 130nm CMOS, measured results show 2.3×, 9.9×, and 5.9× improvements over conventional DCVS structures in delay, static power, and energy per transition, respectively. Even with the smallest area among wide-range level converters, it also has 5.2× smaller standard deviation in delay and only 5.6% change in FO4 delay with 10% V DDL drop, demonstrating robustness.

This article consists of a collection of slides from the author's conference presentation on Centip3De, a 64-core, three dimensional (3D) stacked near-threshold system. Some of the specific topics discussed include: power management considerations with processor performance; threshold computing and design; architectural impact of near threshold computing (NTC) versis large scale 3D CMP; NTC architectures; cache timing analysis; system specifications and design of the Centip3De system; and an evaluation of 2-layer stacking processing.

Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor nodes.

We propose a low power battery voltage supervisory circuit for micro-scale sensor systems that provides power-on reset, brown-out detection, and recovery detection to prevent malfunction and battery damage. Ultra-low power is achieved using a 57pA, fast stabilizing two-stage voltage reference and an 81pA leakage-based oscillator and clocked comparator. The supervisor was fabricated in 180nm CMOS and integrated with a complete 1 mm3 sensor system. It consumes 635pW at 3.6V supply voltage, which is an 850× reduction over the best prior work.

Recent high performance IC design has been dominated by power density constraints. 3D integration increases device density even further, and these devices will not be usable without viable strategies to reduce power consumption. This paper proposes the use of near-threshold computing (NTC) to address this issue in a stacked 3D system. In NTC, cores are operated near the threshold voltage (∼200mV above Vth) to optimally balance power and performance [1]. In Centip3De, we operate cores at 650mV, as opposed to the wear-out limited supply voltage of 1.5V. This improves measured energy efficiency by 5.1×. The dramatically lower power consumption of NTC makes it an attractive match for 3D design, which has limited power dissipation capabilities, but also has improved innate power and performance compared to 2D design.

Wireless sensor nodes have many compelling applications such as smart buildings, medical implants, and surveillance systems. However, existing devices are bulky, measuring >1cm3, and they are hampered by short lifetimes and fail to realize the “smart dust” vision of [1]. Smart dust requires a mm3-scale, wireless sensor node with perpetual energy harvesting. Recently two application-specific implantable microsystems [2][3] demonstrated the potential of a mm3-scale system in medical applications. However, [3] is not programmable and [2] lacks a method for re-programming or re-synchronizing once encapsulated. Other practical issues remain unaddressed, such as a means to protect the battery during the time period between system assembly and deployment and the need for flexible design to enable use in multiple application domains. To this end, we propose a 1.0mm3 general-purpose heterogeneous sensor node platform with a stackable multi-layer structure that includes a new, ultra-low power I2C (Inter-Integrated Circuit) interface for inter-layer communication. The system has an ultra-low-power optical wakeup receiver and GOC (Global Optical Communication), which enables re-programming and synchronization. It also includes an ultra-low power PMU (Power Management Unit) with BOD (BrownOut Detector) to prevent processor malfunctions and battery damage. The BOD also controls a POR (Power-On Reset) module in other layers to enable a proper reset sequence. Image and temperature sensors are implemented, but the modularity of the system allows end-users to easily replace or add layers to incorporate specific circuits in appropriate technologies as needed.

Radio activation in ultra-low-power wireless sensor nodes can require 5–6 orders of magnitude higher power than the sensor's average power consumption. Therefore, accurate timers that allow multiple sensor nodes to synchronize their radio communication are of critical concern for minimizing radio energy consumption. In this paper, we review ultra-low power timers and demonstrate their importance for the overall sensor node energy budget. We also propose a multistage gate-leakage-based timer with boosted charging and temperature compensation that reduces the synchronization uncertainty by 4.7× compared to the best prior gate-leakage-based timer with 660pW power consumption. Effective temperature sensitivity is reduced to 31ppm/°C.

A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the lowest power eDRAM previously reported. With an area-efficient single inverter sensing scheme designed for R/W speed compatibility with ultra-low power processors, 58% array efficiency is maintained for memories as small as 2kb and for as few as 32 bits per bitline.

Bell's Law predicts continual reductions in the size of computing systems. We investigate the status of the next paradigm shift that will usher in ubiquitous computing - sub-mm3 sensor nodes. However, this form factor remains beyond the capabilities of modern integrated circuit design techniques due to battery size. This paper describes new ultra-low power circuit techniques applied to digital processors, memory, power management, and a special focus on standby mode operation, that will bring mm3 sensor nodes to reality.

The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing

Standby power can dominate the power budgets of battery-operated ultra-low power processors, and reducing standby power is the key challenge for further power reduction. State-of-the-art ultra low voltage sensors consume hundreds of nW in wake mode and 100 pW or less in standby mode. Therefore, applying known circuit techniques for further standby power reduction is very challenging. In this paper, we extend known standby power reduction techniques for use in ultra-low power processors. In particular, we propose structures that enable the use of super cut-off voltages throughout the design with minimal power overhead. Different strategies for power gated logic blocks and memory cells are investigated.

An integrated platform for sensor applications, called the Phoenix Processor, is implemented in a carefully-selected 0.18 mum process with an area of 915 times 915 mum2, making on-die battery integration feasible. Phoenix uses a comprehensive sleep strategy with a unique power gating approach, an event-driven CPU with compact ISA, data memory compression, a custom low leakage memory cell, and adaptive leakage management in data memory. Measurements show that Phoenix consumes 29.6 pW in sleep mode and 2.8 pJ/cycle in active mode.

The influence of carrier concentration and oxygen vacancy on the performance of amorphous-indium–tin–zinc-oxide (a-ITZO) thin-film transistors (TFTs) is reported. The ITZO TFT with lowest carrier concentration and oxygen vacancy has a high field-effect mobility (μ FE) of 37.2 cm2/V•s, a high on/off current ratio (I ON/I OFF) of ∼1 × 107 and a low subthreshold swing (SS) of 0.93 V/decade. By increasing the carrier concentration and oxygen vacancy, μ FE, I ON/OFF and SS were surprisingly degraded to 14.4 cm2/V•s, ∼4 × 104 and 4.01 V/decade, respectively. By controlling the carrier concentration and oxygen vacancies of ITZO bulk, improvement of the performance in TFT devices can be achieved. The proposed high μ FE of 37.2 cm2/V•s is enough for the application of next-generation displays requiring ultra-high resolution and high-frame-rate displays.