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Three improvements are suggested upon an incremental attribute evaluation algorithm proposed by the first author. The resulting algorithm allows multiple subtree replacement and cancels three auxiliary tables required by the previous version.

Visual languages have an important role in modeling systems, specification of software, and in specific application domains. By using visual properties like spatial placement or line connections complex structures can be presented, so that humans can understand them quickly. Visual languages can be based on domain-specific metaphors, so that domain specialists can use their conventional way of description and abstraction.For working with a visual language, a specialized graphical frontend is needed. In contrast to textual languages, general purpose editors are insufficient for visual languages, because each visual language has its particular graphical requirements. The frontend should provide methods to aid efficient drawing and restructuring of visual expressions. Often, language-specific structure editors are used as frontends for visual languages. The visual program is stored in a language-dependent data structure. The user interacts with one or more visual representations. Edit operations are directly applied to the underlying structure and after a change the graphical representation is recomputed.The implementation of visual languages requires a wide range of conceptual and technical knowledge from issues of user interface design and graphical implementation to aspects of analysis and transformation for languages in general. We present a powerful toolset that incorporates such knowledge [C. Schmidt and U. Kastens. Implementation of visual languages using pattern-based specifications. Software - Practice and Experience, 35(2):121–131, Nov. 2003]. It generates editors from high level specifications: A language is specified by identifying certain patterns in the language structure, selecting a visual representation from a set of precoined solutions, and associating the pattern to constructs of the abstract grammar. A complete visual structure editor is generated from such a specification. It represents visual programs by attributed abstract trees. Therefore, further phases of processing visual programs can be generated by state-of-the-art tools for compiler construction. Even challenging visual languages can be implemented with reasonable small effort and with rather limited technical knowledge. The approach is suitable for a large variety of visual language styles.

Bytecode verification forms the corner stone of the Java security model that ensures the integrity of the runtime environment even in the presence of untrusted code. Limited devices, like Java smart cards, lack the necessary amount of memory to verify the type-safety of Java bytecode on their own. Proof carrying code techniques compute, outside the device, tamper-proof certificates which simplify bytecode verification and pass them along with the code. Rose has developed such an approach for a small subset of the Java bytecode language.In this paper, we extend this approach to real world Java software and develop a precise model of the memory requirements on the device. We use a variant of interval graphs to model liveness of memory regions in the checking step. Based on this model, memory-optimal checking strategies are computed outside the device and attached to the certificate.The underlying type system of the bytecode verifier has been augmented with multi-dimensional arrays and recognizes references to uninitialized Java objects.Our detailed measurements, based on real world Java libraries, demonstrate that the approach offers a substantial improvement in size of certificate over the similar approach taken by the KVM verifier. Worst case memory consumption on the device is examined as well and it turns out that the refinements based on our model save a significant amount of memory.

Procedural abstraction is an important concept for functional and imperative programming as well. Compilers should implement procedures and calls as efficient as possible. This paper addresses techniques for both memory and runtime improvements of procedure calls. Usual implementations allocate storage for local objects of procedures (i.e. parameters, result and local variables) either in activation records on a runtime stack in the case of recursive procedures or in a global storage area otherwise. We show that objects of recursive procedures can also be allocated globally, if certain conditions on their lifetime are met. We present a method for systematic lifetime analysis based on a context-free grammar which describes the calling structure of the program. It is introduced for a simple functional language and then extended to cover further commom language properties. Furthermore it is shown that the method can nicely be combined with context dependent improvements of the compilation of calling sequences, e.g. for tail recursive calls.

This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a dual design flow, using a central processor specification as reference for the hardware development and the automatic generation of a C-compiler based tool chain. Using our modular rapid prototyping environment RAPTOR and the RF-frontend DB-SDR, functional verification of SDR applications can be performed. An 802.11b transmitter SDR implementation is mapped on our CoreVA a VLIW architecture and evaluated in terms of execution time and energy consumption. By introducing application specific instruction set extensions and a dedicated hardware accelerator, execution time and energy consumption could be reduced by about 90%.

During a typical development process of an embedded application specific processor (ASIP), the architecture is implemented multiple times on different levels of abstractions. As a result of this redundant specification, certain inconsistencies may show up. For example, the implementation of an instruction in the simulator may differ from the HDL implementation. To detect such inconsistencies, we use register trace comparison. Our key contribution is a generic method for systematic trace synchronization. Therefore, we convert a micro-architectural trace into an architectural trace. This method considers pipeline hazards and non-uniform write latencies. To simplify the validation of a processor, we further have implemented an automatic validation environment that includes a tool which points the developer directly to erroneous instructions. The flow has been validated during the development of our CoreVA architecture for mobile applications.