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Ultra-thin-body (UTB) germanium-on-insulator (GeOI) substrates with Si-passivated back interfaces have been fabricated by using advanced epitaxial-lift-off (ELO) technology. Performance of UTB GeOI p-MOSFETs with body thickness (T body) in the 4–16 nm range has also been characterized. Si-passivated back interfaces have been fabricated and found to be effective in mitigating the unpleasant hole-mobility degradation in the UTB GeOI regime owing to the suppression of the back interface scattering.

In this paper, using a ballistic, full-band, and atomistic simulation approach based on the nearest-neighbor tight-binding model and the Non-equilibrium Green's Function formalism, the static and RF performance of a (100)/ strained-Si, (100)/ In0.53Ga0.47As, as well as (111)/ GaSb n-type double-gate ultra-thin-body FETs are analyzed and compared. All the structures are designed according to the ITRS specifications for 2020. Due to a relatively large density-of-states, but also high electron velocity, the GaSb FET represents a good compromise between the strained-Si and InGaAs devices. It exhibits therefore the highest ON-current at a given OFF-current, about 10-15% higher than strained-Si and 25-30% higher than InGaAs. However, in terms of current-gain cut-off frequency, the InGaAs FET is far ahead of its two counterparts, outperforming them by a factor of ~3.

We report the demonstration of an ultra-thin-body In 0.7 Ga 0.3 As-on-nothing N-MOSFET where a self-aligned cavity is formed right beneath the channel layer. Self-aligned Pd-InGaAs source/drain (S/D) contacts were integrated. The gate length L G of 130 nm is the smallest achieved with self-aligned contacts. With effective reduction of subsurface leakage current by the III–V-on-nothing device structure, DIBL of 248 mV/V and SS of 135 mV/decade were achieved.

This paper presents a modified UTB SOI TFET structure and a thorough simulation study of various device design parameters on this structure.

In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150–220 GHz. Effect of operation regime, sub- strate bias, channel width and high temperature (up to 250 ° C) on analog figures-of-merit (FoM) are ana- lyzed. Benchmarking of UTBB with other technologies (as planar FD SOI, different FinFETs, UTB with thick BOX) is presented. Ó

We have investigated carrier transport properties in ultra-thin body (UTB) Ge-on-Insulator (GeOI) MOSFETs for the first time. Both n- and p-channel MOSFET operation fabricated on 9 nm GeOI has been demonstrated. In addition, a significant difference of Ge crystallinity in the front-channel from that in back-one is reported to explain the mobility degradation in UTB region.

We present UTBB devices with a gate length (L G ) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V bb ) enables V t modulation of more than 125mV with a V bb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V t and power management applications. We explore the impact of GP, BOX thickness and V bb on local V t variability for the first time. Excellent A Vt of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I g ) and lower external resistance (R ext ), thanks to a thicker inversion gate dielectric (T inv ) and body (T si ) thickness.

This paper explores the challenges facing the 22nm process generation and beyond. CMOS transistor architectures such as ultra-thin body, FinFET, and nanowire will be compared and contrasted. Mobility enhancements such as channel stress, alternative orientations, and exotic materials will be explored. Resistance challenges will be reviewed in relation to key process techniques such as silicidation, implantation and anneal. Capacitance challenges with traditional and new architectures will be discussed in light of new materials and processing techniques. The impact of new transistor architectures and enhanced channel materials on traditional junction engineering solutions will be summarized.

In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (A VO ) and cut-off frequency (f T ) along with a broader analog ‘sweet spot’ in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (∼ 10 µA/µm) but extend up to 100 µA/µm which corresponds to optimum A VO and f T performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in f T along with a 2 fold enhancement in A VO . This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.

The effects of ≪110≫- and ≪111≫-directed uniaxial compressive strain on hole mobility in (110)-oriented ultra-thin body pFETs have been investigated systematically for the first time. It is found that the strain effect in ≪110≫-directed ultra-thin body pFETs is severely degraded due to small change in conduction effective mass and density-of-states reduction. It is also confirmed by measurements and subband structure calculations that ≪111≫-directed ultra-thin body pFET is free from these degradation mechanisms and achieves larger hole mobility enhancement than ≪110≫-directed ultra-thin body pFET, caused by larger effective mass change and smaller density-of-states reduction.

This paper analyzes and compares the stability, margin, and performance of Ultra-Thin-Body (UTB) SOI 6T SRAM cells operating in subthreshold region with single mid-gap and dual work function (WF) design. Our results indicate that UTB SOI 6T SRAM cells using dual quarter band-gap WF devices (NFET/PFET = 4.35eV/4.95eV) show comparable Read Static Noise Margin (RSNM) and 84% improvement in Write Static Noise Margin (WSNM) as comparaed with that using the single mid-gap WF devices. The “cell” access time improves significantly with correspondingly higher stand-by leakage. Our study suggests that the quarter band-gap WF devices not only support the high performance applications but also meet the stability requirement and offer higher performance while trading-off leakage for subthreshold SRAM applications.

This paper analyzes the stability, margin, and performance of Ultra-Thin-Body (UTB) SOI 6T/8T SRAM cells operating in subthreshold region. An analytical SNM model for UTB SOI 6T/8T SRAM cells operating in the subthreshold region is presented to investigate the Read SNM (RSNM) and Write SNM (WSNM). Our results indicate that back-gating technique is more effective in the subthreshold region than in the superthreshold region for improving RSNM and WSNM. The UTB SOI 6T SRAM cell with back-gating technique to increase the strength of the pull-up transistors and decrease the strength of the pass-gate transistors shows comparable RSNM in the subthreshold region with the 10T bulk subthreshold SRAM cell and an improvement in RSNM variation. Due to better electrostatic integrity, back-gating technique (pull-up PFET with positive back-gate bias, pull-down/pass-gate NFET's with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell β-ratio shows limited improvement on RSNM and has no benefit on SNM variability for subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2X larger than the 6T SRAM cell in the subthreshold region. Mixed-mode device/circuit simulations show that 6T/8T UTB SOI SRAMs operating in the subthreshold region can meet/support the stability, leakage/density, and frequency requirements for intended application space of subthreshold SRAMs.

This paper investigates the Static Noise Margin (SNM) of Ultra-Thin-Body (UTB) SOI SRAM cells operating in subthreshold region using analytical solution of Poisson's equation validated with TCAD simulations. An analytical SNM model for UTB SOI SRAM cells operating in subthreshold region is presented. Our results indicate that back-gate bias (V bg ) can mitigate the Read SNM (RSNM) variability of UTB SOI SRAM cells in the subthreshold region, and the improvement of SNM variability is more significant than superthreshold region. Increasing cell β-ratio shows limited improvement on RSNM and has no benefit on SNM variability for subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2X larger than the 6T SRAM cell in subthreshold region.

Ytterbium silicide provides a low Schottky barrier height to electron on n-type silicon. This property makes this material very attractive for the realization of Source/Drain contacts for n-type MOSFETs. In this communication, the study of structural and electrical properties of YbSi2-x fabricated at different temperature in Ultra-High Vacuum condition without any protective layers is presented. N-type SB-MOSFETs with ytterbium silicide based S/D contacts were fabricated at optimal silicidation temperatures on SOI substrate with an ultra thin body.

The intrinsic parameter fluctuations induced by random discrete dopants (RDD) in nano-scaled MOSFETs are studied by applying the quantum mechanical approach. The increase of effective oxide thickness (EOT) by the quantum mechanical corrections generally makes gate controllability worse. However, as far as ultra thin body (UTB) devices, the increase of EOT improves gate controllability by suppressing leakage current because it reduces electrical body thickness by the constraint of the physical body thickness.

We present a parameter extraction technique for higher-order transport models for a 2D electron gas in ultra thin body SOI MOSFETs. To describe 2D carrier transport we have developed a self consistent Schrodinger-Poisson Subband Monte Carlo simulator. The method takes into account quantization effects and a non equilibrium distribution function of the carrier gas, which allows an accurate description of the parameter behavior for high electric fields. Finally the results are compared with the transport parameters of 3D bulk electrons and the influence of the channel thickness on the mobility is investigated.

Much attention has been paid to ultra-thin body (UTB) and double-gate (DG) MOSFETs because of their superior immunity to short channel effect. However, it has been reported that the electron mobility is degraded in DG compared with single-gate (SG) in (100) UTB nMOSFETs with SOI thickness (tSOI) of around 5-15 nm (Uchida et al., 2003). On the other hand, it has been reported that the hole mobility is enhanced in (100) DG pMOSFETs with tSOI of around 5-6 nm (Tsutsui et al., 2006). In order to design nano-scale DG CMOSFETs such as FinFETs, it is quite important to understand electron mobility behaviors in DG and to identify the suitable device parameters without mobility degradation. In this study, electron mobility in (100) SG and DG with tSOI of less than 5 nm is experimentally investigated. It is found for the first time that no mobility degradation in DG compared with SG occurs when tSOI is 1.7 nm due to strong quantum confinement by ultimately thin SOI.

Mobility in single-gate (SG) and double-gate (DG) ultra-thin body (UTB) SOI MOSFETs under uniaxial tensile stress has been systematically examined. Mobility enhancement in both UTB nMOSFETs and pMOSFETs by stress is experimentally demonstrated for the first time. The enhancement in UTB nMOSFETs is larger than the prediction by theory. The mobility enhancement by stress in DG UTB nMOSFETs and pMOSFETs is also observed. The enhancement may originate from not only the subband energy shift but effective mass change.

An accurate and efficient one dimensional self-consistent numerical model of double gate MOS structure is presented based on finite element method. The model is developed using FEMLAB considering wave function penetration effect into gate oxide. Hence, penetration effect is revealed and presented for full depleted double gate MOSFET. Accuracy of the model has been verified by comparing with established results.

We report on the fabrication of high-performance ultra-thin-body (UTB) SnO2 thin-film transistors (TFTs) using microwave-irradiation post-deposition annealing (PDA) at a low process temperature (

As planar MOSFETs are scaled down, it is more and more difficult to achieve the scaled transistors with high performance. One of the key issues must be large source/drain (S/D) resistance as well as short channel effects (SCEs) (Ghani et al., 2001). These are in trade-off relation because shallow junction for reducing SCEs causes the increase of S/D resistance. One of the solutions to solve both problems may be elevated S/D technique. However, it seems to be another burden in consideration of growing the epitaxial layers on thin body (Widodo et al., 2005). Another solution is to reduce the spacer thickness (Yang et al., 2003). Through this approach, we can reduce the S/D resistance without any sacrifice of short channel effect (SCE) immunity. The requirements of spacer thickness and parasitic S/D resistance along technology node are shown in this paper. Recently, we proposed and successfully demonstrated partially insulated MOSFETs (PiFETs) as an alternative of ultra thin body (UTB) SOI devices (Kim et al., 2005). These are free from floating body, heat dissipation and high cost in comparison with conventional UTB SOI transistors. Despite of these merits, PiFETs like UTB SOI devices still suffer from large S/D resistance as their gate length are scaled down. In this paper, we evaluate characteristics of bulk MOSFETs with ultra thin spacer (UTS) and demonstrate the improved performance of 16 nm UTS PUC MOSFETs among PiFETs due to reduced S/D resistance

This paper describes an experimental determination of the value of eta in ultra thin body (UTB) nMOSFET with SOI thickness ranging from 30 nm down to 5 nm. It is found experimentally for the first time that the eta value is larger than frac12 when SOI thickness is thinner than 12 nm. The meaning of eta value is discussed in terms of occupancy of the lowest subband of 2-fold-valley

Simulations of metal (Schottky) source/drain (S/D) ultra-thin-body fully depleted SOI n-channel MOSFETs, single and dual gate, were performed using parameters associated with ITRS LSTP targets for 2006 through 2018. By optimizing S/D-to-channel underlap for a given S/D barrier height, off-current can be reduced to match the ITRS LSTP specification for each year. ITRS on-current targets then establish limits on the S/D barrier height

The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has been developed. The impact of discrete random dopants in the source and drain regions on 6T SRAM cells has been investigated for well scaled ultra thin body (UTB) SOI MOSFETs with physical channel length in the range of 10nm to 5nm.

We report for the first time an experimental evidence of mobility enhancement in ultra-thin body Double-Gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single and double-gate mode is measured and the temperature dependence of mobility is also studied. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low inversion densities.

Deca-nanometer double-gate MOSFETs is studied using a quantum Wigner Monte Carlo approach, including electron-phonon scattering. Intersubband coupling elements are explicitly calculated and proven to be small in doublegate MOSFETs. This allows quantum transport simulations to be analyzed using decoupled subbands. For long gate length the semi-classical result is recovered. An increasing tunneling component of the drain current with decreasing gate length is obtained. The results clearly show the importance of scattering for gate lengths as short as 25 nm. Performance enhancement due to ballistic transport can thereby be estimated.

This paper reports the first experimental demonstration of superior mobility in [110]-oriented UTB pMOSFETs with t/sub SOI/ ranging from 32 nm down to 2.3 nm. It is shown that the mobility, which is much higher than that in the universal curve in conventional (100)-oriented pMOSFET, is not degraded until t/sub SOI/ is thinned to 3 nm. The high mobility in the UTB regime in [110] pMOSFET is attributed to subband modulation by carrier confinement and heavier hole effective mass normal to channel surface.

For the first time, we show the experimental inversion mobility data on ultra thin [110] SOI substrates for thickness as thin as 6nm. Both electron and hole mobility in ultra thin [110] SOI are evaluated as a function of SOI thickness. In addition, novel processes such as [110] selective epitaxy and extremely thin cobalt disilicide CoSi/sub 2/ are developed. Ring oscillators and SRAM cell are demonstrated for the first time on 6nm [110] ultra thin SOI. When compared to ultra thin SOI in (100) substrate, we observe /spl sim/33% drive current enhancement in PFETs at Lg=50nm and /spl sim/1.8X hole mobility enhancement.

In this work, the speed performance and static power dissipation of the ultra-thin body (UTB) MOSFET are comprehensively investigated, with both DC and AC behaviors considered for the first time. The insightful results show that it is unadvisable to decrease the silicon body thickness continually to achieve better short channel performance with silicon film thickness below 8 nm. Source/drain extension width (lsp) and silicon film thickness (tsi) are two independent parameters to influence the speed and static power dissipation of UTB SOI MOSFET respectively, which can result in great design flexibility. The optimal design regions of the silicon body thickness (tsi) and source/drain extension width (lsp) for LOP (low operating power) and HP (high-performance logic) applications are given respectively, which shed light on UTB SOI MOSFET design. For the first time, based on the different impact of physical and geometric parameters on device characteristics, a method to alleviate the contradiction between power and speed of UTB SOI MOSFET is proposed.

A process/physics-based compact model for the nonclassical double-gate (DG) MOSFETs with ultra-thin bodies is overviewed, and then used in Spice3, to explore optimal design for nanoscale DG-FinFET CMOS and to project possible performances near the end of the SIA 2003 ITRS.

This paper describes the mobility in ultra thin body SOI pMOSFETs. It is experimentally demonstrated that the mobility in 10.2-nm-thick SOI pMOSFET degrades only due to the increased acoustic phonon scattering, while other degradation mechanisms appear in 4.3-nm-thick device. It is also demonstrated that the mobility in 4.3-nm-thick device shows universal characteristics against effective electric field for various substrate biases, which is the same behavior as bulk MOSFETs.

Optimization of source/drain (S/D) extrinsic resistance of ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFETs with recessed and/or elevated suicide contact structure is investigated through new simplified physical compact modeling and 2-dimensional simulation calibrated with 90-nm SOI technology. It is found that the optimum suicide contact can be located below SOI layer surface in elevated contact structure if effective contact length is highly scaled. The closed-form analytical expressions provide a simple guideline for suicide contact design with respect to SOI thickness and contact length in self-aligned suicide technology.

This paper presents an experimental examination of hole mobility in ultra-thin body (UTB) SOI MOSFETs, covering wide ranges of T/sub SOI/ (between /spl sim/3.7 nm and /spl sim/50 nm), and temperature (between /spl sim/79 K and /spl sim/320 K). This paper addresses the observed strong degradation of hole mobility at extremely thin T/sub SOI/, proposing an additional surface roughness scattering mechanism for the thinnest samples due to the perturbation of the conducting band potential stemming from spatial confinement.

A 40nm-gate-length ultra-thin body (UTB) nMOSFET is demonstrated. A self-aligned thin body SOI device has previously been proposed for suppressing the short channel effect. UTB structure can eliminate the punchthrough path between source and drain and provide a more evolutionary alternative to the double-gate MOSFET for deep-sub-tenth micron technology. The advantage of using UTB is illustrated through device simulation (with the aid of Silvaco ATLAS) using simple doping profiles for the body and S/D (simple Gaussian).

The threshold voltage shift caused by quantum confinement in ultra-thin body devices (UTB) is observed experimentally. An analytical model is proposed and shows a good agreement with the experimental data of both PMOSFET and NMOSFET. It predicts a larger threshold voltage shift for a lighter body-doping, which is opposite to the trend in the bulk device. This threshold voltage shift must be taken into account in the design of UTB devices, including the double gate MOSFET.

Ultra-thin body (UTB) MOSFETs with body thickness down to 4 nm and LPCVD selectively deposited Ge raised source and drain (S/D) are demonstrated for the first time. Devices with gate length down to 30 nm show excellent short-channel behavior. Mobility enhancement and threshold-voltage shift due to the quantum confinement of inversion charge by the ultra-thin body are investigated.