415 results on '"Thijs, S."'
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102. Low-power 5 GHz LNA and VOC in 90 nm RF CMOS
103. Current limitation of the THD2 bench: the scatter issue
104. Exploring limits for data registration in the context of PROCARE, a quality improvement project on rectal cancer.
105. Cadmium-induced and trans-generational changes in the cultivable and total seed endophytic community of Arabidopsis thaliana.
106. Atrial trans-septal thrombus in massive pulmonary embolism salvaged by prolonged extracorporeal life support after thrombo-embolectomy. A bridge to right-sided cardiovascular adaptation
107. Unexpected failure during HBM ESD stress in nanometer-scale nLDMOS-SCR devices
108. Charged device model (CDM) ESD challenges for laterally diffused nMOS (nLDMOS) silicon controlled rectifier (SCR) devices for high-voltage applications in standard low-voltage CMOS technology
109. ESD protection for wideband RF CMOS LNAs
110. Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs
111. ESD On-Wafer Characterization: Is TLP Still the Right Measurement Tool?
112. Low-cost feedback-enabled LNAs in 45nm CMOS
113. Mechanical response of electrostatic actuators under ESD stress
114. 50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS
115. Impact of Strain on ESD Robustness of FinFET Devices
116. Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications
117. Perspective of RF design in future planar and FinFET CMOS
118. Reliability issues in MuGFET nanodevices
119. Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies
120. T-diodes - a novel plug-and-play wideband RF circuit ESD protection methodology
121. Calibrated wafer-level HBM measurements for quasi-static and transient device analysis
122. Voltage overshoot study in 20V DeMOS-SCR devices
123. Characterization and modeling of diodes in Sub-45 nm CMOS technologies under HBM stress conditions
124. Understanding the optimization of sub-45nm FinFET devices for ESD applications
125. ESD protection for sub-45 nm MugFET technology
126. A 5 kV HBM transformer-based ESD protected 5-6 GHz LNA
127. Implementation of 6kV ESD Protection for a 17GHz LNA in 130nm SiGeC BiCMOS
128. Implementation of plug-and-play ESD protection in 5.5GHz 90nm RF CMOS LNAs—Concepts, constraints and solutions
129. A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS
130. Multilevel Transmission Line Pulse (MTLP) tester
131. Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies
132. ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions
133. Modeling and simulation for ESD protection circuit design and optimization
134. Mixed-mode simulations for power-on ESD analysis.
135. ESD protection in finfet technologies.
136. HBM ESD robustness of GaN-on-Si Schottky diodes.
137. A SCR-based ESD protection for MEMS — Merits and challenges.
138. CDM protection for millimeter-wave circuits.
139. On gated diodes for ESD protection in bulk FinFET CMOS technology.
140. Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
141. Advanced ESD power clamp design for SOI FinFET CMOS technology.
142. Behavior of RF MEMS switches under ESD stress.
143. HBM parameter extraction and Transient Safe Operating Area.
144. Improving the ESD self-protection capability of integrated power NLDMOS arrays.
145. SCCF — System to component level correlation factor.
146. Next generation bulk FinFET devices and their benefits for ESD robustness.
147. Electrical and thermal scaling trends for SOI FinFET ESD design.
148. Calibration of very fast TLP transients.
149. A study of breakdown mechanisms in electrostatic actuators using mechanical response under EOS-ESD stress.
150. CDM and HBM analysis of ESD protected 60 GHz power amplifier in 45 nm low-power digital CMOS.
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