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The solid-phase epitaxial regrowth (SPER) junction technologies focusing on high-performance device applications have been investigated. It is found that poly-depletion during SPER and subsequent sidewall (SW) formation with disposable sidewall (DSW) flow was significant but it could be effectively suppressed by applying low-temperature SW process. Junction leakage current was also decreased by optimizing the location of the region of end-of-range (EOR) defects. We have also demonstrated that gate-extension overlap length can be controlled by tilted extension implantation. Moreover, we obtained drive currents of 650/350 A/m at I off = 100 nA/m for both N- and PFET, respectively, with excellent PFET's roll-off characteristics. Although, SPER doesn't outperform conventional sRTA at this point, there is a room for optimization and further SPER specific profile optimization will boost the performance. Therfore, this diffusion-less junction technology with extremely low thermal budget is very promising for further scaling of CMOSFETs

We directly evaluated the carrier profile in an operating sub-30-nm n-MOSFET for the first time. The revealed channel profile, including the halo implant covered by the depletion layer, was utilized to increase the n-MOSFET current to 870 muA/mum Idsat at 100 nA/mum Ioff for Vdd = 1 V at Lpoly = 26 nm

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

We report the advantage of the decaborane (B 10 H x +) ion implantation for sub-40-nm-gate-length PMOSFETs compared with conventional boron monomer ion implantation into pre-amorphized layer. PMOSFETs with decaborane ion implantation have a 5% higher on-current than those with boron monomer into pre-amorphized layer. In addition, the threshold voltage fluctuation of the PMOSFETs is also smaller. This high performance of the PMOSFETs is caused by high carrier activation of the decaborane ion implanted layer. We speculated that the high carrier activation results from the surface amorphous layer and undamaged crystal substrate with smooth amorphous/crystal interface due to the cracking of decaborane.

Recently, boron cluster implantation (i.e. decaborane: B10Hx+) is regarded as a promising technology for the formation of P‐type Ultra Shallow Junction (USJ) because of the equivalent high beam current with less beam divergence compared to the conventional B+ or BF2+ implantation. Also as‐implanted and after‐annealing characteristics are different due to the appearance of self‐amorphized layer by the cluster ion bombardment, which suppresses the channeling and enhances the boron activation. However, it is anticipated that the properties caused by this amorphous layer will vary with different implantation conditions or a presence of Pre Amorphization Implantation (PAI) process, which should be understood well to maintain a good process control. From this point of view, we have measured the decaborane implantation characteristics by a couple of different related conditions, for instance, the beam energy and current. Sheet resistance vs junction depth (Rs‐Xj) are also evaluated in different annealing methods...

The x-ray interference technique has been applied to evaluate the structural changes of high temperature grown chemical vapor deposited (CVD) SiO2 film under several post annealing conditions. In annealing above 800 °C in O2 ambient, a thermal oxide growth has been found at the CVD SiO2/Si interface, and its precise thicknesses have been determined. The estimated diffusion coefficient of the oxidant in CVD film was about three times larger compared to that of thermal oxide. A threshold voltage shift in the oxide was found to strongly correlate to the thickness of the thermal oxide rather than to thermal modifications of the CVD SiO2 itself.

The effects of shallow-trench isolation (STI) on the carrier profile of the extension region in sub-50-nm n-MOSFET were directly measured for the first time. The extension overlap length drastically decreased by 3 run within a distance from STI (Y) of 50 nm. In contrast, the channel concentration gradually increased within Y of 100 nm. The STI effect was also measured for transistors with a gate width of less than 130 nm in 6T-SRAM cell. Reduction of the STI effect by nitrogen co-implant suppressed sub-threshold leakage current by up to an order of magnitude and decreased fluctuation in the threshold voltage by 8 %.

We propose new methods to control the work function (WF) of nickel-fully-silicided (Ni-FUSI) gates. We clarified the amounts of segregated dopants, the status at the dielectric surface, and the composition of NiSi to determine the WF of the gates. We demonstrated the segregation mechanism for n- and p-type dopants during the silicidation processes. The amount of dopants used is effective for achieving wide-range WF. Nitridation of the gate oxide surface impacts both the WF of p-type gates and the oxide reliability. The Ni content of NiSi also changes the WF. These methods can be used to simultaneously control the WFs. Based on these three origins, we should be able to achieve wide-range WF differences (0.91 eV), suitable for use in 45-nm node CMOS devices.

We directly evaluated the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-FETs. Using scanning tunneling microscopy, we clearly observed that the roughness of the extension edges induced by the gate LER strongly depended on the implanted dose, pockets, and co-implantations. Impurity diffusion suppressed by a nitrogen (N) co-implant enhanced the roughness of the extension edges, which caused fluctuation in the device performance. We verified the expected impact of the N co-implant on the electrical performance of the n-FETs.

The calculation method of dynamics behavior on automobile engine is getting more important as computer-aided engineering technique to design optimized mechanisms and structures for lighter weight, lower mechanical friction and lower noise. Engine system consists of deformable moving components and several kinds of mechanical joints, such as an oil lubricated bearing. Dynamics problem includes various kinds of noise and vibration phenomena in wide frequency range. Therefore, it is crucial to analyze precisely the coupling behavior between rigid motion and elastic deformation of moving components considering nonlinear dynamic effect of mechanical joint. In this study, we formulated equations of motion for the flexible multibody dynamics system and developed a computer software specialized for internal combustion engines. In the formulation, both rigid motion and elastic deformation are simply expressed by eigen modes on a local observer frame in order to calculate efficiently many deformation modes up to higher frequency range. In addition, several kinds of force elements are formulated to express the nonlinear forces of mechanical joints and the boundary conditions. The developed program has been verified by the experiments under running condition and applied to the real engine design.Copyright © 2005 by ASME

In this paper, the decaborane molecular ion implantation for formation of an ultra-shallow junction of sub-40-nm PMOSFETs is investigated, and its high-performance are demonstrated. B/sub 10/H/sub x//sup +/ implantation can form a shallow and steep USJ with low resistivity and can precisely control the beam without blow-up and energy contamination, compared with the B/sup +/ monomer implantation. PMOSFETs using B/sub 10/H/sub x//sup +/ implantation for source/drain extensions achieve 6-nm shorter Vth roll-off characteristic without degradation of I/sub on/-I/sub off/ characteristic. Therefore, CV/I values can be improved by over 10%. In addition, the precisely controllable and well-collimated beam results occur alongside the Vth fluctuation suppression. The average improvement of Vth fluctuations among extensive gate length (35 to 200 nm) is 14%.

We conclude that fluorine implantation in the extension region (F-tub) makes the Vth roll-off characteristic dramatically improve without degrading the drive current. Using scanning tunneling microscopy (STM) for two-dimensional (2D) carrier profiling, we directly confirmed that such an improvement of the device performance was induced by the reduction of the overlap length and the steep lateral abruptness on the nanometer scale.

Demonstrated the high-performance and high-reliability of ultra-thin poly-Si-gated SiN/HfO/sub 2//SiON high-k stack dielectrics. A SiN layer deposited on HfO/sub 2/ is shown to be indispensable to the suppression of the reaction of poly-Si and HfO/sub 2/, resulting in high thermal stability (1050/spl deg/C). This thermally stable SiN/HfO/sub 2//SiON structure can achieve an ultrathin oxide thickness of T/sub eff//sup inv/ (effective oxide thickness measured in strong inversion region) for 1.7 nm, which is less than 1 nm for EOT. A low leakage current of 5 to 6 orders of magnitude lower than that of SiO/sub 2/ was observed. In addition, this thermal stability can lead to high reliability, which includes TDDB and hot electron integrity.

We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO/sub 2/ gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). A conventional CMOS process was used with high-temperature S/D anneal of /spl ges/1000/spl deg/C, cobalt-silicide and pocket implants. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.

We investigated the effects of fluorine on boron diffusion in thin silicon oxides used for metal‐oxide‐semiconductor structures, including silicon dioxide and oxynitride. We used secondary ion mass spectroscopy to measure the boron penetration depth from p+‐polycrystalline silicon to the silicon substrate through the silicon oxides for various fluorine doses. We compared experimental and simulated results and determined the boron diffusion coefficients in the silicon oxides. The diffusion coefficients have an Arrhenius relationship for each fluorine dose. The diffusion coefficients at a fluorine dose of 1×1016 cm−2 were 30 times larger than with no fluorine dose, and at a fluorine dose of 1×1015 cm−2, diffusion coefficients were 5 times larger. With oxynitride, fluorine has the same enhancing effect. With no fluorine, the diffusion coefficients were independent of oxide thickness. When fluorine is implanted into polycrystalline silicon, especially with a high dose, the diffusion coefficient is larger for ...

We report on the nMISFETs (n-type metal-insulator-semiconductor field effect transistors) characteristics for the atomic layer chemical vapor deposition (ALCVD) HfO/sub 2/ gate stack and the behavior of the HfO/sub 2/ layer during annealing on various oxides.

We studied the uniformity of native oxide formed on Si(001) surfaces during wet chemical cleaning. Uniformity was determined by surface morphology at the initial stage of photoexcited fluorine etching. Since photoexcited fluorine etches Si 40 times faster than it etches Si oxide, it highlights Si native oxides on a Si surface making them observable by scanning tunneling microscopy or atomic force microscopy. Boiling in a HCl‐H2O2‐H2O (1:1:4) solution formed 30–70‐nm islands of oxides. The regions between the islands were not oxidized. Boiling in NH4OH‐H2O2‐H2O (1:1.4:4) also formed oxide islands 30–70 nm in diameter, but the interisland regions were slightly oxidized. Boiling in a HNO3 solution resulted in a native oxide with pinholes at a density of 5×109 cm−2

The diffusivity of boron in gate SiO2 increases with the concentration of boron in the polysilicon gates. A model is described that can explain both the thickness and annealing-time dependencies of the boron penetration in p-channel metal-oxide-semiconductor devices.

This letter discusses the reaction between (001) oriented Si surfaces and photoexcited fluorine gas resulting in the removal of the native Si oxide. For an F2/Ar gas system, the bulk Si was etched in areas where the native Si oxide had been completely removed. However, by using an F2/H2 gas system, only the native Si oxide was removed. We used this method to remove the native Si oxide in Si epitaxial growth. A high‐quality single‐crystal Si film surface was obtained up to a maximum temperature of 600 °C through this Si growth process. We also characterized the etching of a thermal oxide, silicon nitride, and silicon carbide.

This paper deals with the formulation that can analyze vibration noise problems practically in the flexible multibody systems. Many kinds of formulations have been proposed on the flexible multibody systems so far. They are categorized into several groups according to their purposes and coordinate systems. The floating frame of reference formulation is at present the most popular method for general purpose simulations among them. The formulation uses Cartesian coordinates for the position of a body, Euler angles or Euler parameters for the orientations, and modal coordinates for the elastic degrees of freedom. The equations of motion with these different kinds of coordinates are complicated because of coupling between rigid body motion and elastic vibration. On the other hand, the linear theory of elasto-dynamics appears to be simple and could be practical for some limited uses. But it neglects the effect of the elastic deformation on the rigid body motion. In many cases, the effect is significant and essential. In this paper, we propose a new formulation with rigid body modes and a local observer frame (LOF) for large amplitude rigid body motion, and with elastic modes for small amplitude elastic vibration. The LOF is updated properly to compensate the gap between rigid body motion and the LOF motion. The new formulation makes the coupling terms as simple as possible without any loss of the effect of the elastic deformation on the rigid body motion and gives the uniform description in each modal coordinate.

We measured the band discontinuity of the β-SiC/Si heterojunction by photoemission to determine its application to Si-heterojunction bipolar transistors. We measured the valence band discontinuity, Δ E v , as 0.54±0.15 eV. We calculated the conduction band discontinuity, Δ E c , as 0.54 eV. The band line-up was determined using these values of Δ E v and Δ E c when the heterojunction of n-type β-SiC/p-type Si was formed. As a result, the holes in Si feel a potential barrier about 1 eV higher than the electrons in the n-type β-SiC feel at the heterojunction. This band line-up is attractive for Si-HBT's because the holes in the Si base reverse-injected into the SiC emitter are negligible, resulting in higher current gain.

Nitrided-oxide gate dielectrics have been proposed to suppress boron penetration in deep submicron metal-oxide-semiconductor field effect transistors (MOSFETs). However, few quantitative reports have been released on how nitrided oxides enlarge the permissible thermal budget. We evaluated the diffusivities of a nitrided oxide formed by annealing SiO2 in NO gas and demonstrated that this film enables us to use BF2+ for scaled devices. We also proposed a model depicting boron penetration through the nitrided-oxide layer.

Pyrostatins A and B, new inhibitors of N-acetyl-beta-D-glucosaminidase (GlcNAc-ase), have been purified from the culture broth of Streptomyces sp. SA-3501 isolated from a marine environment. They were purified by chromatography on Dowex 50W, silica gel and Capcell Pak C18 (HPLC) followed treatment with active carbon and then isolated as white powders. The structures of pyrostatins A and B were determined by NMR studies to be 4-hydroxy-2-imino-1-methylpyrrolidine-5-carboxylic acid and 2-imino-1-methylpyrrolidine-5-carboxylic acid, respectively. They were competitive with the substrate, and the inhibition constants (Ki) of pyrostatins A and B were 1.7 x 10(-6) M and 2.0 x 10(-6) M respectively.

Benastatins have been isolated as part of a program designed to find microorganism-produced inhibitors of glutathione S-transferase from Streptomyces sp. MI384-DF12. They were purified by chromatography of reversed-phase silica gel, silica gel and Capcell Pak C18 (HPLC) followed by solvent extraction and then isolated as yellow powders. Benastatins A and B have the molecular formulae, C30H28O7 and C30H30O7, respectively. They were competitive with 3, 4-dichloronitrobenzene as the substrate, and the inhibition constants (Ki) of benastatins A and B were 5.0 × 10-6 and 3.7 × 10-6, respectively.

New benzo[a]naphthacenequinone metabolites, designated bequinostatins A and B, have been isolated from the culture broth of the benastatin-producing strain Streptomyces sp. MI384-DF12. The structures of bequinostatins A and B were determined by spectral analyses to be 5,6,8,13-tetrahydro-1,6,7,9,11-pentahydroxy-8,13-dioxo-3- pentylbenzo[a]naphthacene-2-carboxylic acid and 2-decarboxybequinostatin A, respectively. Bequinostatin A showed considerable inhibitory activity against human pi class glutathione S-transferase (GST pi).

Benastatin C, a new member of the benastatins, has been isolated from the culture broth of Streptomyces sp. MI384-DF12. The structure of benastatin C was elucidated as 2-decarboxy-benastatin A by NMR studies. Benastatin D, 2-decarboxybenastatin B, was derived from benastatin B. Benastatins C and D showed inhibitory activities against human pi class glutathione S-transferase (GST pi) and excellent stimulatory activities on the murine lymphocyte blastogenesis in vitro.

The biosynthesis of benastatin A, produced by Streptomyces sp. MI384-DF12, has been studied by feeding experiments with 14C- and 13C-labeled compounds followed by measurement of radioactivity and 13C NMR analysis. The results indicate that benastatin A is derived from two methionine units and fourteen acetate units, condensed in the "head-to-tail" fashion of typical polyketide biosynthesis.

Benastatins A and B, new inhibitors of glutathione S-transferase, have been isolated from the culture broth of Streptomyces sp. MI384-DF12. By X-ray crystallography, benastatin A was determined to be 8,13-dihydro-1,7,9,11-tetrahydroxy-13-dimethyl-8-oxo-3-pentyl- benzo[a]naphthacene-2-carboxylic acid. The structure of benastatin B was elucidated by NMR studies.

Nagstatin, a new inhibitor of N-acetyl-beta-D-glucosaminidase (NAG-ase) was discovered in the fermentation broth of Streptomyces amakusaensis MG846-fF3. It was purified by chromatography on Dowex 50W, Avicel and Sephadex LH-20 followed by the treatment of active carbon and then isolated as colorless powder. Nagstatin has the molecular formula of C12H17N3O6. It is competitive with the substrate, and the inhibition constant (Ki) was 1.7 x 10(-8) M.

Chlorine radicals generated with UV irradiation are effectively used to remove residual metal contaminants after vatious LSI processes. Aluminum, iron, and copper atoms are effectively removed as volatile chloride species from silicon surfaces. The mechanism has been studied using silicon wafers intentionally contaminated with those metal ions. Contaminants are involved in native oxides as metal oxides or hydroxides. Chlorine radicals penetrate the native oxides and attack those oxides or hydroxides vaporizing metal chlorides. The cleaning process is accompanied with slight etching of silicon surfaces to a depth as thin as a few nm. However, this is not essential because the substrate temperature is more important than the etching depth. Alkaline metals are also removed from the surfaces to the level as small as the detection limit of atomic absorption spectroscopy. We believe that those are removed through a lift-off process. The, wixture of fluorine and hydrogen gases removes a native oxide of silicon under UV irradiation. Hydrogen fluoride radicals react with native oxide resulting in hydrogen termination on silicon dangling bonds. These cleaning processes are advantageous for low temperature silicon epitaxy, reliable contact formation, and thin gate oxide growth.

In constructing a surface reaction model of plasma etching, there are many coefficients that must be determined, because there are various species of radical which contribute to surface reactions. In this study, the conventional surface reaction model has been simplified to reduce the number of coefficients. This simplified model was in good agreement with experimental data with a fitting error of ±0.026 nm/s. Furthermore, each term in our model indicates a physically meaningful trend, which shows that our simplification is appropriate for explaining experimental results. The distribution of etching rate was also analyzed using our model to separate ion-enhance and pure-chemical-etching factors across the wafer using only a plasma etching apparatus and a tool for measuring film thickness.

not Available.

We have investigated the effect on the device performance and reliability of incorporating Mg into the HfSiON gate dielectrics. Mg incorporation is effective for reducing the threshold voltage and gate leakage current in n-type metal–oxide–semiconductor field effect transistor. On the other hand, it may introduce interface states and degrade the mobility if the Mg atoms come close to the interface between the Si substrate and the gate oxide. Nonetheless, Mg incorporation has great potential for improving reliability, including positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). Its reliability improvement is mainly caused by gate leakage current reduction and trap density suppression as an result of Mg incorporation.

We have clarified the effects of activation annealing temperature on the negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime improvement of HfSiON/TiN gate stack p-type metal–oxide–semiconductor field effect transistors. Higher-temperature annealing is effective for the improvement in NBTI and TDDB lifetime. This is due to the Si substrate oxidation occuring during the high-temperature annealing, resulting in interface defect state reduction. Annealing is also effective for reducing threshold voltage with consequential improvement in device performance.

A new dual-metal-gate technology that includes a metal-inserted full silicide stack (MIFS) is proposed for scaled high-k complementary metal–oxide–semiconductor (CMOS) processes. A single Ni-rich full silicide (FUSI) layer is used for both types of MOS field-effect transistors (MOSFETs) without the need to form two different FUSI phases, while a thin-TiN layer is selectively inserted between Ni-rich FUSI and a high-k material only for n-channel MOSFETs (nMOSFETs). A low effective work function (m,eff) of 4.45 eV can be obtained in HfSiON nMOSFETs using MIFS gate electrodes whose structure is Ni-rich FUSI/thin TiN (2 nm). m,eff of Ni-rich FUSI gate electrodes fabricated after the selective removal of TiN from HfSiON is as high as 4.8 eV in HfSiON p-channel MOSFETs (pMOSFETs), which is similar to that obtained for `control' Ni-rich FUSI gate electrodes. Since m,eff remains unchanged with decreasing equivalent oxide thickness (EOT), this dual-metal-gate technology is promising for use in scaled high-k CMOS processes from the viewpoints of m,eff, process compatibility, mobility, and EOT scaling.

We discuss scaling the equivalent oxide thickness (EOT) of Hf-based high-k gate dielectrics by post-deposition annealing (PDA). Thin HfON/SiON gate stacks with EOT=0.57 nm were successfully formed by repeating ultra thin (0.6 nm) HfO2 deposition and high-temperature (950 °C) PDA on a previously formed SiON interfacial layer. Physical and electrical analyses revealed that the reduction in EOT was due to crystallization of HfON to the tetragonal phase which has a higher dielectric constant than the amorphous and other crystalline phases. It was also found that Hf diffusion in the SiON interfacial layer was induced by the high-temperature PDA treatment. This also improved the k-value of the interfacial layer and enabled aggressive scaling even when using a SiO2-based interfacial layer. The electron mobility of the gate stack is higher than those in the previous reports, indicating that a high quality interface is realized using this approach. The reduction in EOT together with the excellent interfacial quality demonstrated in the present study shows that this technique is a promising solution for the 22-nm-node and beyond.