237 results on '"TAOUIL, MOTTAQIALLAH"'
Search Results
102. Memristive devices for computation-in-memory
103. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar
104. A computation-in-memory accelerator based on resistive devices.
105. Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads
106. Memristive devices for computing: Beyond CMOS and beyond von Neumann
107. On the Implementation of Computation-in-Memory Parallel Adder
108. Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing
109. Interconnect networks for resistive computing architectures
110. On the robustness of memristor based logic gates
111. Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier
112. Mitigation of sense amplifier degradation using input switching
113. Non-volatile look-up table based FPGA implementations
114. Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability
115. Parallel matrix multiplication on memristor-based computation-in-memory architecture
116. Read path degradation analysis in SRAM
117. Comparative BTI analysis for various sense amplifier designs
118. Boolean logic gate exploration for memristor crossbar
119. Memory profiling for intra-application data-communication quantification: A survey
120. BTI analysis of SRAM write driver
121. Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic
122. Memristor: the enabler of computation-in-memory architecture for big-data
123. Fast boolean logic mapped on memristor crossbar
124. Interconnect networks for memristor crossbar
125. Computation-in-memory based parallel adder
126. On resistive open defect detection in DRAMs: The charge accumulation effect
127. Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier
128. Integral impact of BTI and voltage temperature variation on SRAM sense amplifier
129. Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching
130. Memrisor Based Computation-in-Memory Architecture for Data-Intensive Applications
131. Testing Open Defects in Memristor-Based Memories
132. Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface
133. Quality versus cost analysis for 3D Stacked ICs
134. Interconnect test for 3D stacked memory-on-logic
135. Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity
136. Exploring test opportunities for memory and interconnects in 3D ICs
137. Computation-in-memory based parallel adder.
138. Memristor based computation-in-memory architecture for data-intensive applications.
139. Using 3D-COSTAR for 2.5D test cost optimization
140. Impact of mid-bond testing in 3D stacked ICs
141. Is TSV-based 3D Integration Suitable for Inter-die Memory Repair?
142. Performance Evaluation for Field Programmable Gate Array-based Bioinformatics Sequence Alignment
143. Interconnect test for 3D stacked memory-on-logic.
144. On optimizing test cost for Wafer-to-Wafer 3D-stacked ICs
145. Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
146. On modeling and optimizing cost in 3D Stacked-ICs
147. Yield Improvement and Test Cost Optimization for 3D Stacked ICs
148. Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
149. How significant will be the test cost share for 3D die-to-wafer stacked-ICs?
150. Stacking order impact on overall 3D die-to-wafer Stacked-IC cost
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.