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The latency insertion method (LIM) is a transient simulation technique for circuits and is based on a finite-difference formulation, like the well-known finite-difference time-domain (FDTD) method for solving Maxwells equations. The LIM, like the FDTD method, is only conditionally stable resulting in an upper bound for the time step of the transient simulation. This bound on the time step is a function of the circuit topology and the circuit element values. It is critical to know this bound analytically for a given circuit. However, stability conditions of the LIM have been proven only for 1-D, infinitely long, distributed uniform RLC circuits, employed in transmission line modeling. For nonuniform circuits, these conditions have been predicted and have been observed experimentally as well but have not been possible to prove using the existing stability analysis techniques. Recently, analytical stability conditions of the LIM for nonuniform RLC circuits have been proven using the Lyapunovs direct method (LDM). However, when a conductance to ground (G) is added to a node of an LC or RLC circuit, the stability conditions cannot be derived using the Lyapunov function proposed. In this brief, analytical stability condition of the LIM is derived for the first time for nonuniform GLC circuits using the LDM with a new Lyapunov function. Index Terms--Conditional stability, finite-difference time-domain (FDTD) method, spectral radius.

A numerical-convolution-based approach has been proposed for the accurate transient simulation of interconnects characterized by band-limited (b.l.) frequency-domain (f.d.) data and terminated by arbitrary equivalent circuits. Propagation delay is enforced in the transient results by obtaining causal impulse responses from b.l.f.d, data, extracting the propagation delays from them, and enforcing the delays in the causal impulse responses. Causal impulse responses are obtained through a new minimum-phase/all-pass decomposition of the frequency data. In this decomposition, a new form for the all-pass component has been proposed that preserves the sign of the original frequency response in the reconstructed response, unlike the prior approaches, leading to an accurate transient result. Arbitrary terminations are conveniently handled by integrating the numerical convolution in a modified nodal analysis (MNA) framework, a framework used by commercial circuit simulators, through a new transient simulation formulation. Numerical results demonstrating the accuracy and capability of the proposed procedure have been presented. Index Terms--Causality, convolution, scattering parameters, signal flow graphs, transient response.

Ensuring the integrity of the power supply in the power distribution networks (PDNs) of a chip is essential for building reliable high-performance chips. To ensure the power integrity, accurate, and memory- and time-efficient simulation approaches for simulating the power-supply noise in the on-chip PDN are essential. In this paper, a finite-difference formulation based on the latency insertion method (LIM) has been employed for simulating the power-supply noise in the on-chip PDN. A new common-mode type equivalent circuit has been proposed. In this equivalent circuit, a capacitance to ideal ground may not be present at all the nodes. Further, the nodes can be capacitively coupled to each other. To avoid inverting a large nonbanded matrix, a small capacitance to ground is added to a node that did not have any capacitance to ground, and a small series inductance is added to any floating capacitor that did not have any series inductance. Approximate closed-form expressions to compute the values of these capacitances to ground and series inductances have been proposed. The accuracy of the LIM-enabled transient simulation and the accuracy of the proposed closed-form expressions have been demonstrated. The memory and time complexity of the simulation for each time step have been shown to be O([N.sub.n]) each, where [N.sub.n] is the number of nodes in the equivalent circuit. Stability condition is derived for the first time for multidimensional inhomogeneous RLC circuit. A upper bound of the time step is derived from the stability condition. Using this bound on the time step, the runtime of the overall transient simulation has been estimated to be approximately proportional to [N.sup.2-2.5.sub.n] for [N.sub.n] in the order of millions. Index Terms--Computational complexity, explicit, floating capacitor, implicit, latency insertion method (LIM), power distribution network (PDN).

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 [micro]m. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material. [DOI: 10.1115/1.2804096]

The fabrication of low-loss transmission line structures with an air dielectric layer is described. The channels are characterized at low frequency (10 and 100 kHz) using capacitance and loss tangent and at high frequency (500 MHz to 10 GHz) using S-parameter measurements. The incorporation of an air gap resulted in structures with effective dielectric constants between 1.5-1.8 and significantly lower loss tangents. The fabrication technique could be used to create more complicated air gap transmission line structures for use in monolithic microwave integrated circuits. Index Terms--Air gaps, dielectric losses, multiprocessor interconnection, transmission lines.

Power/ground planes in electronic packaging can be a major factor for noise coupling. There can be noise coupling not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. Due to the large size of the power/ground planes, it is difficult to analyze them using full-wave simulators. It is known that the finite-difference solution of the Helmholtz equation provides a faster approach with comparable accuracy. For multilayered planes and arbitrary geometries with aperture coupling, we present a multilayered finite-difference method (MFDM). It provides an accurate representation of wrap-around currents, which have not been modeled earlier, for large cutouts. Estimation of the influence of such coupling effects are essential especially for a successful design of mixed-signal systems. This method allows to consider realistic structures, which would be prohibitive to simulate using full-wave simulators. Index Terms--Finite-difference method (FDM), Helmholtz equation, power/ground planes, simultaneous switching noise.

This paper presents the application of a fast and accurate layout-level statistical analysis methodology for the diagnosis of RF circuit layouts with embedded passives in liquid crystalline polymer substrates. The approach is based on layout-segmentation, lumped-element modeling, sensitivity analysis, and extraction of probability density function using convolution methods. The statistical analyses were utilized as a diagnosis tool to estimate distributed design parameter variations and yield of RF circuit layouts for a given measured performance. The results of statistical analysis and diagnosis were compared with measurement results of fabricated filters. Statistical methods were also applied for design space exploration to improve system performance, as well as estimation of yield and diagnosis of faults during batch fabrication. Index Terms--Bandpass filter, liquid crystalline polymer (LCP), parametric yield, RF synthesis, statistical diagnosis.

In this paper, a multilayered on-chip power distribution network consisting of two million passive elements has been modeled using the finite-difference time-domain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately. Index Terms--Chip--package interaction, circuit finite-difference time-domain (FDTD), decoupling capacitor, large chips, on-chip power distribution, power supply noise, wafer level package.

A fast and accurate layout-level synthesis and optimization technique for embedded passive RF components and circuits such as inductors and bandpass filters have been presented. The filters are composed of embedded inductors and capacitors in a multilayer liquid crystalline polymer substrate. The proposed approach is based on a combination of segmented lumped-circuit modeling, nonlinear mapping using polynomial functions, artificial neural network-based methods, and circuit-level optimization. Synthesis and optimization results of inductors for spiral/loop designs based on microstrip and stripline configuration are within 5% of data obtained from electromagnetic (EM) simulations. For RF circuits, the methodology has been verified through synthesis of 2.4- and 5.5-GHz bandpass filters with and without transmission zeros. Scalability has been shown over a range of 2-3 and 4-6 GHz, respectively, with bandwidth variation of 0.5%-3% of center frequency. The synthesized models are within 3%-5% of EM simulation data. Index Terms--Artificial neural networks (ANNs), filter synthesis, inductor optimization, liquid crystalline polymer (LCP), synthesis.

This paper discusses a method for the construction of multiport broadband passive macromodels using frequency data obtained from an electromagnetic simulation or measurements. This data could represent the frequency response of a distributed interconnect system. The macromodels are generated using rational functions by solving an eigenvalue problem. For numerical computation, the macromodels are represented as a summation of rational functions consisting of low-pass, band-pass, high-pass, and all-pass filters. The stability and passivity of the macromodels are enforced through constraints on the poles and residues of rational functions. To enable the construction of broadband macromodels, methods based on band division, selector, subband reordering, subband dilation, and pole replacement have been used. Two test cases that describe the performance of the proposed algorithm, and three test cases that are representative of distributed systems have been analyzed to verify the efficiency of the method. Index Terms--Broadband multiport passive macromodels, circuit simulation, distributed interconnect networks, frequency dependent data, macromodeling, passivity, rational functions.