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A low output resistance and high slew rate class-AB flipped voltage follower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the low output resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as low output resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented.

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier’s specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18- $\mu \text{m}$ CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.

A thermally actuated, single-axis, bidirectional translation stage is designed and constructed. To increase the temperature of the thermal actuator, induction heating is used while air-water-mist cooling is used to decrease the temperature. An automated control strategy comprising PID closed loop control (for heating) and On/Off switching between air and mist control (for cooling) is described. The translation stage of this study produces a displacement range of 100 μm and 200 μm (using 240 W and 480 W power sources) in the presence of preloads up to 1 kN. Dependent on the power source used, the root mean square (rms) controller error at steady-state is within 15 nm (240 W) and 35 nm (480 W). No significant variation in the rms controller error was measured in the presence of the different preloads. Dynamic performance is evaluated from step responses over the full range of the actuator as well closed-loop frequency responses. The non-linear, asymmetric aspects of heating and cooling are discussed. Further observations of the system behavior and the preload effect are presented with discussion covering the slew rate, magnitude of overshoot, and controller settling time.

A four-stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed-forward Gm-stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transconductance stages to form a segment, and linked several segments to form a large multistage amplifier. For example, a two-stage amplifier linked with a three-stage amplifier can realize a five-stage amplifier, two three-stage amplifiers linked can realize a six-stage amplifier. A four-stage amplifier in the form of 2+2 (two stages and two stages) was used as an example to verify this compensation method. The proposed OTA is designed in the 180nm complementary metal oxide semiconductor process. It consists of two parts which ensure the stability and improve the bandwidth performance. The first part is a feed-forward transconductance stage, and the second part is the two-segment transconductance stages with the Miller compensation techniques employed within and between the two segments. Based on the small-signal model, stability analysis and theoretical derivation are performed in theory. On condition of a 2-pF load capacitance, a direct current gain of 109dB and a gain-bandwidth of 240MHz with a phase margin of 50° can be achieved. The proposed design consumes 2.19mW in a 1.8-V supply voltage. The transient simulation indicates that the settling time of the output is 19ns with the settling error being 1%, and the slew rate is 114V/μs.

This article reviews electromagnetic bearings with power electronic control for high-speed machinery, which are termed active magnetic bearings (AMBs). AMB is a contactless-type bearing, which uses magnetic force to support the rotor. This is suitable for high-speed applications, harsh operating conditions, and also clean environments. However, the AMB has nonlinear characteristics and is inherently unstable. Due to recent advancements in fast-switching power devices, high-switching-frequency power converters, high-bandwidth current control, nonlinear control strategies, advanced digital controllers, and sensors, AMBs have become promising for high-speed aerospace, industrial, and energy applications. This article contains a brief tutorial on the AMB, covering its operating principle, system-level block diagram, magnetic-circuit-based analysis, dynamic load due to rotor mass unbalance, load capacity, force slew rate, and response to large force disturbance. Furthermore, a design example of an eight-pole AMB with four excitation coils is presented to achieve a load capacity of 180 N. A preliminary design, based on magnetic circuit analysis, is seen to fall short in terms of load capacity. Iterative changes to the AMB dimensions achieve the required load capacity, but the characteristics are still nonlinear. Finite-element analyses bring out the effects of magnetic saturation on load capacity, linearity between force and current, force slew rate, and relationships between maximum force generated and AMB dimensions. An improved design procedure is presented to achieve both desired load capacity and linear characteristics, while balancing the compactness requirement. The improved design also achieves the desired slew rate besides faster response and improved stability.

A proposed ultra-high slew rate current recycling folded cascode operational transconductance amplifier (OTA) working in the subthreshold region is presented. By employing adaptive biasing and the ...

A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The design...

This paper introduces two high-performance single-stage bulk-driven (BD) operational transconductance amplifiers (OTA) in weak-inversion with rail-to-rail input and output voltage ranges suited for the excessively low-voltage of 0.5 V supply. The strategy depends on adopting a modified bulk-driven non-tailed input core to achieve high input core transconductance with a minimum power supply and an enhanced input common-mode range. Moreover, a partial positive feedback loop provides an overall improved DC gain and effective transconductance further. The input core of OTA1, named composite class-AB OTA, comprises two combined non-tailed differential pairs as composite differential pairs. The proposed OTA2, named composite super class-AB BD-OTA, exploits a matched bulk-input Flipped voltage follower (FVF) pair to adaptively bias the input core used in the composite class-AB BD OTA. As a result, a significant increase in large-signal input current to the output side due to super class-AB behavior improves the slew rate. The post-layout simulation results using the Cadence Spectre simulator with UMC 0.18 µm process technology confirm that the proposed OTAs have improved small-signal and large-signal performances over the conventional OTA driving a high capacitive load of 5 nF. The proposed composite class-AB and super class-AB BD OTA deliver 2.29 times, and 3.77 times open-loop DC gain, 10.6 times, and 117 times unity-gain bandwidth with 2 times, and 12.03 times slew rate at the expense of almost 0.52 times and 1.21 times power consumed over conventional counterpart, respectively.

Objectives: To present a power efficient Universal Biquad Operational Transconductance Amplifier circuit. Methods: OTA (operational transconductance amplifier) based Biquad filter is analyzed using three different simulated tools three different tools (CADENCE, XILINX, ORCAD and MATLAB tools) are used for designing the circuit. The 0.18mm CMOS technique is used using the Cadence tool for plan and reproduction. The same circuit has been implemented on ORCAD tool as well as Xilinx tool. Findings: The proposed Biquad filter improves the frequency response, power dissipation and provides vary of the KHN biquadratic filter circuits it uses minimum numbers of Operational Transconductance phenomenon Amplifier (OTA) to realize an equivalent. The assorted parameters specifically Center frequency, dcgain, Bandwidth, Power Dissipation and Quality issue are all electronically tunable. OTA based Biquad filter is simulated in CADENCE Virtuoso tool. Opamp-RC Biquad filter offers a bandwidth of 425 kHz, pass band gain of zero DB, whereas Gm-C measuring system based mostly filter offers 85MHz, passband gain of zero DB. Over-all power dissipation of the Biquad filter is 4.3mW with 1.8V DC Supply has basing current of 50mA with gracefully voltage 2.5v. by keeping the supply voltage, bias current and load capacitor as 2.5V, 50mA and 10pFrespectively, it has been seen that the power is reduced using the CADENCE virtuoso tool. Novelty : This study presents a Universal Biquadratic filter having less power dissipation. The circuit was optimized for gain, GBP, slew rate, areas, voltage offset, phase margin, power area etc. compared to all the previous filter circuits (OTA GMC filters, OTA type-C filters) designed with the help of OTA. Keywords: OTA; CMOS; CADENCE Virtuoso; Static Power; Dynamic Power; MOSFET

Driving solutions for power semiconductor devices are experiencing new challenges since the emerging wide bandgap power devices, such as silicon carbide (SiC), with superior performance become commercially available. Generally, high switching speed is desired due to the lower switching loss, yet high $dv/dt$ and $di/dt$ can result in elevated electromagnetic interference (EMI) emission, false-triggering, and other detrimental effects during switching transients. Active gate drivers (AGDs) have been proposed to balance the switching losses and the switching speed of each switching transient. The review of the in-existence AGD methodologies for SiC devices has not been reported yet. This review starts with the essence of the slew rate control and its significance. Then, a comprehensive review categorizing the state-of-the-art AGD methodologies is presented. It is followed by a summary of the AGDs control and timing strategies. In this work, using AGD to reduce the EMI noise of a 10-kV SiC MOSFET system is reported. This work also highlights other capabilities of AGDs, including reliability enhancement of power devices and rebalancing the mismatched electrical parameters of parallel- and series-connected devices. These application scenarios of AGDs are validated via simulation and experimental results.

Non-destructive measurements of nA beam currents in particle beam storage rings by detecting the azimuthal magnetic field generated by moving charged particles with a Cryogenic Current Comparator (CCC) are well established. The detection of beam currents with small amplitudes with a CCC in a storage ring demands a high slew rate which is caused by the rapid change of the beam current exceeding the operational limit of the SQUID in flux-locked loop mode. Previous solutions to increase the slew rate used a LCR first-order low-pass filter were a small resistor, unfortunately, dominated the current noise of the CCC. In this work we present a novel take by adding a second resonator into the CCC which in turn allows for higher resistances of the LCR low-pass filter and therefore lower thermal current noise. A second challenge connected with this CCC approach is the residual magnetization of the highly permeable magnetic core and the resulting shielding currents in the superconducting circuits of the CCC. The timing of a storage ring in the range of minutes opens a way to reduce these DC currents using a LR high-pass filter. Using serial sub-micro ohm resistors, time constants in the hour range can be achieved to improve the stability and performance of the CCC system.

This brief presents a more detailed model for the slewing behavior of self-biased ring amplifiers and outlines the factors which affect the large signal operation. A set of analytical expressions derived for the self-biased ring amplifier are presented which are valid for a larger portion of a design space than prior expressions. The equations presented are well matched with simulation results and the accuracy of the derived equations is reported. Finally, the paper examines the proposed equations and simulation results to provide insight about design parameter dependence.

A high-gain two-stage class A–AB operational amplifier (Op-Amp) is presented. A boosted recycling folded cascode with more than four cascode transistors compared to the conventional structure is used in the first stage of the proposed Op-Amp. The AB class output stage is constructed using a quasi-floating-gate MOSFET and a bootstrap capacitor. Indirect feedback compensation is utilized, leading to smaller compensation capacitors and, therefore, higher slew rate (SR) and bandwidth. The proposed circuit is simulated by using a 180-nm 1.8-V CMOS process standard technology. Simulation results with a 50-pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 121.6 dB, 45.3 MHz, 66.2 V/μS, 29.7 nS, and 65.6°, respectively. The PM and SR reduce to 65.6° and 51.9 V/μS, respectively, when driving a 100-pF capacitance load. The proposed Op-Amp consumes 1.59 mW @ 1.8 V, which makes it a high-current-efficiency two-stage amplifier.

The high peak current withstand capability of thyristors makes them extremely suitable for pulsed power applications. Silicon carbide (SiC) thyristors provide significant efficiency advantages compared with their silicon counterparts due to their very fast switching transitions. This article presents the development and characteristics of 3 kV SiC thyristors. A novel current-source gate driver is proposed to enhance their switching speed and, hence, maximize their benefits in pulsed power applications. The proposed driver provides a very high gate current slew rate while limiting the peak of the current pulse. The higher gate current slew rate achieves faster and, thus, more efficient device switching transition. Gate driver circuit description, variant topologies, and experimental results for a 3 kV SiC thyristor for a pulsed power application are presented to verify the proposed concepts.

A study of the reset transient of charge-sensitive amplifiers operating with a pulsed switch in parallel to the feedback capacitance is presented. Analytical models have been developed for amplifiers in both linear and slew rate regimes during the reset phase. The models predict the time interval required to reset the amplifier that, in most cases, significantly differs by the simple discharge of the feedback capacitance through the switch resistance and strongly depends on the open-loop gain and bandwidth of the core amplifier and on the input capacitance. The models also quantitatively predict spurious voltage transients at the preamplifier’s input and possible ringings at the output, as a function of the main general parameters of the circuit. A case application study of the presented model is proposed for low-capacitance detectors, such as semiconductor drift detectors or small pixel detectors.

In this paper, operational amplifier circuit is designed using model parameters of high-k FinFET in 22nm technology. The conventional design expressions for MOSFET based OPAMP design are fine tuned to design FinFET based OPAMP. The OPAMP design is suitable for use as sub circuit in ADC design as it supports low voltage, high speed and low power dissipation. The transistor geometries are identified so as to achieve high performance and energy efficient OPAMP. Schematic capture is carried out using Cadence tool. From the simulation studies, the designed OPAMP has a unity gain bandwidth of 100 GHz and slew rate is equal to 1V/μS. The maximum power dissipation of differential amplifier circuit is 800nW and hence suitable for all low power analog and digital circuits.

Purpose This paper aims to investigate the attitude control pointing improvement for a small satellite with control moment gyroscopes (CMGs) using the active force control (AFC) method. Design/methodology/approach The AFC method is developed with its governing equations and integrated into the conventional proportional-derivative (PD) controller of a closed-loop satellite attitude control system. Two numerical simulations of an identical attitude control mission namely the PD controller and the PD+AFC controller were carried out using the MATLAB®-SimulinkTM software and their attitude control performances were demonstrated accordingly. Findings Having the PD+AFC controller, the attitude maneuver can be completed within the desired slew rate, which is about 2.14 degree/s and the attitude pointing accuracies for the roll, pitch and yaw angles have improved significantly by more than 85% in comparison with the PD controller alone. Moreover, the implementation of the AFC into the conventional PD controller does not cause significant difference on the physical structure of the four single gimbal CMGs (4-SGCMGs). Practical implications To achieve a precise attitude pointing mission, the AFC method can be applied directly to the existing conventional PD attitude control system of a CMG-based satellite. In this case, the AFC is indeed the backbone for the satellite attitude performance improvement. Originality/value The present study demonstrates that the attitude pointing of a small satellite with CMGs is improved through the implementation of the AFC scheme into the PD controller.

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a $0.35\mu \text{m}$ CMOS process and occupies an active chip area of $456\times 278 \mu \text{m}^{\mathbf {2}}$ . Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a $0.054\mu \text{s}$ response time. The power-supply rejection (PSR) at 100kHz is −75.6dB.

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (D...

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer’s first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm $$\times$$ 59 μm).

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 $\mu \text{m}$ HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of $\text{d}{V} _{\mathrm {SSF}}$ /dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM1 and FoM2 of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.