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This investigation examines the physical mechanisms that can increase the variability of both p-n junctions and silicon–germanium heterojunction bipolar transistors (SiGe HBTs) at cryogenic temperatures. The important operative mechanisms responsible for device parameter variability include bandgap narrowing due to heavy doping, mechanical stress, and the Ge profile. The impact of direct tunneling on cryogenic parameter variability in SiGe HBTs is also examined. Measurement results are compared with TCAD simulations to provide additional insights, and possible mitigation methods are discussed. [ABSTRACT FROM AUTHOR]

A W-band balanced frequency doubler with an optimized harmonic termination and neutralization technique is proposed for high output power and high conversion efficiency in a 90-nm SiGe process. The proposed design demonstrates a peak conversion gain of 0.7 dB and the maximum output power higher than 4 dBm at an output frequency of 84 GHz with the conversion efficiency of 14%. [ABSTRACT FROM AUTHOR]

This letter presents single-ended and differential D-band power amplifiers (PAs) in 55nm SiGe BiCMOS technology. The proposed PAs exploit the remarkable features of common-base stages for rising the power efficiency, i.e., 1) higher breakdown voltage; 2) sharp compression profile due to the enhanced linearity; and 3) supply current adapted to the signal amplitude by means of current clamping. A four-stage single-ended PA proves P1,dB = 16.8 dBm with PSAT = 17.6 dBm at 135 GHz. The PAEs at P1,dB and P1,dB-6,dB are 17.1% and 8.5%, respectively. With a differential PA, the linear output power is increased to P1,dB = 18.5 dBm with PSAT = 19.3 dBm at 135 GHz. The PAEs at P1,dB and P1,dB-6,dB are 12.6% and 6.7%, respectively. The PAs demonstrate 3 × PAE improvement in the linear region against the state of the art. [ABSTRACT FROM AUTHOR]

Dielectrically-modulated Tunneling-Field-Effect-Transistor (TFET) based biosensor has been given a major deal of interest since it promises a high sensitivity but low current during the detection process. This paper has proposed a novel biosensor based on the TFET configuration to effectively increase both the sensitivity and current while conjugating the biomolecules. The proposed biosensor is configured by SiGe source along with the n+ doped pocket between the source and the channel region. Indeed, the material and structural engineering lending to modification of the bandgap and tunneling length have been introduced as the effective solutions that will help the biosensor detecting the biomolecule samples by high sensitivity which is immune to the possible noise. The proposed structure has been compared with a traditional biosensor and also a recently proposed biosensor including only a doped pocket inside the channel. Regarding the definition of the sensitivity of biosensor in term of the drain current, after performing theoretical analysis and making the comparisons, the proposed biosensor got a high sensitivity (76) and raised current (1.8E- $10~\mu \text{A} / \mu \text{m}$) during the hybridization of the biomolecule as compared to other structures. Also, practical issues in the cases of the TAT Trap-Assisted Tunneling (TAT) component and partial fill factor revealed that the proposed biosensor can be good selection. Biotin-Streptavidin binding as a specific biomolecule has been studied in order to show the power of the suggested biosensor in the detection. All the obtained results revealed that the proposed structure in this paper can be introduced as a suitable and excellent replacement for other counterparts. [ABSTRACT FROM AUTHOR]

In this study, we discuss Si-SiGe etch characteristics as well as SiGe surface composition modification. It is required to etch Si and SiGe simultaneously for Si/SiGe dual channel Fin-FETs. Therefore, etch control of these two materials is desired. However, not only halogen chemistries but also physical sputtering etch SiGe selective to Si. We found that Si can be etched faster than SiGe by hydrogen plasma. Our analysis presents that hydrogen bonds selectively with Si rather than Ge, which leads to Si selective removal. As for SiGe surface modification, realizing Si-rich surface in SiGe is known to improve SiGe/high-k interface quality in advanced CMOS. It is also presented that the low-temperature hydrogen plasma induces Si-surface segregation (i.e., Si-rich surface) in SiGe, which is confined near the top-surface region. We proposed this may be caused by ion-energy-driven surface reaction. Our study also shows that Ge/Si ratio increases with plasma exposure time, which has correlation with surface roughness. Using the hydrogen plasma and conventional halogen plasma, we successfully demonstrate to etch Si/SiGe dual channel fins with depth and CD value control.

The stacked nanowire field-effect transistor is an important option for future generations of CMOS technology. It features superior electrostatic control due to all-around gates while maintaining sufficient drive currents by stacking multiple channels. One of the challenges for manufacturing such devices is the fabrication of inner spacers between the nanowires in order to control the parasitic capacitances. A previously demonstrated approach for inner spacer fabrication uses the wet chemical etching of a sacrificial silicon-germanium layer between the silicon channels in order to prepare a cavity into which the spacer material is deposited. The etch rate of the sacrificial layer depends on the germanium content. Thus, the variations of the Si-Ge composition across the wafer lead to the corresponding geometrical variations of the transistor structures. This work traces the effect of Si-Ge composition variations via the inner spacer geometry on the key electrical properties of the devices using the numerical simulations. A significant impact on on-current and capacitances was determined. It could be shown that the dependence of the current on the Si-Ge composition is closely related to the doping profile in the nanowires. These results improve the understanding of sources of variability in nanowire transistors and, hence, may help to improve device reproducibility.

In this article, we present and evaluate compact static thermal model parameter extraction techniques for modern silicon germanium heterojunction bipolar transistors (SiGe HBTs). We found that the model implementation of thermal resistance (Rth) based on only junction temperature is implicit requiring time-consuming iterative procedure which may lead to potential instabilities. Dedicated extraction techniques are proposed for obtaining compact model-specific Rth and its temperature coefficient. The proposed method is primarily validated on SPICE generated synthetic data. Next in order to showcase a compact model-independent verification, we also test the method using detailed thermal simulation from TCAD. Finally, we apply our extraction technique on measured data from fabricated transistors. The results are benchmarked to already obtained nominal Rth values from the same device family. [ABSTRACT FROM AUTHOR]

This article focuses on the reduction of the self-heating (SH) effect in an advanced SiGe hetero-junction bipolar transistor (HBT) considering the Peltier effect. Bismuth Telluride is the working material for most Peltier cooling devices and thermoelectric (TE) generators. This is because Bi2Te3 has the highest TE figure of merit (ZT), of any material around room temperature. An electro-thermal model is performed using the COMSOL multiphysics software. Accurate direct current (dc) and radio frequency (RF) electrical simulations, as well as the extraction of the device static and dynamic thermal parameters are performed on the proposed structure. The current gain (β), the cutoff frequencies (fmax), and the maximum network temperature Tmax have been considered. We have extracted these parameters by taking into account the phenomenon of the SH which occurs in this device. We then have integrated around the structure, a cooling system considering elements with “Peltier effect.” So, in this case, the electrothermal model is essentially based on the Peltier effect. It allows generating a potential Δ V difference from a temperature Δ T gradient in the considered structure. Thus, we analyze carefully the heat distribution and the electrical potential on the surface of the component. By using this cooling method, we can observe clearly a decrease in the maximum temperature (Tmax) of the HBT SiGe due to the SH phenomenon: from Tmax = 467 K to Tmax = 330 K. The proposed method shows a sensible improvement of dc and RF figures considering the thermal impact of Peltier effect upon the transistor. [ABSTRACT FROM AUTHOR]

We report a new 128 GSa/s SiGe digital to analog converter (DAC) having 8 bit physical resolution and 24 GHz 3-dB bandwidth and present its architecture and the results on fundamental converter assessment. We further integrated the DAC into a coherent optical transmission testbed allowing increase of symbol rate up to 128 GBaud. Using probabilistic constellation shaped modulation formats at an entropy of 7.5 bits per symbol and polarization multiplex we successfully transmitted at net-bit rates up to 1.55 Tb/s for a single carrier in back to back while for a typical data center interconnect (DCI) distance of 80 km a net bit rate of 1.52 Tb/s has been achieved. [ABSTRACT FROM AUTHOR]

We propose and demonstrate a 100 Gbit/s silicon photonic (SiPh) coherent receiver (Rx) with advanced digital signal processing (DSP) for dual-polarization quadrature-phase-shift-keying (DP-QPSK) transmission. It employs integrated 2D polarization-splitting grating couplers (2D-GCs), modified hybrid mixers and high speed silicon-germanium (SiGe) photodiodes (PDs). The 2D-GC replaced the polarization beam splitters and rotators needed in traditional coherent Rx. Moreover, the SiGe PD has the bandwidth >50 GHz. [ABSTRACT FROM AUTHOR]

The requirement to achieve high reliability for the die attach in thermoelectric generator (TEG) package design is key to their viability and safe operation in automotive applications. In this study, the reliability of die attach material Al 718 (88% Al, 12% Si) during high temperature operating conditions is discussed. A novel approach is outlined to determine the damage parameter for accurate reliability predictions using a scalable test vehicle fabrication, testing, and finite element analysis (FEA) simulations. In addition, a new TEG package design is proposed that can withstand extreme environmental conditions and exhibit enhanced mechanical reliability by minimizing the likelihood that sublimation and oxidation of the semiconductor dies occurs. The proposed design of TEGs is analyzed using finite element simulations. Prototype models were fabricated and tested to validate the computational predictions. Continuum damage mechanics was used to predict the fatigue life of TEG packages using computational modeling of cyclic damage evolution. The results demonstrated that the proposed die attach design can be commercially viable for high-temperature TEG applications. [ABSTRACT FROM AUTHOR]

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This letter presents a linear wideband differential optical driver amplifier in a 90-nm silicon germanium (SiGe) bipolar-complementary-metal-oxide-semiconductor (BiCMOS) process. The amplifier utilizes a modified triple-stacked heterojunction bipolar transistor (HBT) topology with emitter degeneration to achieve high output voltage swing and high linearity. The amplifier achieves 13.2-dB voltage gain with a bandwidth from dc to 53 GHz. The amplifier can deliver a 4-V peak-to-peak differential ($V_{\mathrm {ppd}}$) with a total harmonic distortion (THD) of 1.6% at 1 GHz. The amplifier consumes 630-mW dc power at the small-signal operation. [ABSTRACT FROM AUTHOR]

Maximum oscillation frequency (${f}_{\textit {MAX}}$) of mm-wave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of ${f}_{\textit {MAX}}$ are very difficult. Determination of ${f}_{\textit {MAX}}$ is significantly affected by the measurement uncertainties in the admittance (${y}$) parameters. In order to get rid of the random measurement error and to obtain a reliable and stable ${f}_{\textit {MAX}}$ value, the frequency dependent ${y}$ -parameters are described by rational functions formulated from the small-signal hybrid ${\pi }$ -model of the transistor under investigation. The parameters of these functions are determined following a least square error technique that minimizes the functional error with the measured data. The approach is especially useful for a fast and reliable evaluation of ${f}_{\textit {MAX}}$ value. Devices from two different SiGe and an FDSOI (Fully Depleted Silicon On Insulator) MOS technology are measured and stable ${f}_{\textit {MAX}}$ values are estimated following this approach. [ABSTRACT FROM AUTHOR]

This work investigates a low-temperature and high-pressure (LTHP) hydrogen treatment in Si-channel and SiGe-channel metal–oxide–semiconductor capacitors (MOSCAPs). The LTHP hydrogen treatment can repair dangling bonds in the SiO2/Si and SiO2/SiGe interfaces to enhance device performance. Additional parameters of the treatment, including treatment pressure and time, are also investigated to better understand the reaction mechanisms, which further proves the effectiveness and potential of this supercritical fluid (SCF)-based treatment. In addition, this treatment will not damage the front structure and materials due to the relatively low process temperature (120 °C). Therefore, this treatment can be a nondestructive postannealing process. The results of extracting interface defect density (Dit) by the conductance method show that there is an ~51% reduction in the defect density after this posttreatment, a significant decrease. Finally, a TCAD simulation of different defect densities verifies the repair mechanism of deep-level defects. [ABSTRACT FROM AUTHOR]

Increasing demands for new computer architectures may require embedded non-volatile memories as for example in-memory computing. Ferroelectric field-effect transistors (FeFETs) add further advantages besides their outstanding properties due to the availability of both n-type and p-type transistors. The latter favor a different channel materials, like SiGe, due to the low hole mobility in silicon. In this article, we demonstrate the integration of ferroelectric hafnium oxide on SiGe as well as working p-type FeFETs, possessing a large memory window of about 1.1 V and low variability. Such architectures were co-integrated into a standard high-k metal gate (HKMG) CMOS platform. Furthermore, we report on the impact of annealing temperature on the interface and ferroelectric layer, which appears to be universal for SiGe and Si substrates. Here, a growth of the interface layer during annealing at higher temperatures was observed as well as a reduction of the wake-up effect for the ferroelectric layer. [ABSTRACT FROM AUTHOR]

This work focuses on the design issues of radio frequency (RF) bipolar integrated circuits (ICs) as a part of frequency synthesizers for extreme environmental applications. It is shown that silicon–germanium (SiGe) and gallium arsenide (GaAs) heterojunction bipolar transistors (HBTs) as well as bipolar RF ICs (including frequency dividers, voltage-controlled oscillators, and wide-band amplifiers) are highly sensitive to ambient temperature and radiation-induced displacement damage. This article also presents a design approach based on specialized HBT macromodels and hardening techniques. [ABSTRACT FROM AUTHOR]

In this work, we present a simple analytical model for electrothermal heating in multifinger bipolar transistors under realistic operating condition where all fingers are heating simultaneously. The proposed model intuitively incorporates the effect of thermal coupling among the neighboring fingers in the framework of self-heating bringing down the overall model complexity. Compared to the traditional thermal modeling approach for an n-finger transistor where the number of circuit nodes increases as n2, our model requires only n-number of nodes. The proposed model is scalable for any number of fingers and with different emitter geometries. The model is validated with 3-D thermal simulations and measured data from STMicroelectronics B4T technology. The Verilog-A implemented model simulates 40% faster than the conventional model in a transient simulation of a five-finger transistor. [ABSTRACT FROM AUTHOR]

We investigate the reliability of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) in 55-nm technology under mixed-mode stress. We perform electrical characterization and implement a TCAD model calibrated on the measurement data to describe the increased base current degradation at different collector-base voltages. We introduce a simple and self-consistent simulation methodology that links the observed degradation trend to interface traps generation at the emitter/base spacer oxide ascribed to hot holes generated by impact ionization (II) in the collector/base depletion region. This effectively circumvents the limitations of commercial TCAD tools that do not allow II to be the driving force of the degradation. The approach accounts for self-heating and electric fields distribution allowing to reproduce measurement data including the deviation from the power-law behavior. [ABSTRACT FROM AUTHOR]

In this brief, design methodology and measurement results of W-Band Dicke radiometer blocks are presented. The Dicke radiometer blocks are implemented in IHPs 0.13- $\mu \text{m}$ SiGe BiCMOS technology. All the implemented blocks, namely the SPDT switch, LNA and the power detector demonstrate the state of the art performance at W-Band. The SPDT has a measured IL of 1.8 dB and 20 dB isolation. The LNA achieves a peak gain of 22.3 dB and 4.2 dB NF and the PD has a NEP better than 0.5 pW/ $\sqrt {Hz}$. To achieve the minimum NETD, all the blocks are designed to be as wideband as possible. Using the measurement and simulation results, the achievable NETD of the radiometer is calculated to be better than 0.5 K. [ABSTRACT FROM AUTHOR]

A miniaturized broadband on-chip bandpass filter (BPF) is presented based on shunt dual-layer meander-line resonators and several metal-insulator-metal (MIM) capacitors. To understand the operational mechanism of the proposed BPF structure, it is analyzed using a simplified LC equivalent circuit model for further investigation of the transmission zeros (TZs) distributions. To validate the proposed idea, the BPF with three TZs is implemented in a commercial 0.13- $\mu \text{m}$ SiGe (Bi)-CMOS process. The measured results show that the BPF has a center frequency at 18 GHz with a very broad bandwidth of 66.7%, and the minimum insertion loss within the passband is 2.9 dB. The chip, excluding the GSG pads, is about 0.318 mm $\times0.392$ mm. [ABSTRACT FROM AUTHOR]

We present scaling and variation predictions for a strained-silicon (s-Si) fin-based high electron mobility transistor (FinHEMT) with well-tempered, short-channel characteristics. Using device simulation calibrated with experimental data, we predict that the FinHEMT can achieve high electron mobility (~1100 cm2/Vs) and enhance effective mobility (up to 2x) by suppressing the surface roughness scattering effect in the Si quantum well (QW) channel. Moreover, excellent scalability of the FinHEMT ON-current (${I}_{{\textit {ON}}} >1.1$ mA/ $\mu \text{m}$ at ${L}_{G} < 10$ nm) is predicted as the high channel mobility can reduce the underlap series resistance in the scaled device. Owing to this low underlap resistivity, geometrical variations of fin width and underlap length have little effect on the ON-current in FinHEMT. [ABSTRACT FROM AUTHOR]

We report improvement of TiN/Y2O3/ Si0.78Ge0.22 metal-oxide-semiconductor (MOS) interface properties by employing the trimethylaluminum (TMA) pretreatment before Y2O3 deposition. It is found that the optimum number of the TMA pretreatment cycles for minimizing interface trap density (Dit) and slow trap density (ΔNst) of TiN/Y2O3/SiGe interfaces with post metallization annealing (PMA) at 450 °C is ten cycles. The reduction in Dit and Δ~Nst is attributable to less amounts of Ge–O bonds at the SiGe interfaces. On the other hand, an increase in Dit with further increasing the number of TMA pretreatment is attributable to more amounts of Al–O bonds in ILs. [ABSTRACT FROM AUTHOR]

This letter presents new wideband single-pole double-throw (SPDT) RF switches utilizing SiGe heterojunction bipolar transistors (HBTs) for both series and shunt switches. SiGe HBT, when used as a series switch, exhibits small parasitic components compared to bulk CMOS, which improves insertion loss at high frequency and supports wider bandwidth. For a series switch, three configurations are proposed: using the collector as an input (CI), using the emitter as an input (EI), and using a combination of the two in an antiparallel (AP) fashion. While all three configurations exhibit similar performance, the SPDT switch with the EI SiGe HBT exhibits the best insertion loss and isolation achieving dc-to-above 110-GHz bandwidth, 2.5 dB of insertion loss, and 27.3 dB of isolation at 60 GHz. The SPDT switch with AP SiGe HBT pair exhibits the highest linearity, with 15.6 dBm of input 1-dB compression point (IP 1 dB) at 10 GHz. With 0.61 mW of power dissipation, these new SPDT switches using SiGe HBTs exhibit similar performance to silicon-on-insulator (SOI) CMOS while obtaining higher power capability among conventional series-shunt SPDT designs. [ABSTRACT FROM AUTHOR]

In this letter, a self-mixing balanced frequency tripler is presented. It comprises a push–push frequency doubling stage followed by a single balanced mixing stage sharing the input power via coupled lines. The chip is fabricated using the SG13G2 (130-nm SiGe BiCMOS) technology of Innovations for High Performance Microelectronics (IHP). A measured output power of 3 dBm is achieved at 280 GHz with a dc-to-RF efficiency of 2.19%. [ABSTRACT FROM AUTHOR]

This article presents the design of a highly linear high-power silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) 802.11ac/ax wireless local area network (WLAN) power amplifiers (PAs). The challenges associated with electrothermal effects on the dynamic operation of WLAN PAs are first discussed. We then propose the design methods that take into account the electrothermal transient effect to improve linear output power (POUT) and dynamic error vector magnitude (DEVM). A compact four-way output transformer balun is proposed to achieve efficient power combining, and a built-in 2nd-harmonic short is demonstrated by using a novel multi-layered metallization scheme. A thermally compensating dynamic bias circuit that improves the DEVM and reduces memory effects is designed with an integrated temperature sensor. Different SiGe HBT array layouts, laterally and vertically arranged, of the output stage of the PA are also investigated. With the 802.11ac MCS9 VHT80 test signals, the DEVM of a PA with a laterally arranged output stage is lower than that of its vertical counterpart. This suggests the importance of the layout on the transistor electrothermal transient effect. The PA with the laterally arranged output stage shows a POUT of 22.5/23.6/23.2 dBm (DEVM = −35 dB) with 10.0/12.2/11.2% power-added efficiency (PAE) at 5210/5530/5855 MHz under an 802.11ac MCS9 VHT80 test signal at 50% duty cycle. Good DEVM performance was measured under the test signal with various duty cycles, indicating that the proposed PA is thermally robust. The design supports the 802.11ax MCS11 VHT80 signals with 19.4-dBm POUT, satisfying a DEVM of −40 dB. [ABSTRACT FROM AUTHOR]

A push-pull oscillator topology that uses only one type of active device is proposed in this article. A magnetic transformer is leveraged to set positive feedback around a common-collector differential npn transistor pair, implementing the push-pull operation. This results in half the bias current for a given amplitude of oscillation, compared to more standard oscillator topologies. A thorough phase noise analysis of the circuit is carried out, emphasizing the crucial role of the magnetic transformer in the circuit operation and noise optimization. Proof-of-concept prototypes implemented in a 130-nm SiGe BiCMOS technology operate at 17 GHz and show a phase noise as low as −116 dBc/Hz at 1-MHz offset, while drawing 13.7 mA from the 3.3-V supply. The tuning range is 15%. While the circuit is demonstrated in SiGe BiCMOS technology, it lends itself equally well to implementations in other technologies where only one fast device is available, such as SiGe HBT, InP HBT, and GaN HEMT. [ABSTRACT FROM AUTHOR]

This article describes the design and performance of a 140-GHz SiGe and a 100-GHz InP triple-stacked HBT distributed amplifier with active bias terminations. The active bias network is configured to extend the practical low-frequency operation while maintaining gain flatness and linearity. Triple-stacked HBTs are used to increase the gain–bandwidth and linear output capability. The SiGe design is based on HBTs with a peak ƒT/ƒmax of 300/350 GHz and achieves 11.7 dB of gain and a bandwidth from baseband to 140 GHz. The InP HBT design is based on DHBTs with a peak ƒT/ƒmax of 250/250 GHz and obtains a gain of 10.8 dB and a bandwidth of 100 GHz. Although the SiGe design achieves 1.5 times higher gain–bandwidth, the InP DHBT design achieves ~3–4.5 dB greater IP3, P1~dB, and P3 ~dB while consuming only ~23% higher dc power. These results represent the first broadband performance comparison of near-identical (apples–apples) DA designs implemented in SiGe and InP HBT device technologies. Although there are previous reports of larger bandwidth distributed amplifiers in both InP and SiGe technologies demonstrated up through 200 GHz, the InP and SiGe monolithic microwave integrated circuits (MMICs) described in this article are believed to represent the highest bandwidths reported for HBT DAs using practical on-chip active bias terminations. [ABSTRACT FROM AUTHOR]

We present a comparison of design trade-offs for transimpedance, sensitivity, DC voltage offset cancellation, group-delay variation (GDV), common-mode rejection, and overload for transimpedance amplifiers (TIA) based on balanced, unbalanced, and pseudodifferential topologies. The TIAs are implemented monolithically in the IHP 250-nm SiGe BiCMOS EPIC process (fT = 190 GHz). Measurement results shown here support data rates to 50 Gb/s with BER better than 10−10. The power consumption of the TIAs is 54 mW for TIA designs that approach 1 pJ/b. [ABSTRACT FROM AUTHOR]

This letter presents a compact ${W}$ -band frequency tripler implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology. It uses a single-balanced differential pair core overdriven as Class A amplifiers. The usage of a single-stage multiplication without any additional amplifying stage along with the on-chip transformer baluns for single-ended to differential conversions at the input and the output improves efficiency, at the same time enabling a compact design. The third-order harmonic is further improved by enhancing the second-order harmonic at the common node of the differential pair, which in turn mixes with the input and contributes to the third-order harmonic. The tripler generates a saturated output power of 2.9 dBm at 84 GHz with fractional 3-dB bandwidth of 25.6%, ranging from 75 to 96 GHz and an in-band fourth-harmonic suppression of more than 20 dBc. The chip occupies an area of $435\,\,\mu \text{m}\,\,{\times }\,\,560\,\,\mu \text{m}$ (0.24 mm2) and consumes 88 mW from a 3.3-V power supply. [ABSTRACT FROM AUTHOR]

This article presents two broadband frequency multiplier chains (FMCs) fabricated with a standard 130-nm SiGe BiCMOS process. In both solutions, a broadband push-push frequency doubler (x2) operating at 220–360 GHz was employed. In order to properly drive such a doubler, with sufficient input power and bandwidth, two different power amplifiers (PAs) have been adopted: the former is based on a cascode configuration and the latter is based on a stacked topology. In addition, a D-band frequency quadrupler (x4) has been integrated before the PAs and doubler, to complete the design of frequency eighth tupler (x8) chains. The first FMC with the cascode PA achieves peak output power of 2.3 dBm, with maximum conversion gain (GC) and bandwidth of 15 dB and 127 GHz, respectively. The second FMC with the stacked PA delivers a saturated output power of 2.5 dBm, with a maximum GC and a bandwidth of 12 dB and 72 GHz, respectively. The two FMCs consume maximum dc power of 0.537 and 0.542 W. The complete design procedure of the FMCs is presented in this article. To the best of our knowledge, the reported bandwidth is state-of-the-art and widest among SiGe based FMCs. [ABSTRACT FROM AUTHOR]

Low-noise amplifiers (LNAs) are necessary components for any communications system. Single-event transients (SETs) induced by energetic particles in space can corrupt the data in an RF receiver. Using p-n-p silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs), instead of their more common n-p-n counterparts, has been shown to be an effective mitigation technique in digital, analog, and RF circuits. Since p-n-p SiGe HBTs tend to have lower performance than n-p-n SiGe HBTs, in this article, the tradeoffs between performance and SET robustness have been evaluated through the use of simulations. Two LNAs were designed using an algorithmic design technique: one using only n-p-n SiGe HBTs, and the other using only p-n-p devices. The n-p-n LNA had higher peak gain and lower noise figure at the center frequency of 5 GHz when compared to the p-n-p LNA, by 3.2 and 0.4 dB, respectively. However, the n-p-n LNA also produced transients with amplitudes larger than the p-n-p LNA across all simulated linear energy transfers. Although the p-n-p LNA has lower overall performance, it is also more robust to SETs. Thus, the choice between using n-p-n and p-n-p SiGe HBTs for an RF design will depend on application requirements. [ABSTRACT FROM AUTHOR]

The blanket boron implant (BBI) in the sigma-shaped trench before the embedded SiGe (eSiGe) source/drain (S/D) formation for 28-nm PMOSFET is proposed in this letter. It is demonstrated that the BBI can significantly reduce the S/D junction capacitance with little influence on On/Off characteristic. In addition, the 1/ƒ noise is also effectively lowered. [ABSTRACT FROM AUTHOR]

In an advanced complementary metal-oxide-semiconductor (CMOS) technology node, small nano-scopic defects tend to have a significant impact on the yield and reliability of the final product. As the technology advances in fin field-effect-transistors (FinFETs), it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. The process of selective epitaxial growth of silicon-germanium (SiGe) on source/drain (S/D) regions is especially prone to defects due to the complexity of the process, thus giving a very narrow processing window to achieve the desired device, yield and reliability results. In this paper we evaluate a critical defect of “Abnormal epi” seen during the selective epitaxial growth of in-situ boron (B) doped SiGe on FinFETs. Abnormal epi here refers to abnormally large and spurious epitaxial growth defect occurring as random instances on a wafer die. These defects, depending on where in the layout they occur, can lead to catastrophic failure under higher test voltages due to the physical shorting of n and p FET devices. We also explore the process parameters which influence this defect including incoming surface conditions and propose mechanisms that lead to the defect. Further, an optimization of the processing parameters in the integration scheme to minimize the occurrence of these defects leads to yield gain and cost savings required for high volume manufacturing. [ABSTRACT FROM AUTHOR]

This letter presents a 210–291-GHz $8\times $ multiplier chain in the 0.13- $\mu \text{m}$ SiGe Bipolar CMOS (BiCMOS) technology for the broadband generation of carrier signals, imaging, and spectroscopy. It consists of three cascaded Gilbert-cell doublers with compact input matching networks to generate quadrature collector currents in the switching quad for broadband flat conversion gain. The multiplier chain generates a saturated output power of −7.7 dBm at 244.5 GHz with a 3-dB bandwidth of 81 GHz. It consumes 0.24 W of dc power and occupies 0.86 mm 2 of chip area. [ABSTRACT FROM AUTHOR]

Nonreciprocal components such as circulators, isolators, and gyrators play vital roles in modern communication systems. However, all of them are limited to 0.1 terahertz (THz) due to their poor performances in terms of linearity, loss, and noise at high frequency, making them not amenable for the potential sub-THz/THz operation. In this letter, a 210-GHz nonreciprocal isolator based on the resistor-free unidirectional ring resonators is implemented in a 130-nm SiGe BiCMOS process ($f_{T}/f_{\mathrm {max}} = 300$ /500 GHz). Thanks to the proposed resistor-free ring resonators, the isolator achieves 1.40-dB loss, 6.7-dB noise figure (NF)/unit, 21.2-dB isolation, and superior linearity. Even compared with the nonreciprocal components operating at a much lower frequency, this structure also exhibits a good performance. [ABSTRACT FROM AUTHOR]

This paper reports the design and characterization of a D-band front-end receiver, implemented in a 0.13- ${\mu {m}}$ SiGe BiCMOS technology, for use in a direct-detection-based Dicke radiometer architecture. The peak responsivity of the Dicke radiometer is 688 MV/W at 130 GHz, and its minimum value is about 82.6 MV/W at 170 GHz. The Dicke switching frequency is 10 kHz. The noise equivalent power of the Dicke radiometer remains below $20\textit {fW/H}{z}^{\text {1/2}}$ at the frequency range of 110–155 GHz, and its minimum value is about $9.3~\textit {fW/H}{z}^{\text {1/2}}$ at 130 GHz. The implemented radiometer achieves an NETD of 0.13K for a back-end integration time of 30ms. Its total chip area is approximately 1.7mm2, and the overall quiescent DC power consumption is 33.8 mW. To the authors’ best knowledge, the implemented Dicke radiometer achieves the best NETD in the literature. [ABSTRACT FROM AUTHOR]

We propose a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV semiconductor (p-IV) heterostructure, allowing us to realize both n- and p-channel TFET operations under the same device structure. Here, the p-IV side in the heterostructure has a metal–oxide–semiconductor (MOS) gate-stack that modulates the surface potential of the p-IV MOS interface and controls the band-to-band tunneling (BTBT) current under the p-TFET operation. Technology computer-aided design (TCAD) simulation predicts the p-TFET operation with symmetric electrical characteristics to the n-TFET operation. Moreover, we experimentally demonstrate the p-TFET operation of the n-ZnSnO/p-SiGe bilayer device, fabricated on a SiGe-on-insulator substrate, under Si back-gate operation. In addition, both n- and p-TFET operations are observed in an identical device by using the top- and back-gate electrodes. [ABSTRACT FROM AUTHOR]

Among all material systems currently being exploited for tunnel field-effect transistor (TFET) applications, silicon germanium (SiGe) is most likely to be adopted for the future low power very-large-scale integration (VLSI) technologies due to its VLSI-compatibility, mature synthesis techniques, and tunable bandgap. This article demonstrates experimentally the enhancement of the drive current (ION) and the reduction in the subthreshold swing (SS) of vertical Si p-TFET by inserting a thin layer of boron-doped Si0.8Ge0.2 (EG ~ 1 eV) between the source and the channel. Owing to the reduction in the tunneling barrier height and the increased lateral electric field, carrier transport across the tunneling junction is significantly enhanced. By improving the material quality, further enhancement in the device performance is observed. Simulation suggests that the proposed structure serves as an effective method to boost the device performance of TFETs. [ABSTRACT FROM AUTHOR]

This letter presents a novel implementation of a ${V}$ -band single-pole double-throw switch that facilitates the internal calibration of radiometers by integrating an ambient noise source and an avalanche noise source. The switch is implemented in a 0.13- $\mu \text{m}$ SiGe bipolar-CMOS (BiCMOS) process and uses a shunt topology with $\lambda $ /4 directional couplers that inject noise from the avalanche source. The avalanche source is implemented using the collector-base junction of a SiGe heterojunction bipolar transistor (HBT) and attains a measured excess noise ratio of 18.7 dB at 60 GHz. The switch achieves a midband insertion loss of 2.0 dB and an isolation of 22 dB at 60 GHz. An excess input-referred noise temperature of 620 K is added with the noise source ON. To the best of our knowledge, this is the first avalanche noise source using a diode-configured SiGe HBT and the first monolithic two-reference switch for calibrating millimeter-wave radiometers. [ABSTRACT FROM AUTHOR]

In this brief, the analysis, design, and measured results of a fully integrated 7-bit step attenuator implemented in a 0.25- $\mu \text{m}$ Silicon–Germanium (SiGe) BiCMOS process technology, are described. The attenuator is designed based on delicately ordered and cascaded $\Pi $ /T type attenuation blocks, which are comprised of series/shunt switches employing SiGe hetero-junction bipolar transistors (HBTs) with peak $f_{T}/f_{\max }$ of 110/180 GHz. HBTs are employed as a series switch to decrease the insertion-loss (IL) of the attenuator. Moreover, to the authors’ best knowledge, this is the first study presenting the effect of employing reverse-saturated HBTs as a shunt switch for each attenuation blocks. Thanks to this advancement, the highest input-referred 1-dB compression point (IP1dB) is reported for Si-based similar studies. This method also decreases the IL of the proposed attenuator. The measurements result in the state-of-the-art performance with 28.575-dB attenuation range by 0.225-dB gain steps while maintaining 7-bit amplitude resolution across 6.6 GHz–12.8 GHz frequency band, where RMS phase error remains below 3.3° and IL is less than 12.4 dB. The measured IP1dB of the attenuator is 13.5 dBm while drawing 8 mA from 3.3-V supply. The die occupies an area of 1.37 mm $\times \,\, 0.56$ mm excluding pads. [ABSTRACT FROM AUTHOR]

Absorption spectroscopy based on supercontinuum generation in the mid-infrared is a powerful technique to analyze the chemical composition of samples. Furthermore, phase-coherent supercontinuum sources can enable fast data acquisition with coherent, stable pulses that allow single-shot measurements. We report here a numerical study of the coherence of an octave-spanning mid-infrared supercontinuum source that was experimentally obtained in an air-clad SiGe/Si waveguide. We show that engineering two closely spaced zero-dispersion wavelengths that enclose an anomalous dispersion band centered around a fixed pump wavelength can produce supercontinuum pulses with high spectral density and full coherence at the extreme ends of the spectrum. This work is important for absorption spectroscopy, on-chip optical frequency metrology, and f-to-2f interferometry applications. [ABSTRACT FROM AUTHOR]

A comparison of heavy-ion-induced single-event transients (SETs) in silicon–germanium heterojunction bipolar transistors (SiGe HBTs) fabricated on both bulk and silicon-on-insulator (SOI) substrates is presented. Experimental heavy-ion data show a reduction of sensitive volume of ≈ 350 × for the SiGe HBTs fabricated on SOI compared to those on a bulk substrate. Furthermore, the results indicate that the sensitive volume of the SOI SiGe HBTs is confined to the intrinsic device. These results have been confirmed using pulsed laser data and TCAD simulations. Limiting the charge collection depth of SiGe HBTs by fabricating them on SOI facilitates correlation of ion and laser results. The improved ease of correlation is a result of suppressing diffusive charge collection mechanisms that are difficult to replicate with the charge deposition profile generated by two-photon absorption using a tightly focused laser beam. However, a potential issue with pulsed laser testing is determining the loss of the pulse energy through the buried oxide, which requires detailed knowledge of the semiconductor platform. Overall, the reduction of sensitive volume for the SOI SiGe HBTs compared to those on a bulk substrate is a clear advantage from a single-event upset vulnerability perspective. [ABSTRACT FROM AUTHOR]

The propagation of single-event transients from the electrical to the photonic domain in a segmented Mach–Zehnder modulator was investigated using pulsed-laser measurements and lumerical simulations. Although electrical transients can heavily degrade the input data to the modulator, almost all of the degradation can be suppressed once it is converted into the optical domain. The mitigation of transients is primarily accomplished by increasing Vπ of each segment, making electrical transients up to 6 V essentially negligible. A “folding” effect of the optical transient is also explained in relation to Vπ. Two radiation-hardening-by-design (RHBD) approaches are suggested to mitigate transient effects. [ABSTRACT FROM AUTHOR]

This article reports the design and characterization of a W-band frequency extension module, implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, for the vector network analyzers (VNAs). The frequency extension module has a dynamic range of about 110 dB, for an IF resolution bandwidth of 10 Hz, with an output power that varies between −4.25 and −0.3 dBm over the W-band. It has an input-referred 1-dB compression point of about 1.9 dBm. The directivity of the frequency extension module is better than 10 dB along the entire W-band, and its maximum value is approximately 23 dB at around 75.5 GHz. The total chip area is about 5.9 mm2. To the best of authors’ knowledge, this article is the first demonstration of a single-chip frequency extension module in a silicon-based semiconductor technology. [ABSTRACT FROM AUTHOR]