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This paper presents a power management policy that utilizes reinforcement learning to increase the power efficiency of mobile device systems based on a multiprocessor system-on-a-chip (MPSoC). The proposed policy predicts a system’s characteristics and learns power management controls to adapt to the variations in the system. We consider the behavioral characteristics of systems that run on mobile devices under diverse scenarios. Therefore, the policy can flexibly manage the system power regardless of the application scenario and achieve lower energy consumption without compromising the user satisfaction. The average energy per unit quality of service (QoS) of the proposed policy is lower than that of the previous six dynamic voltage/frequency scaling governors by 31.66%. Furthermore, we reduce the runtime overhead by implementing the proposed policy as hardware. We implemented the policy on the field programmable gate array (FPGA) and construct a communication interface between the central processing units (CPUs) and the hardware of the proposed policy. Decision-making by the hardware-implemented policy is 3.92 times faster than by the software-implemented policy.

We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and $2 \times 2$ ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient $6 \times 6$ approximate ternary multipliers. The energy benefit of the proposed $6 \times 6$ approximate ternary multipliers have been verified using HSPICE simulation. The proposed approximate design shows 82.8% power-delay product with 41.8% mean absolute percentage error improvement over the previous approximate multiplier-based design. Image processing applications are conducted using the proposed approximate designs to confirm that the accuracy of ternary multiplication is satisfied the user’s requirement.

In advanced technology nodes, emerging 3-D integration technology is a promising “More Than Moore” lever for continued scaling of system capability and value. In the 3-D integrated circuit (3-D IC) implementation, the power delivery network (PDN) is crucial to meeting design specifications. However, determining the optimal PDN design is nontrivial. On the one hand, to meet the voltage (IR) drop requirement, a denser power mesh is desired. On the other hand, to meet the timing requirement, more routing resource is needed for signal routing. Moreover, additional competition between signal routing and power routing is caused by intertier vertical interconnects in 3-D IC. In this article, we propose a power delivery pathfinding methodology for emerging 3-D integration, which seeks to identify a “near-optimal” (or, very high quality) PDN for a given BEOL stack, vertical interconnection, and PDN specification. Compared with previous works, our methodology can explore richer solution spaces as it supports different PDN layer combinations and PDN layer configurations. We develop models for routability and worst IR drop to help reduce iterations between PDN design and circuit design in 3-D IC implementation. We present validations and demonstrate improvement in IR drop and routability with real design blocks in 28- and 14-nm foundry technology nodes.

Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼10

Variation-aware leakage analysis becomes an essential design process as the technology node continuously shrinks. This article proposes a novel additive statistical leakage analysis method that uses exponential mixture model (EMM) to estimate the leakage distribution. Using a few leakage data for sub-blocks of an input circuit, we estimate any shape of leakage distribution regardless of new process nodes or operating conditions. Leakage distribution of an input circuit can be obtained by adding the leakage distributions of the sub-blocks. The proposed addition step sequentially adds the leakage distributions of sub-blocks that are expressed as EMMs. Before the addition step, we improve the accuracy by handling linear dependence among leakage simulation data of sub-blocks. In addition, we propose a method to reduce the number of components of an EMM to prevent exponential increase in runtime and memory during the addition process. The proposed method achieved 43.6 times improvement in goodness-of-fit of the estimated cumulative density functions compared to the best results of other analytic model-based methods.

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

In bus routing, if signal bits in a bus structure share a common routing topology, routability is increased by avoiding twisted patterns and variation immunity. The bus routing problem has become significantly important because of increasing complexity of bus structures for multichip-module, I/O pins, or on-chip memories in advanced technology. We present and evaluate a compact topology-aware bus routing method that can both compactly synthesize the routing topology of the bus and minimize design rule violations even in designs with high bus density and high track utilization. Our proposed method completed the bus routing in the runtime limit of the ICCAD-2018 contest and achieved 66% reduction in total cost compared with the winner of that contest.

Modern mobile systems are requested to execute diverse user scenarios. Depending on the types of user scenarios, mobile systems utilize hardware resources differently. Thus, power management policies of mobile systems must adapt to various user scenarios. In this paper, we propose a dynamic voltage/frequency scaling (DVFS) policy to increase the energy efficiency of multicore mobile systems by adapting to user scenarios. The proposed policy provides effective power management regardless of user scenarios by using operation characteristics that can represent the execution behavior of various user scenarios. Furthermore, the proposed policy is suitable for modern mobile systems in which online power management is essential, because it does not require preliminary knowledge of target scenarios. To balance the trade-off between energy consumption and quality-of-service (QoS), the proposed scenario-aware policy provides `just enough' processing speed to process the requested amount of work at the given parallelism level. To demonstrate the practicality of the proposed policy, we evaluated the effectiveness of the proposed scenario-aware policy for real-world user scenarios. Compared to the conventional DVFS policies, the proposed scenario-aware policy achieved a maximum of 25.5% energy saving on the mobile system that uses asymmetric multicore CPU, and a maximum of 30.7% energy saving on the mobile system that uses symmetric multicore CPU, without any QoS violation that degrades user experiences.

A new concept of read-out method for ferroelectric random-access memory (FeRAM) using a graphene layer as the channel material of bottom-gated field effect transistor structure is demonstrated experimentally. The transconductance of the graphene channel is found to change its sign depending on the direction of spontaneous polarization (SP) in the underlying ferroelectric layer. This indicates that the memory state of FeRAM, specified by the SP direction of the ferroelectric layer, can be sensed unambiguously with transconductance measurements. With the proposed read-out method, it is possible to construct an array of ferroelectric memory cells in the form of a cross-point structure where the transconductance of a crossing cell can be measured selectively without any additional selector. This type of FeRAM can be a plausible solution for fabricating high speed, ultra-low power, long lifetime, and high density 3D stackable non-volatile memory.

With the increasing demand for state-of-the-art technologies, such as wearable devices and the Internet of things (IoT), power integrity has emerged as a major concern for high-speed, low-power interfaces that are used as mobile platforms. By using case-specific design models in a high-speed memory system, only a limited analysis of the effects of parametric variations can be performed in complex design problems, such as adjacent voltage domain coupling at high frequencies. Moreover, a conventional industrial method can be simulated only after completing the design layout; therefore, a number of iterative back-annotation processes are required for signoff; this delays the time to market. In this paper, we propose a power integrity coanalysis methodology for multiple power domains in high-frequency memory systems. Our proposed methodology can analyze the tendencies in power integrity by using parametric methods, such as parameter sweeping and Monte Carlo simulations. Our experiments prove that our proposed methodology can predict similar peak-to-peak ripple voltages that are comparable with the realistic simulations of low-power double data rate four interfaces.

We propose SmartGrid, a new video-retargeting method that preserves a shape of the salient object and maintains a temporal coherence for the static background regions in the video. Previous methods mainly focus on preserving the shape of the salient object or maintaining the temporal coherence for each region. However, these methods do not explicitly adjust the sizes of the grids corresponding to the salient objects and the static background regions. Thus, they have difficulty in maintaining the consistency of the salient object shape and the temporal coherence for the static background regions. The basic idea of SmartGrid is to maintain the consistency of the contents in consecutive frames by analyzing the degree of the spatiotemporal consistency. Compared to the best results obtained using eight previous methods, SmartGrid achieved improvements of 1.19× in Bidirectional Similarity Measure, 7.59× in Jittery Metric 1, and 13.16× in Jittery Metric 2, and reduced the average computation time per pixel by 6.14×.

This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89μΑ to 1.46μΑ. By connecting ternary inverters back-to-back, a trit-storage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.

This paper presents a convolutional neural network (CNN) accelerator that can skip zero weights and handle outliers, which are few but have a significant impact on the accuracy of CNNs, to achieve speedup and increase the energy efficiency of CNN. We propose an offline weight-scheduling algorithm which can skip zero weights and combine two non-outlier weights simultaneously using bit-level sparsity of CNNs. We use a reconfigurable multiplier-and-accumulator (MAC) unit for two purposes; usually used to compute combined two non-outliers and sometimes to compute outliers. We further improve the speedup of our accelerator by clipping some of the outliers with negligible accuracy loss. Compared to DaDianNao [7] and Bit-Tactical [16] architectures, our CNN accelerator can improve the speed by 3.34 and 2.31 times higher and reduce energy consumption by 29.3% and 30.2%, respectively.

In this work, we present a differentiable neural architecture search (NAS) method that takes into account two competing objectives, quality of result (QoR) and quality of service (QoS) with hardware design constraints. NAS research has recently received a lot of attention due to its ability to automatically find architecture candidates that can outperform handcrafted ones. However, the NAS approach which complies with actual HW design constraints has been under-explored. A naive NAS approach for this would be to optimize a combination of two criteria of QoR and QoS, but the simple extension of the prior art often yields degenerated architectures, and suffers from a sensitive hyperparameter tuning. In this work, we propose a multi-objective differential neural architecture search, called MDARTS. MDARTS has an affordable search time and can find Pareto frontier of QoR versus QoS. We also identify the problematic gap between all the existing differentiable NAS results and those final post-processed architectures, where soft connections are binarized. This gap leads to performance degradation when the model is deployed. To mitigate this gap, we propose a separation loss that discourages indefinite connections of components by implicitly minimizing entropy.

Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect portion. We examined the benefits of ternary logic including the impacts of interconnect length reduction using a realistic ternary device model. The standard cell layouts of ternary SUM, NCARRY, NANY, and PROD gates are designed using balanced ternary logic and multi-threshold graphene barrister (MTGB). The interconnect wire length of the 5-trit arithmetic logic unit is reduced by ~37 % and this reduction rate is maintained even in more complex circuits.

A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.

Convolutional neural networks (CNNs) require a huge amount of off-chip DRAM access, which accounts for most of its energy consumption. Compression of feature maps can reduce the energy consumption of DRAM access. However, previous compression methods show poor compression ratio if the feature maps are either extremely sparse or dense. To improve the compression ratio efficiently, we have exploited the spatial correlation and the distribution of non-zero activations in output feature maps. In this work, we propose a grid-based run-length compression (GRLC) and have implemented a hardware for the GRLC. Compared with a previous compression method [1], GRLC reduces 11% of the DRAM access and 5% of the energy consumption on average in VGG-16, ExtractionNet and ResNet-18.

This paper presents a power management policy that exploits reinforcement learning to increase power efficiency of mobile device systems. Our Q-learning-based policy predicts a system’s characteristics and learns power management controls to adapt to the system’s variations. Therefore, we can flexibly manage the system power regardless of the application scenario and can achieve lower energy per QoS compared to previous dynamic voltage/frequency scaling governors. To minimize the process overhead, we implemented our power management policy as hardware; the hardware-implemented policy reduced the average latency up to 40× compared to the software-implemented policy.

Owing to the growth of the size of convolutional neural networks (CNNs), quantization and loop tiling (also called loop breaking) are mandatory to implement CNN on an embedded system. However, channel loop tiling of quantized CNNs induces unexpected errors. We explain why channel loop tiling of quantized CNNs induces the unexpected errors, and how the errors affect the accuracy of state-of-the-art CNNs. We also propose a method to recover accuracy under channel tiling by compressing and decompressing the most-significant bits of partial sums. Using the proposed method, we can recover accuracy by 12.3% with only 1% circuit area overhead and an additional 2% of power consumption.

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10−16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

In the design process of advanced semiconductor devices, statistical leakage analysis has emerged as a major step due to uncertainties in the leakage current caused by the process variations. In this paper, a novel statistical leakage analysis which uses Gaussian mixture model (GMM) as the density function of leakage current is proposed. To estimate the probability density function, our proposed method clusters the rapidly converged leakage data using the GMM. The GMM can represent any distributions, so it is suitable to estimate the leakage distribution, which varies as the technology node or operating condition changes. In addition, our proposed method (SLA-GMM) defines a terminating condition that guarantees the convergence of the leakage data and prevents the underfitting or overfitting in the GMM modeling process. With sequential addition, SLA-GMM significantly reduced the error that can occur during the addition process. In studies with a goodness-of-fit test, SLA-GMM achieved up to 98% and 94% improvements in the Chi-square static and the K-S static compared with the previous method based on an analytic model.

Convolutional neural networks (CNNs) are computationally intensive, and deep learning hardware should be implemented energy-efficiently for embedded systems or battery-constrained systems. In this paper, we propose an outlier-aware time-multiplexing MAC. We exploit a CNN feature maps' characteristic of being able to express most of the data in a low bit-width except a few large values, which we call ‘outliers' Our outlier-aware time-multiplexing MAC has improved the energy efficiency by up to 21.1% compared to conventional MACs.

We propose a fence-region-aware mixed-height standard cell legalization that can optimize the placement of standard cells that have more than a two row height in various shapes of the fence region. The algorithm consists of pre-legalization and mixed-height standard cell legalization steps to prioritize cell legalization; then a quality refinement step that uses simulated annealing reduces the displacement. Our proposed method achieved 63% improvement in the average quality score and 72% improvement in average runtime, compared to the winners of the ICCAD-2017 contest.

We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate. HSPICE simulation result has confirmed that power consumption of QETFF is lower than conventional single-edge-triggered flip-flop. The average power consumption is reduced by 31 % in flip-flop and 75 % in clock tree. We designed a ternary serial adder using QETFF and the energy efficiency of the proposed circuit is significantly improved compared to the previous design of ternary serial adder.

A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to maximize NTV mode clock frequency. Some cells that are particularly slow in NTV mode are optimized through transistor sizing and stack removal; static noise margin of each gate is extracted and appended in a library so that function failures can be checked and removed during synthesis. A new gate-sizing algorithm is proposed that takes account of timing slacks at both modes. A new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock-tree synthesis is reformulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock-path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV mode clock period is reduced by 24%, on average; clock skew at NTV decreases by 13%, on average; and NTV mode energy-delay product is reduced by 20%, on average.

Power gating circuit suffers from large amount of rush current during wakeup, especially when all switch cells are turned on simultaneously. If each switch cell is turned on at a different time, rush current can be reduced. It is shown in this paper that rush current can be reduced even more if signal transition time (or signal slew) to each switch cell is adjusted. We define wakeup scheduling as to determine turn-on time and signal slew of each switch cell; the goal is to minimize wakeup delay while keeping rush current below the maximum value that is allowed. The determined turn-on time and signal slew are implemented using a buffered tree. The wakeup scheduling and buffered tree construction are integrated into a design flow. To adapt to process variation, we use adjustable delay buffers in the wakeup network. We also apply grid-based design flow and use Schmitt triggers to implement large designs. Experiments in an industrial 1.1V, 32-nm technology demonstrate that the wakeup delay is reduced by 12% on average of example circuits compared with turn-on scheduling. HighlightsWe determine the signal slew and turn-on time of each footer cell to minimize wakeup delay while rush current constraint is respected.We implement the determined turn-on time and signal slew using a buffered tree.We propose a variation-adaptive design flow that uses adjustable delay buffers to satisfy rush current constraint.Experiments demonstrate that the wakeup delay is reduced compared with turn-on scheduling.

In this paper, we propose a novel method which utilizes the Gaussian Mixture Model (GMM) to estimate the leakage distribution of a circuit. Our proposed method assumes that the leakage distribution can be represented using the GMM which can cover any continuous function. After the GMM clustering using the leakage simulation data, the leakage distribution of the input circuit can be obtained. The experimental results with the K-S test showed that the proposed method exhibited 1.82e+05 times larger p-value and 7.74e-01 times smaller K-S statistics compared to the state-of-the-art benchmark method on average.

The power integrity of high-speed interfaces is an increasingly important issue in mobile memory systems. However, because of complicated design variations such as adjacent VDD domain coupling, conventional case-specific modeling is limited in analyzing trends in results from parametric variations. Moreover, conventional industrial methods can be simulated only after the design layout is completed and it requires a lot of back-annotation processes, which result in delayed delays time to market. In this paper, we propose a chip-package-PCB coanalysis methodology applied to our multi-domain high-speed memory system model with a current generation method. Our proposed parametric simulation model can analyze the tendency of power integrity results from variable sweeps and Monte Carlo simulations, and it shows a significantly reduced runtime compared to the conventional EDA methodology under JEDEC LPPDR4 environment.

Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to (ii) improve design performance (e.g., timing speculation). However, significant overheads (e.g., 16% and 14% energy penalties due to throughput degradation and additional circuits) are incurred by existing resilient design techniques. For instance, resilient designs require additional circuits to detect and correct timing errors. Further, when there is an error, the additional cycles needed to restore a previous correct state degrade throughput, which diminishes the performance benefit of using resilient designs. In this work, we describe an improved methodology for resilient design implementation to minimize the costs of resilience in terms of power, area, and throughput degradation. Our methodology uses two levers: selective-endpoint optimization (i.e., sensitivity-based margin insertion) and clock skew optimization. We integrate the two optimization techniques in an iterative optimization flow which comprehends toggle rate information and the trade-off between cost of resilience and margin on combinational paths. Since the error-detection network can result in up to 9% additional wirelength cost, we also propose a matching-based algorithm for construction of the error-detection network to minimize this resilience overhead. Further, our implementations comprehend the impacts of signoff corners (in particular, hold constraints, and use of typical vs. slow libraries) and process variation, which are typically omitted in previous studies of resilience trade-offs. Our proposed flow achieves energy reductions of up to 21% and 10% compared to a conventional (with only margin used to attain robustness) design and a brute-force implementation (i.e., a typical resilient design, where resilient endpoints are (greedily) instantiated at timing-critical endpoints), respectively. We show that these benefits increase in the context of an adaptive voltage scaling strategy.

The coupling of power domains in a typical package power distribution network (PDN) is investigated, mainly focusing on the effect of ground structures and substrate parameters. From the simulated impedance parameter data, the self and the coupling capacitances are calculated. The preliminary study shows that the effect of the bottom ground planes has the most dominant effect on the domain coupling, and the ground plane between adjacent power domains can be effectively used to reduce the domain coupling.

Multiple-valued logic (MVL) has potential advantagesfor energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuitdesigns. We design a novel ternary multiplier based on a ternaryCMOS (T-CMOS) compact model. To estimate performance andenergy efficiency of our ternary design, we construct a standardternary-cell library and exploit a ternary static timing analysis(T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.