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State-of-the-art portable ultrasound imaging systems employ a small transducer array and a low carrier frequency to fit stringent constraints on power and form factor, and this tends to compromise the ultrasound imaging quality. In this paper, we present a low-complexity low-power asynchronous compressed beamformer (ACB) for portable diagnostic ultrasound. The proposed ACB integrates asynchronous sampling and compressive sensing (CS), and is capable of reducing data conversion power and handling a large data volume at the mixed-signal interface. A high-rate continuous-time ternary encoding (CT-TE) scheme eliminates the need for interpolation filters and coordinate rotation digital computer (CORDIC) units typically used in a conventional architecture. A split-projection least squares (SPLS) signal reconstruction algorithm is applied that replaces high-cost nonlinear signal recovery with a series of low-complexity and independent linear problems. Experiments with measured ultrasound data demonstrate the proposed ACB architecture, and the SPLS reconstruction algorithm achieves 9-fold data compression compared with Nyquist sampling.

High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-ends and subsequent digital signal processing is a major issue. This paper presents a 64-way 6 bit 10 GS/s time-interleaved successive-approximation-based ADC front-end that efficiently incorporates a two-tap embedded FFE and a one-tap embedded DFE, providing the potential for a lower complexity back-end DSP and/or decreased ADC resolution. Fabricated in a 1.1V GP 65nm CMOS process, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33 mm 2 core ADC area. The effectiveness of the embedded FFE and DFE is demonstrated with significant timing margin improvement observed for 10 Gb/s operation over several FR4 channels.

ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER=10-9. Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm 2 area.

Cognitive radio requires power spectral density (PSD) estimation in order to detect the inactive bands for opportunistic secondary usage. In this paper, we present a new compressed power spectral estimation scheme via group-based total variation minimization. Leveraging the intra-group total variation penalty, piecewise-constant characteristics in the signal power spectrum are modeled to improve accuracy of estimation. The effectiveness of the proposed technique is illustrated using simulation of complex baseband OFDM signals. The results show that the proposed scheme has lower power spectral estimation error at the same compressed sampling rate and signal-to-noise ratio compared to previous state of the art compressive spectrum sensing methods.

Compressive sensing (CS) is a promising technique that enables sub-Nyquist sampling, while still guaranteeing the reliable signal recovery. However, existing mixed-signal CS front-end implementation schemes often suffer from high power consumption and nonlinearity. This paper presents a digital-assisted asynchronous compressive sensing (DACS) front-end which offers lower power and higher reconstruction performance relative to the conventional CS-based approaches. The front-end architecture leverages a continuous-time ternary encoding scheme which modulates amplitude variation to ternary timing information. Power is optimized by employing digital-assisted modules in the front-end circuit and a part-time operation strategy for high-power modules. An S-member Group-based Total Variation (S -GTV) algorithm is proposed for the sparse reconstruction of piecewise-constant signals. By including both the inter-group and intra-group total variation, the S-GTV scheme outperforms the conventional TV-based methods in terms of faster convergence rate and better sparse reconstruction performance. Analyses and simulations with a typical ECG recording system confirm that the proposed DACS front-end outperforms a conventional CS-based front-end using a random demodulator in terms of lower power consumption, higher recovery performance, and more system flexibility.

This paper presents a sub-Nyquist rate data acquisition front-end based on compressive sensing theory. The front-end randomizes a sparse input signal by mixing it with pseudo-random number sequences, followed by analog-to-digital converter sampling at sub-Nyquist rate. The signal is then reconstructed using an L1-based optimization algorithm that exploits the signal sparsity to reconstruct the signal with high fidelity. The reconstruction is based on a priori signal model information, such as a multi-tone frequency-sparse model which matches the input signal frequency support. Wideband multi-tone test signals with 4% sparsity in 5~500 MHz band were used to experimentally verify the front-end performance. Single-tone and multi-tone tests show maximum signal to noise and distortion ratios of 40 dB and 30 dB, respectively, with an equivalent sampling rate of 1 GS/s. The analog front-end was fabricated in a 90 nm complementary metal-oxide-semiconductor process and consumes 55 mW. The front-end core occupies 0.93 mm2.

The increasing demand for integrating multiple wireless services in one multi-standard handset, exemplified by the software-defined radio (SDR) model, calls for digitizing wireless receivers in a quest for flexibility. Radio-frequency (RF) front-end and analog baseband filters need to be exchanged for digital processing at the expense of a highly challenging analog-to-digital converter (ADC) specifications. In this paper, the sensitivities of continuous-time (CT) delta-sigma (ΔΣ) ADCs, which are candidate architectures for multi-standard receivers and SDRs, to out-of-band (OOB) blockers at the ADC input are investigated. This analysis addresses the problems and performance limitations that can result from large OOB blockers appearing at the input of CT ΔΣ modulators in a digitized multi-standard receiver. Analysis and discussions given in different sections of the paper are verified by CT system-level simulations.

A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40×) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 μm × 800 μm in 0.13 μm CMOS.

A wideband low-noise amplifier (LNA), which is a key block in the design of broadband receivers for multiband wireless communication standards, is presented in this paper. The LNA is a fully differential common-gate structure. It uses multiple feedback paths, which add degrees of freedom in the choice of the LNA transconductance to reduce the noise figure (NF) and increase the amplification. The proposed LNA avoids the use of bulky inductors that leads to area and cost saving. A prototype is implemented in IBM 90-nm CMOS technology. It covers the frequency range of 100 MHz to 1.77 GHz. The core consumes 2.8 mW from a 2-V supply occupying an area of 0.03 mm2. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB, while the average NF is 2 dB across the whole band. The LNA achieves a return loss greater than 10 dB across the entire band and a third-order input intercept point IIP3 of - 2.85 dBm at the maximum gain frequency.

This paper presents a sub-Nyquist rate sampling receiver architecture that exploits signal sparsity by employing compressive sensing (CS) techniques. The receiver serves as an analog-to-information conversion system that works at sampling rates much lower than the Nyquist rate. A parallel-path structure that employs current mode sampling techniques is used. The receiver performance is quantified analytically. Useful and fundamental design guidelines that are unique to CS are provided based on the analytical tools. Simulations with a 90-nm CMOS process verify the theoretical derivations and the circuit implementations. Based on these results, it is shown that an instantaneous receiver signal bandwidth of 1.5 GHz and a signal-to-noise-plus-distortion ratio of 44 dB are achievable. The receiver power consumption is estimated to be 120.8 mW. A comparison with state-of-the-art high-speed analog-to-digital conversions reveals that the proposed approach improves the figure of merit by a factor of three if the signal exhibits a 4% sparsity.

Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5 prmss clock jitter. In comparison, existing architectures based on time-interleaving require 0.5 prmss clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband-communication-receiver development and provides the potential to enable several high-data-rate communication applications.

Nonlinearities in transmitter circuits, such as power amplifiers, cause degradation in system performance and adjacent-channel spectral growth interference. Polyphase multipath is considered among the techniques that can compensate the nonlinearities, creating a clean output spectrum. However, the polyphase technique requires analog phase shifters that consume considerable power. Aiming at reducing the power consumption, this brief presents a novel multiphase multipath technique with digital phase shifters. The technique is capable of canceling most of the harmonic and intermodulation products produced by a current-output nonlinear circuit to achieve the required linearity. The proposed system has advantages over existing polyphase techniques in power consumption, accuracy, and flexibility. However, it lacks image rejection and local oscillator harmonic cancellation. Detailed analyses and simulations of the new technique are provided to show the effectiveness of the harmonic distortion cancellation.

This paper presents a wideband common-gate (CG) LNA architecture that overcomes the fundamental tradeoff between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure (NF) over the previously reported feedback amplifiers in a CG configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. An amplifier prototype was realized in 0.18-μm CMOS, operates from 1.05 to 3.05 GHz, and dissipates 12.6 mW from 1.8-V supply while occupying a 0.073-mm2 active area. The LNA provides 16.9-dB maximum voltage gain, 2.57-dB minimum NF, better than - 10-dB input matching, and - 0.7-dBm minimum IIP3 across the entire bandwidth.

A novel technique to reduce die area on a discrete-time sinc2↓2 filter for charge sampling is proposed. An SNR comparison of the conventional and the proposed topology reveals that the new technique saves 25% die area occupied by the sampling capacitors of the filter. The idea is also extended to implement higher downsampling factors, and greater percentage of area is saved as the downsampling factor is increased. The proposed filter also has the topological advantage over previously reported works of allowing the designers to use active integration to charge the capacitance, which is critical in obtaining high linearity.

Transform-domain (TD) receivers expand the received signal over a basis set, and then operate on the basis coefficients. An analog computation of the basis coefficients efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate. Frequency-domain (FD) sampling, as a special case of TD sampling, has been proposed to parallelize the sampling process in broad-band communication receivers. The flexibility and scalability of TD receivers allow for the design of receivers that can cope with a large range of narrow-band and broad-band communications standards. A theoretical TD receiver design example is provided which is capable of processing GSM, Bluetooth, IEEE802.11g, Wimax, and UWB in just one configurable front-end. An example of spectrum sensing in cognitive radio is also provided.

ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1-3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major concern for wireline receiver applications [3]. In this work, a hybrid ADC-based receiver architecture is presented that introduces innovations in both the ADC and the digital equalizer design. First, an analog 3-tap feed-forward equalizer (FFE) is efficiently embedded into a 6b time-interleaved SAR ADC, allowing for reductions in both ADC resolution and digital equalizer complexity. Second, significant power reduction is achieved by detecting reliable symbols at the ADC output and dynamically enabling/disabling the digital equalizer.

This paper presents a mixed-signal frequency-domain implementation of the autocorrelation receiver used in the detection of ultra-wideband communication signals that are modulated with transmitted-reference signaling. The digital receiver architecture is based on samples provided by an analog-to-digital converter (ADC) in the frequency domain. Among the advantages of the new receiver are the relaxation of the conversion speed achieved by the inherent parallel architecture of the frequency-domain ADC and the flexibility and simplicity of an all-digital receiver architecture that follows the mixed-signal ADC radio front-end. The paper provides the symbol detection formulas and the corresponding system implementation and makes comparisons with the conventional time-domain implementations. Additionally, a time synchronization technique for the new receiver structure is proposed, which makes the receiver insensitive to any time offset at the pulse level. Furthermore, as a particular case of great practical interest, we consider a single bit for the ADC implementation, and we show with experimental results that the resultant frequency-domain mono-bit digital receiver provides a performance gain that increases with the number of frequency samples, when compared with its time-domain counterpart.

This paper introduces a multicarrier communication receiver for broadband applications based on analog to digital conversion (ADC) of the received signal in the frequency domain. The samples of the spectrum of the received signal are used in the digital receiver to estimate the transmitted symbols through a matched filter operation in the discrete frequency domain. The proposed receiver is aimed at the reception of high information rates in a multicarrier signal with very large bandwidth. Thus, the receiver architecture provides a solution to some of the challenging problems found in the implementation of conventional wideband multicarrier receivers based on time-domain ADC, since It efficiently parallelizes the A/D conversion reducing the sampling speed requirements. We show that the sampling rate requirements are relaxed as the number of frequency samples is increased, which introduces a trade-off between complexity and sampling rate. The new receiver possesses additional advantages, including scalability with increasing frequency samples, the possibility of optimally allocating the available number of bits for the ATD conversion across the frequency domain samples which potentially reduces the distortion introduced by the high-speed ADC, narrowband interference suppression that can be directly carried out in the frequency domain, and inherent robustness to frequency offset which makes it an attractive solution when compared with traditional multicarrier receivers. We also investigate how the proposed receiver responds to common multicarrier communication receiver problems such as phase noise and channel frequency selectivity.

Ultrawideband systems employ short low-power pulses. Analog receiver designs can accommodate the required bandwidths, but they come at a cost of reduced flexibility. Digital approaches, on the other hand, provide flexibility in receiver signal processing but are limited by analog-to-digital converter (ADC) resolution and power consumption. In this paper, we consider reduced complexity digital receivers, in which the ADC is limited to a single bit per sample. We study three one-bit ADC schemes: 1) fixed reference; 2) stochastic reference; and 3) sigma-delta modulation (SDM). These are compared for two types of receivers based on: 1) matched filtering; and 2) transmitted reference. Bit-error rate (BER) expressions are developed for these systems and compared to full-resolution implementations with negligible quantization error. The analysis includes the impact of quantization noise, filtering, and oversampling. In particular, for an additive white Gaussian noise channel, we show that the SDM scheme with oversampling can achieve the BER performance of a full-resolution digital receiver.

Some proposed high speed wireline communications make use of an ADC front end to allow a feedforward equalizer (FFE) to compensate for the frequency dependent loss of the channel. High precision ADCs are expensive in terms of power. The FFE block performs multiplication and addition operations at high speed and further increases the power consumption. This paper proposes a simple forward error correction method by which the ADC resolution and the equalizer complexity can be reduced. A single parity check code implemented together with a threshold detector can provide single error correction capability. With this error correction capability, the number of taps required in the FFE block is shown to be reduced to 3 taps from 6 taps for a channel with 15dB insertion loss at 5GHz frequency with the data rate being 20Gb/s. The effective number of bits (ENOB) required from the ADC is also shown to reduce to about 3.5 bits from 6 bits. The high rate of the code and the very simple decoder architecture make this error correction mechanism well suited for the wireline application.

This paper develops metastability error models for flash and asynchronous SAR ADCs and describes a novel ADC-based receiver statistical modeling methodology to analyze the BER performance impact of metastability error propagation through digital FFE equalization.

The conventional analog-to-digital conversion (ADC) and digital signal processing (DSP) architecture has led to major advances in miniature and micro-systems technology over the past several decades. The outlook for these systems is significantly enhanced by advances in sensing, signal processing, communications and control, and the combination of these technologies enables autonomous robotics on the miniature to micro scales. In this article we look at trends in the combination of analog and digital (mixed-signal) processing, and consider a generalized sampling architecture. Employing a parallel analog basis expansion of the input signal, this scalable approach is adaptable and reconfigurable, and is suitable for a large variety of current and future applications in networking, perception, cognition, and control.

This paper presents a low-power asynchronous compressive sensing (ACS) front-end scheme that allows the coexistence of radar and wireless systems. The analog front-end architecture introduces one major system advantage needed in an interference-robust wideband radar: multiple parallel signal processing channels capable of rejecting inband interference and handling large data volume at the analog-to-digital converters output. This advantage is offered by a filter-bank parallel ACS receiver that filters out undesired interference and exploits the sparsity of radar pulsed signals in a scattered environment. Numerical simulations on a vehicle-to-vehicle collision avoidance radar system with in-band wireless interference demonstrate the proposed radar receiver is robust to in-band interference, and achieves 6-fold data volume compression compared with Nyquist sampling.

Next-generation Wireless Body Sensor Networks (WBSNs) calls for miniaturization and power-efficient integration for long-term monitoring, real-time diagnostics and patient-centered healthcare solutions. However, state-of-the-art WBSN prototypes remain challenged by stringent power constraints and large form factors. The recently proposed asynchronous compressive sensing scheme suggests an efficient way to improve power consumption by reducing the data volume in energy-hungry radio links. In this paper, we present a modified front-end called Asynchronous Binary Compressive Sensing (ABCS) for WBSNs. A low-cost reconstruction method is proposed that exploits the embedded binary signal structure in the ABCS. By incorporating binary amplitude as a prior, better signal recovery performance is obtained comparing with the traditional approaches. Analyses and simulations with an ECG recording confirm the ABCS front-end outperforms the conventional CS approaches in terms of hardware complexity, power consumption and system flexibility.

A calibration technique for Noise Transfer Function (NTF) optimization of Continuous-Time Sigma Delta (CT \( \Upsigma \Updelta \)) modulators is presented. This technique employs a test tone applied at the input of the quantizer to evaluate the noise transfer function of the \( \Upsigma \Updelta \) modulator using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed-mode systems. Once the modulator’s output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal-to-Quantization Noise Ratio (SQNR) performance is extracted via an LMS software-based algorithm. This approach uses a simple test signature to measure both in-band and out-of-band loop behavior.

The traditional Nyquist sampling architecture does not provide a feasible solution in a large multi-channel ultrasound imaging system. The main issues are the huge data volume after the analog-to-digital interface, high power consumption, and circuit complexity at both the front-end and mid-end. This paper presents a Compressed Digital Beamformer (CDB) framework for the design of an ultrasound imaging system with a large transducer array (≥ 1024) operating at a moderate carrier frequency (≥ 5 MHz). Simulations demonstrate that the proposed CDB framework achieves a Compression Ratio (CR) of 0.1 and Mean Square Error (MSE) of -27.7 dB with 4 quantization bits.

In this paper we present an asynchronous compressive sensing front-end for radar systems. By using a continuous-time ternary encoding scheme (CT-TE), the amplitude variations on radar pulses are converted into timing information. The oversampling architecture mitigates the quantization error and improves time-delay estimation accuracy. The high data volume resulting from oversampling is reduced by using compressive sensing (CS) in the digital domain. Moreover, the high power consumption of randomization in an analog CS front-end is avoided in the proposed asynchronous scheme by using a part-time operation strategy in the most power demanding modules. Simulations show that the proposed scheme achieves a better range accuracy and probability of detection at sub-Nyquist rate compared to a conventional system that uses oversampling ADCs.

The quest for higher data rates in state-of-the-art wireless standards and services calls for wideband and high-resolution data-converters in wireless transceivers. While modern integrated circuits (IC) technologies provide high cut-off frequencies ( ) for transistors and hence allow the operation at higher speeds, the main limitation against increasing speed of operation of data-converters is the problem of clock-jitter. Clock-jitter is a common problem associated with clock generators due to uncertainty in the timing of the clock edges caused by the finite phase-noise (PN) in the generated clock waveform. Particularly, noise components induced by several noise sources in the system providing the clock (e.g. phaselocked loop, PLL) add to the clock waveform and cause uncertainty in the timing of the zero-crossing instants from cycle to cycle. Figure 1 shows a survey chart of the analog-todigital converter (ADC) implementations reported in IEEE International solid-state circuits conference (ISSCC) and VLSI Symposium since 1997 [1]. The straight lines show the limitation on the achievable signal-to-noise ratio (SNR) by clock-jitter for jitter root-mean square (rms) values of 1ps and 0.1ps. As can be seen from the chart, the performance of most ADCs falls below the line corresponding to 1ps rms jitter, few ADCs reside in the range between 1ps and 0.1ps, and almost all ADC implementations reported so far are beyond the 0.1ps rms jitter line. This means that the main limitation on increasing the ADC performance in terms of SNR and speed is the specification on the clock-jitter of 0.1ps.

Serial link receivers with ADC front-ends are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6b 1.6GS/s ADC with a novel embedded DFE structure. Leveraging a time-interleaved SAR ADC architecture, a redundant cycle loop-unrolled technique is proposed in order to relax the DFE feedback critical path delay with low power/area overhead. Fabricated in an LP 90nm CMOS process, the 6b ADC with embedded 1-tap DFE consumes 20mW total power, including front-end T/Hs and reference buffers, and the core time-interleaved ADC occupies 0.24mm2 area.

This paper investigates the sensitivity of continuous-time (CT) delta-sigma analog-to-digital converters (ADCs), candidate architectures for multi-standard and software-defined radio receivers, to feedback pulse-width jitter (PWJ) in presence of blocker signals received at the ADC input. A comparison between delta-sigma modulators with feedforward (FF) and feedback (FB) loop filter structures in terms of robustness to digital-to-analog converter (DAC) PWJ, in presence of blockers, is performed. Analysis and discussions developed in the paper are verified by CT simulations in Matlab/Simulink® and simulations results show good agreement with the theoretical expectations. It is shown that the PWJ induced errors due to out-of-band (OOB) blockers in the feedback path dominate the total in-band noise power (IBN) in FF delta-sigma structures and can cause a reduction in the achievable dynamic range that can be as large as 12 dB (2 bits of resolution) in case of using a non-return-to-zero DAC waveform. On the other hand, for same blocker levels at the modulator input, PWJ induced errors caused by OOB blockers have negligible contribution to the IBN in FB structures, owing to their stronger low-pass filtering characteristic and hence higher attenuation of OOB blockers.

Wideband spectrum sensing for cognitive radios requires very demanding analog-to-digital conversion (ADC) speed and dynamic range. In this paper, a mixed-signal parallel compressive sensing architecture is developed to realize wideband spectrum sensing for cognitive radios at sub-Nqyuist rates by exploiting the sparsity in current frequency usage. Overlapping windowed integrators are used for analog basis expansion, that provides flexible filter nulls for clock leakage spur rejection. A low-speed experimental system, built with off-the-shelf components, is presented. The impact of circuit nonidealities is considered in detail, providing insight for a future integrated circuit implementation.

We propose a novel parallel mixed-signal compressive spectrum sensing architecture for Cognitive Radios (CRs) with a detailed study of the signal modeling. The mixed-signal compressive sensing is realized with a parallel segmented compressive sensing (PSCS) architecture, which not only can filter out all the harmonic spurs that leak from the local random generator, but also provides a tradeoff between the sampling rate and the system complexity such that a practical hardware implementation is possible. We consider application of the architecture to do spectrum estimation, which is the first step for spectrum sensing in CRs. The benefit of prior knowledge about the input signal's structure is explored and it is shown that this can be exploited in the PSCS architecture to greatly reduce the sampling rate.

Analog Compressive Sensing (CS) provides a novel strategy to sample and process wideband sparse signals at sub-Nyquist rate. This scheme exploits the signal sparsity to reduce the sampling rate requirements. The analog compressive sensing system performance is greatly impacted by the accuracy of analog circuit components, especially with the scaling of CMOS technology. In this paper, the effect of the circuit imperfections in the analog compressive sensing architecture based on Parallel Segmented Compressive Sensing (PSCS) is discussed, such as the finite settling time, the timing uncertainty and so on. An iterative background calibration algorithm based on LMS (Least Mean Square) is proposed, which is shown to be able to effectively calibrate the error due to the circuit nonideal factors.

A low-power wideband divide-by-odd-ratio ring-oscillator-based complementary-injection-locked frequency divider (CILFD) is proposed. The multiple-input complementary-injection scheme widens its locking range over 100% to sufficiently cover the PVT variations. The CILFD consumes dynamic power only with no additional power penalty for larger division ratios. The differential input and output are realized employing auxiliary cross-connected inverters. The CILFDs with division ratios of 3 and 7 are implemented in a 0.18 µm CMOS technology. The measurement results show a locking range from 1.4 to 4.4 GHz with an input incident power of −4 dBm. The power consumption while locked at 4.7 GHz is 0.9 mW from a single 1.8-V power supply.

In this paper a two stage CMOS Radio Frequency (RF) low noise transconductance amplifier is proposed. The feed-forward noise-cancelling technique is exploited to improve the Noise Figure (NF). Simulations with 45 nm CMOS process have been performed to verify the proposed design. The LNA achieves a transconductance of 115 mS, -3 dB bandwidth of 4.5 GHz, NF of 3.4 dB and IIP3 of -10 dBm. Compared to the single stage transconductance amplifier, the in band NF improves by 3.3 dB. The power consumption is 40 mW.

Operating at sub-Nyquist rate, compressed sensing (CS) has been successfully applied to the design of impulse ultra-wideband (I-UWB) receivers where Nyquist sampling is a formidable challenge. However, strong narrowband interference (NBI) can easily jam and saturate the receiver front-end and greatly degrade the system performance. In this paper, CS is applied to the design of I-UWB receivers with NBI mitigation. By exploiting the sparsity of the NBI within the pulse UWB spectrum, a compressive measurement matrix can be designed that is not only efficient at collecting signal energy, but also nulls out the NBI effectively. The performance analysis of the proposed receiver is provided. Simulation results show the effectiveness of the proposed method for UWB signal detection and NBI mitigation.

A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (8.9 ps rms @ 600 MHz) and tracks PVT variations. The DLL consumes 20 mW and occupies a 470 mum X 800 mum area in 0.13mum CMOS.

A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW.

A parallel structure to do spectrum sensing in cognitive radio (CR) at sub-Nyquist rate is proposed. The structure is based on compressed sensing (CS) that exploits the sparsity of frequency utilization. Specifically, the received analog signal is segmented or time-windowed and CS is applied to each segment independently using an analog implementation of the inner product, then all the samples are processed together to reconstruct the signal. Applying the CS framework to the analog signal directly relaxes the requirements in wideband RF receiver front-ends. Moreover, the parallel structure provides a design flexibility and scalability on the sensing rate and system complexity. This paper also provides a joint reconstruction algorithm that optimally detects the information symbols from the sub-Nyquist analog projection coefficients. Simulations showing the efficiency of the proposed approach are also presented.

Transform domain (TD) sampling is presented as an inexpensive and feasible solution for software defined receivers that operate on a very wide frequency spectrum. TD receivers expand the received signal over a basis set, and then operate on the basis coefficients. An analog computation of the basis coefficients efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate. Frequency domain (FD) sampling, as a special case of transform-domain sampling, has been proposed to parallelize the sampling process in wideband receivers. The proposed receiver makes use of a windowed integrator to perform charge sampling, which provides inherent anti-aliasing. More complex decimation filters with stronger attenuation of the unwanted channels are easily obtained from the simple integrator and can be exploited in designing a multi-standard receiver. The flexibility and scalability of TD receivers allow for the design of software radios that can operate on a large range of narrowband and wideband communications standards. A "dreamed software- defined-radio" TD receiver design example is provided which is capable of processing GSM, Bluetooth, IEEE802.11b/g, WiMax and UWB in a single reconfigurable frontend.

In the UWB multicarrier receiver, after analog to digital conversion (ADC), the samples of the spectrum of the received signal are used in the digital receiver to estimate the transmitted symbols through a matched filter operation in the discrete frequency domain. The proposed receiver is aimed at the reception of high information rates in a multicarrier signal with very large bandwidth. Thus, the receiver architecture provides a solution to some of the challenging problems found in the implementation of conventional wideband multicarrier receivers based on time-domain ADC, since it parallelizes the A/D conversion, reducing the sampling rate. The receiver is also directly applicable to multicarrier ultra-wideband communication receivers. Additional advantages of the proposed receiver include the possibility of optimally allocating the available number of bits for the A/D conversion across the frequency domain samples, narrowband interference suppression that can be directly carried out in the frequency domain, and inherent robustness to frequency offset which makes it an attractive solution when compared with traditional multicarrier receivers.

Weighted median (WM) filtering structures for complex-valued samples have been proposed but none of them allows the use of complex-valued weights. This paper defines complex-valued weighting for median filters with complex-valued input samples. Two different approaches to the handling of weights in the complex domain are presented, both derived from characteristics of complex-valued linear filters, resulting in two definitions of the complex weighted median filter. The LMS optimizations of the proposed filtering schemes are also presented. Simulations are shown illustrating the performance of the new complex WM filter structures compared with previous approaches to the problem and with classical linear filters.

The paper introduces techniques to perform analog-to-digital (A/D) conversion, based on the quantization of the coefficients obtained by the projection of a continuous-time signal over an orthogonal space. This framework for A/D conversion is motivated by the sampling of an input signal in domains which may lead to lower levels of signal distortion and significantly less demanding A/D conversion characteristics. The A/D conversion distortion is reduced by assigning optimal bit rates according to the variance distribution of the coefficients. Moreover, since the quantization of the coefficients is realized at the end of a time window during which the signal is projected, the speed of the quantizers can be much lower than the one needed in conventional time-domain ADCs. In particular, we study ADC in the frequency domain which overcomes some of the difficulties encountered with conventional time-domain A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals.

This paper introduces novel techniques to perform analog to digital (AJD) conversion, based on the quantization of the coefficients obtained by the projection of a continuous-time signal over an orthogonal space. The new A/D techniques proposed here are motivated by the sampling of the input signal in domains which may lead to lower levels of signal distortion and significantly less demanding A/D conversion characteristics. As a particular case, we study A/D conversion in the frequency domain where samples of the signal spectrum are taken such that no time-aliasing occurs in the discrete-time version of the signal. We show that the frequency domain analog to digital converter (ADC) overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The discrete frequency samples are then passed through a vector quantizer with relaxed characteristics, operating over DC levels that change with a speed that is much lower than that required for time-domain A/D conversion. Fundamental figures of merit in A/D conversion and important system trade-offs are discussed for the proposed frequency domain ADC. As an example of this approach, we consider a multi-carrier UWB communications scheme.

Ultra-wideband (UWB) systems employ short, low power pulses. Analog receiver designs can accommodate the required bandwidths, but come at a cost of reduced flexibility. Digital approaches, on the other hand, provide flexibility in receiver signal processing but are limited by analog-to-digital (ADC) resolution and power consumption. In this paper we consider reduced complexity digital receivers, in which the ADC is limited to a single bit per sample. We study three one-bit ADC schemes: fixed reference, stochastic reference, and sigma-delta modulation (SDM). These are compared for two types of receivers based on (i) matched filtering, and (ii) a transmitted-reference. Bit error rate (BER) expressions are developed for these systems, and compared to full resolution implementations with negligible quantization error. The analysis includes the impact of quantization noise, filtering, and oversampling. In particular, for an additive white Gaussian noise channel, we show that the SDM scheme with oversampling can achieve the BER performance of a full resolution digital receiver.

This paper presents a data estimation scheme for wide band multichannel charge sampling filter bank receivers together with a complete system calibration algorithm based on the least mean squared (LMS) algorithm. A unified model has been defined for the receiver containing all first order mismatches, offsets, imperfections, and the LMS algorithm is employed to track these errors. The performance of this technique under noisy channel conditions has been verified. Moreover, a detailed complexity analysis of the calibration algorithm is provided which shows that sinc filter banks have much lower complexity than traditional continuous-time filter banks.