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In this paper, temporal gas temperature in plasma was measured by Rayleigh scattering in a passive way since synchronization was difficult due to the randomness of current pulses. The plasma was generated between a 10 mm pin-to-plane gap connected to a H.V DC voltage through a 130 MΩ resistor and a skin sample was placed on a grounded plate. Even the plasma can be touched by a human hand without any feeling of warmth, the peak temperature could be 337 K then decrease to 295 K over 60 μs at 1 mm. Moreover, the applied voltage dramatically affects peak current and the peak temperature. Therefore, the transient “high” temperature cannot be touched and the so-called “cold” plasma might not be “cold”.

In this article, a novel circuit is proposed to synthesize absorption common-mode filters (A-CMFs) in only one stage, which can be implemented with different kinds of transmission lines. This proposed one-stage absorption circuit has been derived with analytical equations, and design formulas are found to determine circuit parameters. To validate the proposed circuit and derived formulas, an intuitional structure composed of a meander slotline (MSL), a straight differential pair, and one resistor is proposed. Moreover, a technique named meander asymmetrical coplanar strip (MACPS) has also been developed to reduce the size of MSL-type A-CMF by up to 26%. Finally, the proposed test sample of MACPS-type A-CMF is fabricated in a two-layer printed circuit board (PCB) and measured. The common-mode (CM) noise absorption efficiency of above 80% can be obtained from 2.33 to 2.67 GHz to eliminate CM noises in the Wi-Fi 2.4 GHz band. Besides, the MACPS-type A-CMF provides an excellent differential-mode (DM) signal integrity. The −3 dB bandwidth of DM insertion loss can reach 7.5 GHz, and the measured eye diagram of the proposed work is identical to that of the reference board even the transmitted data rate is up to 16 Gb/s. To our best knowledge, the smallest A-CMF implemented in a two-layer PCB is achieved in this article with the electrical dimension being only 0.0358 λg2.

In this brief, a novel pseudo-differential low-transconductance amplifier is proposed based on the bootstrapping technique. The transconductor is implemented using two voltage follower topologies as amplifiers with their outputs connected to both terminals of a resistor, thus bootstrapping the voltages at these terminals to increase the equivalent resistance value, and achieve a very low transconductance without the need for large passive components. In this way, a highly-linear compact structure is designed whose transconductance can be tuned by external current sources. The circuit was fabricated in a standard 0.18μm CMOS process. The experimental results show a tunable transconductance in the range of tens of nA/V, with a total harmonic distortion lower than -40dB at 350mVpp@1kHz. The power consumption of the amplifier is 4μW under a 1.8V supply voltage. This work was supported by CONACYT through the Doctoral Grant 467255 and the Research Project CONACYT CB-2015-257985

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 GΩ and 700 GΩ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz.

A novel quasi-reflectionless bandpass filter (BPF) using double-sided parallel-strip line (DSPSL) is proposed in this letter. It is composed of a BPF and two symmetric absorptive bandstop filters (ABSFs) terminated by a pair of resistors that can dissipate the input untransmitted signal energy. Through detailed analysis, the high characteristic impedance is required for the open-circuited stubs of the ABSFs to enhance the selectivity. This cannot be realized in traditional microstrip designs, but it can be obtained easily by offsetting the DSPSL. Meanwhile, the BPF with T-shaped structure consists of a half-wavelength (λ/2) DSPSL with a centrally-loaded λ/2 stub, which answers for generating two transmission zeros (TZs) to achieve better out-of-band suppression. For demonstration, a prototype is designed, fabricated and measured, and the simulated and measured results with good agreement are presented.

In this letter, a compact bandpass filtering power divider with tunable bandwidth based on spoof surface plasmon polaritons (SSPPs) and substrate integrated waveguide (SIW) is proposed. The hybrid-SIW-SSPP structure shows good potential to expand the scope of bandwidth control of the device. The bandwidth can be designed in a wide range by simply optimizing its dimensions or loading interdigital structures (ISs). Defected ground structure (DGS) is also introduced on the bottom layer to further improve the out-of-band suppression. And good isolation can be obtained via additional resistors welded across the SSPP slot. A prototype loaded with dumbbell-shape DGS and two resistors is fabricated with an overall size of 45 mm x 18 mm x 0.5 mm. Both $S_{21}$ and $S_{31}$ are around -3.8 dB within the whole X-band. The simulated and measured results agree with each other well.

In this article, a novel wideband bandpass power divider (PD) with out-of-band multi-transmission zeros (TZs) is presented. It consists of 2M shunted short-circuited stubs (SCSs), (M + N) cascaded coupled line sections, and ( $M + N - K_{N)$ isolation resistors. There are two types of topologies, and the number of TZs is solely determined by N. Through even- and odd-mode analyses, general simultaneous equations for characteristic impedances, coupling strengths, and isolation resistors are derived with the proposed algorithm. By suitably selecting all the design parameters, all the S-parameters (S₁₁, S₂₁ = S₃₁, S₂₂ = S₃₃, and S₃₂) of the proposed topology could provide an equal-ripple response with controllable ripple level in the passband. For a given fractional bandwidth (FBW), TZs and out-of-band rejection level can be designed independently. For further optimization, several isolation resistors can be omitted with the unchanged performances. For verification, two experimental circuits are fabricated and measured. Good agreement between the measured and simulated results is attained so as to successfully validate the correctness of the proposed design approach.

In this brief, we analyzed the output ripple in a capacitively-coupled chopper-based instrumentation amplifier (CCIA). Our analysis found that the shape and amplitude of the output ripple of the CCIA are determined by five design parameters, namely amplifier offset, transconductance, chopping frequency, Miller compensation capacitance, and the nulling resistor. With different design specifications, the CCIA ripple appears in four different shapes, including triangular ripple, RC-settling ripple, square ripple, and step-change ripple. These findings are verified by the silicon results. As the cause of each ripple shape varies, this analysis serves as a guideline for designing practical chopper-based amplifiers and their corresponding ripple reduction techniques.

The indium phosphide (InP) 130 nm double-heterojunction bipolar transistor (DHBT) offers milliwatts of output power and high signal amplification in the lower end of the terahertz frequency band when the transistor is used in a common-base configuration. Instrumentation can directly benefit from this technology by enabling the development of novel broadband sources or synthesizers that rely on our ability to amplify the signal over enormous bandwidths. However, the design of high gain and stable amplifiers presents many obstacles and limitations as we increase the bandwidth and the carrier frequency. Here we show that adding a series resistor at the collector terminal of the common-base transistor prevents instabilities in the terahertz monolithic integrated circuit (TMIC) amplifier and increases its fractional bandwidth. Adopting this technique, we report a state-of-the-art broadband common-base amplifier that exhibits a minimum small-signal gain of 18.9 dB from 325 GHz to 477 GHz. This amplifier presents the highest fractional bandwidth and gain above 300 GHz. Our work demonstrates the feasibility of high-performance amplifiers that address the need of future terahertz electronic systems.

A technique to reduce the area of a low-noise sub-sampling PLL (SSPLL) is proposed. The resistor in the loop filter is eliminated. The transconductor driven by the phase detector is switched such that its output consists of a positive and negative pulse with the former wider than the latter. A low frequency zero can thus be realized with a substantially smaller capacitor. Transconductor noise is suppressed to acceptable levels by the high phase-detector gain. In applications that require low out-of-band phase noise, the capacitance can be reduced by 25x or more with typical PLL parameters. A prototype SSPLL from 24.4 GHz-29.2 GHz with a 50 MHz reference clock and bandwidth of 1MHz in 65nm LP CMOS process uses a loop filter capacitance of only 5pF. The conventional topology would require 38pF for the same integrated jitter. The in-band phase noise at 1MHz offset ranges from -90 to -95dBc/Hz, and the out-of-band phase noise at 10 MHz offset ranges from -117 to -121dBc/Hz. The jitter integrated from 10kHz to 50MHz is 330-390fs. It consumes 18.2mW, exhibiting a minimum FoM of 235dB over the frequency range. The SSPLL occupies an area of only 0.14mm².

A differential four-way power divider for 24 to 30 GHz and a frequency reconfigurable differential four-way power divider for 24 to 30 GHz and 37 to 43.5 GHz are presented. The differential structure provides sound virtual grounds in a multiple-channel chip. Both circuits have a four-way Wilkinson power divider (WPD) configuration based on lumped elements that provide small chip sizes. The first one has a small core chip area of 0.09 mm², a small insertion loss of 0.93 to 1.94 dB, and the port-to-port isolation of 19.1 to 25.6 dB from 24 to 30 GHz. It has a small amplitude and phase differences at four outputs. The second one allows frequency-reconfigurable operation by switching inductances and capacitances to cover widely separated frequency bands (5G NR n257-n261 bands). In addition, switched capacitors (SCs) are inserted to resonate out the parasitic series inductances in isolation resistors at both bands of 24-30 GHz and 37-43.5 GHz. It has a core chip area of 0.168 mm², insertion losses of 1.65-1.89 dB at 24 to 30 GHz and 2.04-2.70 dB at 37 to 43.5 GHz, respectively. The port-to-port isolations are 23.4-37.6 dB at 24 to 30 GHz and 22.6-28.4 dB at 37 to 43.5 GHz.

The multilevel connected dc–dc converters system is considered a practical technology to increase the capacity and reduce voltage and current stresses on the power devices. In practice, mismatched parameters are inevitable, which increase the challenge of output voltage regulation and current sharing control. In order to conquer these difficulties, this article investigates the current sharing based on incremental passivity control for multilevel connected dc–dc converters. Combined with passivity-based control, a finite-time estimator is given to improve the robustness against the load variations. The proposed method results in a linear control law despite the bilinear nature of this system. Moreover, analysis exhibits that stability and current sharing are independent of inductor parameters. Furthermore, stability of the closed-loop system has been proved that the proposed approach is valid both for a linear and nonlinear load. After introducing the proposed control scheme, simulation and experiments are offered to validate its fast transit response and antidisturbance performance.

The study presents the pyroelectric performance improvement by employing exhaust emissions from automobiles. Electric outputs through the material BaSn0.05Ti0.95O3 are recorded after subjecting the surface of the sample for heating under infrared (IR) lamp and flowing water. The thickness of the automobile exhaust ink was nearly 35 µm on the sample surface. Observations show significant improvements with open circuit voltage increase to five times, electric current enhances upto six times across the resistor of 10 Ω and nearly 17 times increment in energy harvested. Peak values of open circuit voltage obtained were 0.3 and 1.2 V for uncoated as well as coated samples respectively. The electric current for the heating & cooling cycle represents peak value of 1.47 µA when compared with uncoated sample with a value of 0.24 µA. Moreover, energy stored across capacitor of10 µF founds an increment from 1.4 µJ for uncoated sample to 23.10 µJ for coated sample. The study proposes effective utilization of harmful automobile exhaust and harvesting of energy for low power electronics. Therefore this study systematically investigates the pyroelectric energy potential of BaSn0.05Ti0.95O3 ceramics by using automobile emission and compares it with similar class of materials.

Recent developments in electronics has led to an increase in fabrication and assembly speeds of printed circuit boards (PCBs). In addition, the size of manufactured PCBs and electronic components (e.g. resistors, capacitors, transistors etc.) are becoming much smaller. By increased demand and production speed, the reliability and thus the inspection of manufactured PCB assemblies became an important issue. In the assembly PCB production process, detection of surface mount technology (SMT) solder defects is made with automatic optical inspection (AOI) devices using image processing methods. Besides these expensive device methods, the method by which the controls are made by the operators visually is a low-cost solution used by most of the companies that manufacture printed circuit board assembly. In addition, circuit defects and solder defects cannot be tested and controlled with 100% accuracy due to human error. This paper proposes to detect solder joint defects with machine learning methods using YOLO algorithm to speed up time and increase accuracy in assembly PCB production line. Approximately 40000 images were obtained from the real production line before training with the YOLOv4 algorithm for high accuracy rate. Detection of solder defects of SMT circuit elements in approximately 5K (4056x3040) images resolution can be achieved with 97% accuracy in around 4 seconds. As a result of the use of the system, this proposed method has been proven with the reports received from the production line and precision-recall curves. Thus, it has been observed that the production speed and accuracy rate are increased. © 2021 IEEE. Kocaeli University Kocaeli University Technopark

This paper presents a new approach to design filtering power dividers (FPD) with regular triangle patch resonator (RTPR). According to the electric-field (E-field) distributions of the resonator modes, the TM₁₀ and TM₁₁ modes have been selected to realize two- and three-way power dividers respectively, showcasing the flexible characteristic of the RTPR. Afterwards, an in-phase multiway excitation scheme for the RTPR is developed to well excite the designated modes and suppress multiple spurious modes, simultaneously. Subsequently, to further reject the harmonics so as to extend the upper stopband greatly, shorting posts are deployed at the locations with null electric field distribution for the specified operation mode. Ultimately, to validate the design concept, a two-way and a three-way second-order FPD employed at TM₁₀ (f₁₀= 1.27GHz) with fractional bandwidth (FBW) of 7% and at TM₁₁ (f₁₁= 2.2GHz) with FBW of 4.5% are designed and measured. The measured results of the two fabricated circuits well agree with the simulated ones. Results indicate that both of the two FPDs exhibit properties of good port-to-port isolation, high selectivity with transmission zeros near both sides of the passband, as well as wide stopband extended to 3.35 and 2.9 times of fundamental operation frequencies, respectively.

The avalanche transistor-based Marx circuit has great advantages in generating high-voltage nanosecond pulses. The introduction of auxiliary triggering topology (ATT) can reduce the damage probability of transistors in M × N -stage Marx bank circuits (MBCs). However, as the number of modified stages increases, the output voltage drops significantly, which makes it not achievable to adopt ATT at each stage. The transistors in nonmodified stages still have a certain failure rate when operating at a high repetition rate. Moreover, the previous ATT is only applicable in the negative polarity MBC. In this article, an improved ATT is proposed to solve the above problems. First, its operating principle is analyzed, and the feasibility of its application in both negative and positive MBCs is verified by simulations. Then, the effects of the improved ATT on M × N -stage MBCs are experimentally studied, and the results show that the improved ATT can be used in all stages of MBC without reducing the output voltage. It can also reduce the minimum operating voltage of transistors and widen the regulating range of output voltage. In addition, it can improve the synchronous conduction of parallel-connected transistors. Finally, two nanosecond pulse generators with positive and negative polarity, respectively, are developed and used to drive the atmospheric pressure plasma jet. The amplitude of output voltage can be adjusted in the range of 5–10 kV, measuring at the open end of a coaxial cable with 75 Ω impedance, and the maximum repetition rate is up to 7 kHz.

In this brief, novel single-layer dual-band bandpass filters (BPFs) with input-/two-port all-frequency absorptive performance are presented. The design consists of a simple coupled-line (CL) based dual-band BPF section and auxiliary dual-band bandstop filter (BSF) sections with resistively terminated absorptive stubs. The dual-band BPF can transmit spectral energy in two operational passbands with good in-band filtering response, while the out-of-band RF-signal energy can be well absorbed by auxiliary BSF sections shunted at input/output ports, which indicates all-frequency absorption from DC. Besides, the impedance of the absorptive stub and the value of the grounded resistor can be independently adjusted to enhance the absorption performance. Furthermore, the operational foundations and explicit design equations are discussed and derived. Good agreements between the simulated and measured results verify the design theory.

Silicon carbide (SiC) MOSFET exhibits low channel resistance, low junction capacitances, and wider temperature range compared with silicon counterpart. However, the high dv=dt in a bridge-leg connected SiC MOSFETs induce the detrimental coupling noise, increasing device stress and EMI and restricting the converter operation at a high switching frequency. This paper presents two single-supply based variable gate voltage driving (SSVGVD) circuits for SiC MOSFETs to exploit the switching-speed capacity by mitigating the coupling noise during switching transients. Both driver circuits employ a simple auxiliary circuits comprising a transistor, zener diode, and resistor to control the gate voltage of power devices in a bridge-leg configuration. The proposed driver circuit can be easily realized with a driver IC using only positive driver supply, offering a compact, low-cost, and reliable solution. Experimental tests with SiC MOSFETs demonstrate the effectiveness of the SSVGVD gate driver.

In this paper, an integrated low-profile low radar cross section (RCS) circularly polarized (CP) antenna array based on multi-functional modes generation method is proposed, which can realize good in-band radiation performance and wide out-of-band RCS reduction characteristics on the same layer without additional subassembly except resistors. By embedding a resistor in the center of a metallic strip, the half and one and a half wavelength resonant modes are changed into the absorption modes; while the one wavelength resonant mode is excited as the radiation mode when offset feeding at an appropriate location. Furthermore, the CP radiation performance is achieved with four bent and center-rotating-symmetric metallic strip and the sequentially rotated feeding network. The simulation results show that the designed integrated antenna array generates the same left-hand CP radiation performance as the array without embedding resistors, and the monostatic RCS of the array is significantly reduced in the lower and upper bands, with an average reduction value of 10 dB. Prototypes of the designed antenna array with 4×4 elements are fabricated and measured to validate the simulation results.

Conventional di/dt and dv / dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

This article describes how to prevent excessive electricity consumption of lights on the floors at night and automatically turn on the lights after the end of movement, using electricity only when needed.

The purpose of this work is to substantiate the real effectiveness of the proposed active electric power resonant amplifier circuit, represented by a sequence of four inductively coupled active-reactive circuits. The first of them is the input with a source of a harmonic signal to be amplified. The second one generates amplified reactive power in the voltage resonance mode. The third one carries out the output of power from the second circuit without the reverse influence of the amplification processes with an additional third-party voltage source in the current resonance mode. The fourth circuit inductively connected to the third circuit contains an output load - a resistor that simulates the release of amplified active power. The analysis and numericalassessments of the characteristics of the processes in the proposed scheme of the resonant amplifier of active electric power made it possible to substantiate its fundamental capability. Quantitative estimates for the experimental model made it possible to give recommendations on the choice of the parameters of the circuit elements of the resonant amplifier, which has sufficiently high efficiency indicators for low-resistance output active loads.The results obtained are based on the conclusions of a generalized theoretical analysis of electromagnetic processes and numerical estimates for its experimental implementation. The proposed scheme for the resonant amplification of active electric power, the rationale for its fundamental effectiveness, the theory and numerical assessments of the characteristics of the ongoing processes are of practical interest for further experimental studies, as well as for formulating recommendations for the manufacture of operating samples of this proposal are very promising directions. The results of the conducted research are seen as a theoretical search for the conditions for the highest efficiency and an experimental study of electromagnetic processesin the proposed circuit of a resonant amplifier of active electric power., Метою цієї роботи є обґрунтування реальної дієвості запропонованої схеми резонансного підсилювача активноїелектричної потужності, представленої послідовністю з чотирьох індуктивно пов’язаних активно-реактивних контурів. Перший – вхідний із джерелом гармонічного сигналу, що підлягає посиленню. Другий – у режимі резонансу напруг формує посилену реактивну потужність. Третій – з додатковим стороннім джерелом напруги в режимі резонансу струмів здійснює виведення потужності другого контуру без зворотного впливу на процеси посилення.Четвертий контур, індуктивно пов’язаний із третім контуром, містить вихідне навантаження – резистор, що моделює виділення посиленої активної потужності. Проведений аналіз та числові оцінки характеристик протікаючих процесів у запропонованій схемі резонансного підсилювача активної електричної потужності дозволяючи обґрунтувати його принципову дієздатність.

Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be − 147.001 dBc/Hz and − 181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability.

Fractional and reference spurs appear at the output of a fractional PLL along with the carrier. In the proposed architecture, two PLLs are conjunctly implemented for spur reduction—one fractional and other integer—with their control voltages summed together for dual control. A very low value (1/100) of the fractional frequency division ratio is considered. A fractional sampler is introduced that places bandstop notches at very low frequencies and hence, loop bandwidth of the fractional PLL has to be lower than the first spur frequency. To alleviate the issue of high area requirement by the second-order loop filter capacitors in the fractional PLL, the charge pump is divided into two parts with high and low values of pump currents. The charge pump with the low pump current drives the loop filter network segment with the resistor; thus, the area of the capacitor in this network can be reduced. By simulation in 180 nm CMOS technology, it is observed that the largest fractional spurs are reduced from $$+19.2$$ to $$-66.2$$ dBc, and the reference spurs from $$-28.5$$ to $$-67.8$$ dBc. Monte Carlo simulations show best and worst case spurs at $$-73$$ and $$-69$$ dBc, respectively. The architecture shows the phase noise characteristics of the integer PLL when identical oscillators are used in both the loops.

This paper presents a new mutually coupled circuit (MCC) based on voltage differencing current conveyor (VDCC). The proposed MCC has been designed using the Gorski-Popiel technique. The proposed circuit consists of two VDCCs as active elements, three resistors, and two grounded capacitors as passive elements. The primary and secondary self-inductances and the mutual inductance can be controlled independently and can be adjusted electronically by the bias current of the VDCCs. There is only one matching condition for satisfying symmetrical coupling. Time and frequency-domain analyses have been performed with the LTspice program to verify the theoretical analyses. A double-tuned band-pass filter application is given to show the functionality of the proposed MCC.

Fast recovery, high sensitivity, high selectivity, and room temperature (RT) sensing characteristics of NO gas sensors are essential for environmental monitoring, artificial intelligence, and inflammatory diagnosis of asthma patients. However, the conventional semiconductor-type gas sensors have poor sensing characteristics that need to be solved, such as slow recovery speeds (>360 s), low sensitivity (3.8), and high operating temperatures (>300 °C). We propose here a memristor-based NO gas sensor as a gasistor (gas sensor + memory resistor) with SnO2, Ta2O5, and HfO2 films, which successfully demonstrated the feasibility of fast reaction/recovery (

A differential quench and reset (QR) configuration for single-photon avalanche diodes (SPADs) is proposed and investigated in this work. Compared to the traditional single QR configuration in which only one QR circuit is connected to either the cathode or anode of the SPAD, the differential QR configuration consists of two QR circuits to quench and reset through both the cathode and anode terminals. Using a SPAD fabricated in a 65 nm CMOS process, the measurement results of the traditional single passive quench and reset (SPQR) circuit and the proposed differential passive quench and reset (DPQR) circuit shows that the SPAD with the DPQR circuit presented a reduced reset time, an improved timing performance, an increased count rate and a decreased afterpulsing. In addition, the differential output pair from the DPQR circuit has the potential to increase the signal-to-noise ratio of the detection system due to its ability to reject common-mode noise and interference.

The charge-generating sensors are widely used in many applications in consumer, automotive and medical electronics. They generate a charge proportional to the applied input quantity: pressure, temperature, acceleration, strain, light, etc. Usually, charge amplifiers are used to register such signals. The charge amplifier is an integrator that integrates the input current over time. In continuous-time signal processing, a parallel resistor is used to dissipate the energy stored on the integration capacitor, and such self-zeroed integrator circuits are known as lossy integrators. To achieve low-frequency operation, when a capacitor is in the picofarad range, a very high-ohmic resistor, in the range of gigaohms, must be used. Such a high-ohmic resistor increases the output offset voltage to an unacceptable level. To overcome the output offset problems, a composite charge amplifier has been recently introduced. This paper presents an innovative lossy integrator readout circuit which contains only one opamp in the feedback. The circuit can be easily adapted to the needed gain and cut-off frequency. Its operation is validated by experimental results. The sufficiently low high-pass cut-off frequency allows the circuit to be used for biosignal amplification. Heart and respiration rates can be easily recorded with piezoelectric sensors attached to the wrist or lung wall. The presented circuit can benefit many applications where charge-to-voltage conversion is needed.

In this brief, a novel compact single circular patch dual-band (DB) filtering power divider (FPD) is proposed for the first time. In this design, the modified TM01 resonance mode (i.e., TM01’ mode) is developed by introducing a metallic via in the center of the patch, while four additional same metallic vias are placed in the patch to control the generated TM01’ mode and the TM21 mode. In addition, vertical slot perturbations are investigated to control the TM11 mode and the TM31 mode, while the transversal slot perturbation loaded with three resistors is exploited to achieve good isolation. In this context, with elaborate exploitation of these resonant modes, two passbands can be attained, correspondingly. The lower passband is formed by TM01’ and TM11 modes, while the upper passband is constituted by TM21 and TM31 modes, respectively. For validation, a prototype is implemented. Results exhibit relative compact size, wider bandwidths, nice return losses, as well as decent isolation.

Line commutated converter based high voltage direct current (LCC-HVDC) has played a more and more vital role in the power systems in recent years. However, the energization inrush current generated by unloaded switched-on of converter transformer seriously threatens the safety and stable operation of the power system. To limit the energization inrush current, a suppression method utilized resistive type superconducting fault current limiter (R-SFCL) is investigated in this paper. Firstly, the mechanism of energization inrush current is described, and the theoretical feasibility of SFCL for such an application is discussed. Then, the structure and working principle of the R-SFCL are studied. Simulation results obtained in PSCAD/EMTDC validated that the R-SFCL can effectively limit the energization inrush current.

In this article, a novel dual-functional reconfigurable integrated structure is presented. The structure is composed of periodic arrays of four metallic loops, and a hollow Jerusalem cross with resistors etched on 3.3 mm-thick dielectric substrate, lumped resistors, and p-i-n diodes are connected in parallel on the edge of four metallic loops. When p-i-n diodes are switched ON, the designed structure is regarded as a high-gain, circular polarized (CP) antenna array operating within the absorption band. When the p-i-n diodes are switched OFF, the function of the structure is converted into an absorber. In addition, the four patches forming CP are used to increase the bandwidth of axial ratio (AR), and a composite structure is adopted to extend the absorbing band. Finally, $2\times {2}$ integrated units surrounding absorbing elements are fabricated and measured. The simulated and measured results manifest that the designed integrated structure realizes a high gain of 12.6 dB at 10.8 GHz, an AR from 10 to 12 GHz, and a wide absorption from 7 to 12 GHz.

Wide bandgap semiconductors show superior material properties enabling silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) present good features on its switching speed and withstand voltage. However, the high voltage and fast switching characteristics of SiC MOSFETs also put forward new requirements for voltage measurement, that is, high bandwidth under high voltage conditions. This article proposes a new voltage divider structure and a proactive parameter design compensation network to build high voltage and high bandwidth voltage sensing circuit. This structure utilizes the characteristics that the same resistor has the same parasitic capacitance to meet the high frequency constraints of the voltage sensing circuit. The influence of parasitic parameters and load parameters on circuit performance is analyzed in detail, which provides a basis for the compensation network design. By combining the proposed voltage sensing circuit with an appropriate proactive parameter design load effect compensation network (PDCN), the withstand voltage rating of the low-voltage and high-bandwidth voltage probes can be extended to required levels. Different from other existing methods, PDCN can actively design the compensation circuit parameters and provide the optimal parameters of the compensation circuit. This lead to a smaller input capacitance than the state of the art commercial voltage probes, which will help to obtain better performance when measuring high-speed switching voltage. The performance of the voltage measurement is experimentally verified and compared by SiC-based double pulse test (DPT) circuits.

A single phase resistive type superconducting fault current limiter (SFCL) was fabricated and successfully tested in the distribution network of Chongming Island, China. This paper presents the in-grid test of the 10 kV resistive type SFCL. Firstly, the specifications of this SFCL and the target grid is introduced. Then, the working performance of the SFCL is evaluated on basis of the data obtained from both rated state test and artificial fault tests. Further discussions are carried out to verify both the current limiting function and the voltage holding function of the SFCL by the numerical model built in PSCAD.

Memristor crossbar arrays are used in a wide range of in-memory and neuromorphic computing applications. However, memristor devices suffer from non-idealities that result in the variability of conductive states, making programming them to a desired analog conductance value extremely difficult as the device ages. In theory, memristors can be a nonlinear programmable analog resistor with memory properties that can take infinite resistive states. In practice, such memristors are hard to make, and in a crossbar, it is confined to a limited set of stable conductance values. The number of conductance levels available for a node in the crossbar is defined as the crossbar's resolution. This paper presents a technique to improve the resolution by building a super-resolution memristor crossbar with nodes having multiple memristors to generate r-simplicial sequence of unique conductance values. The wider the range and number of conductance values, the higher the crossbar's resolution. This is particularly useful in building analog neural network (ANN) layers, which are proven to be one of the go-to approaches for forming a neural network layer in implementing neuromorphic computations., 13 pages

For the spatial characterization of the soil in agricultural fields, the use of sensors is an alternative to collecting soil samples for laboratory analysis. Among such sensors, those that measure apparent soil electrical conductivity (ECa) are distinctive. In ECa sensors based on electrical resistivity, perfect soil–electrode contact is required for a reliable ECa measurement. Thus, this study aimed to develop and evaluate an algorithm for the analysis of the signals used in a soil ECa sensor based on electrical resistivity. Two criteria were selected for analysing the signals read by the sensor. The first criterion verifies whether the read signals have a square wave shape. The second criterion evaluates whether the main frequency of a read signal is similar to that of the applied signal, as set by the user. The algorithm was evaluated using signals obtained from soil ECa measurements conducted under laboratory and field conditions. In the laboratory, the absence of soil–electrode contact was simulated by connecting a resistor to the electrodes. In the field, the ECa measurements were performed in clayey and sandy soils under low and high moisture conditions. The simulation of the absence of soil–electrode contact showed that the algorithm was effective for detecting the unsuitability of the read signals for ECa calculation in eight of the ten scenarios. The results of the field measurements in soil with low moisture content demonstrated that the algorithm could detect signals that were inappropriate for ECa calculation.

Pre-insertion resistors (PIR) are critical components for suppressing the closing inrush current and operating overvoltage during the closing process of the circuit breaker. And it is widely adopted in 800kV and above transmission lines and alternating current filters of converter substations. These special application environments lead to higher failure rates than other electrical components. However, in the daily operation and fault diagnosis of PIR, there is no systematic method to analyze whether there are defects in PIR and the cause of failure after the PIR fails. Based on two PIR failure in series and parallel structures, this paper proposes methods such as dynamic resistance fitting, acoustic and vibration signal detection, insulation performance test, and heat capacity test during operation. In the aspect of fault diagnosis, methods such as PIR splicing based on Iterative Closest Point , stress analysis, and electric field simulation are proposed. Finally, proposed methods can be adjusted to estimate the operating state of PIR through the disassembly inspection to avoid the GIS breakdown accident during the operation of the circuit breaker.

DC fault current limitation is the key technique to improve the reliability and security of flexible dc grid operation. But the traditional dc fault current limiting method, which directly installs inductor in dc grid, will seriously deteriorate transient response ability and operation stability of the dc grid. In this paper, a simple I-SFCL topology is proposed. According to the theoretical analysis, the I-SFCL has similar ability of limiting dc fault current compared with the method directly installing dc inductor. And it can effectively eliminate negative effect of dc inductor on system transient response ability and operation stability. Finally, the simulation cases based on PSCAD/EMTDC proves the correctness of theoretical analysis and superiority of the proposed I-SFCL.

This paper presents a novel physically unclonable function (PUF) for security authentication. Instead of using the variation of transistors or PDK provided passive components as entropy source, the parasitic resistance created between metal and via layers is used as the static entropy source. A symmetric bridge configuration consisted with the parasitic resistance creates the necessary voltage difference for comparison. An accurate backend incremental analog-to-digital converter (IADC) is implemented to convert the voltage difference into a digitized value. The operation of the IADC allows to achieve a good native instability. Two different types of layout structures are implemented to create the necessary parasitic resistance and compared. Fabricated in a 65nm process, the prototype PUF achieves a native instability and bit error rate of less than 1.45% and 0.12% with 5000 repeated evaluations. The proposed design shows 0.58%/0.1V and 0.53%/10°C bit error across the voltage and temperature range of 0.9 to 1.4V and 0°C to 85°C, respectively without any stabilization techniques. The distance ratio between intra-die and inter-die Hamming Distance is above $305\times $ .

In this letter, a laser-scribed graphene (LSG) fabrication method is used to create graphene to be used in a microwave application, for example, a voltage-tunable microstrip attenuator. Graphene used in microwave circuits, such as tunable attenuators, usually focuses on using exfoliated graphene, deposited graphene nanoplatelets, or microwave irradiation. It will be demonstrated that the fabrication of LSG from graphene oxide on standard double-sided FR-4 copper-clad substrate can be used as a voltage-controlled resistor that results in a tunable microstrip attenuator across the microwave frequencies from 50 MHz to 5.5 GHz.

In this paper, we proposed a variable protective resistor that realizes controllable energy dissipation and temperature inhibition for the no-insulation (NI) HTS coil-systems, during sudden discharging. The resistor is paralleled with the meter-class bore NI coil, which aims to be used in a high-field magnetic resonance imaging scanner (MRI), to avoid burn-out and shorten restart time of the coil when it has to be shut-down during an accident. To establish the relationship between the value of protective resistor, the energy dissipation and the temperature increase during sudden discharging for the NI coil, in this study, a numerical analysis coupled with a partial element equivalent circuit and a thermal analysis was conducted. Based on the results, the mechanism that how a protective resistor shares energy dissipation and inhibits temperature increase, has been clarified. Meanwhile, the effects of the value of protective resistor on the discharging behavior and temperature increase of NI pancake coil during sudden discharging, were also evaluated to verify the feasibility of this protection method in the application of MRI.

A terahertz (THz) fundamental oscillator IC with high efficiency and compact chip size based on an indium phosphide (InP)-based resonant tunneling diode (RTD) is proposed. The oscillator is designed by utilizing a low-frequency bias stabilizer, along with utilizing a negative differential resistance oscillator topology. The oscillator is fabricated by using an InP monolithic THz integrated circuit multilayer process. The fabricated oscillator shows a high dc-to-RF power efficiency ( η ) of 0.274 % with a low dc power consumption of 3.4 mW and an RF output power of 9.3 μ W at an oscillation frequency of 692 GHz. The IC exhibits a chip size of 300 × 380 μ m2 excluding the measurement pads. The achieved η and chip size are good values among THz oscillators above 500 GHz reported to date.

FitzHugh-Nagumo, FHN, is a most critically significant Neural Cell method which is effectively capable of modeling the synaptic behavior by leveraging van-der-pol oscillators. The FitzHugh-Nagumo model makes use of common circuitry of FHNs, remarkably similar to the very conventional LC oscillators. Conventional LC oscillators, needless to say, have been largely deployed and comprehensively studied for quite some time. Notwithstanding its similarity to other LC oscillators, FitzHugh-Nagumo contains a resistor in series with the circuit that makes it inconsistent with other LC oscillator models. In this paper, a productive circuit technique is used to make FitzHugh-Nagumo circuit analogous to a LC conventional oscillator, which consequently provides the capability of using analytical approaches on these systems. This gives the designer of neural cells the opportunity of taking advantage of the vast knowledge about oscillatory systems. The proposed circuit model has been verified in terms of accuracy and compatibility for free-running, locked, and unlocked states. In addition, a theoretical analysis, aiming to clarify the background principle of the FitzHugh-Nagumo design process, is also provided. The simulation results which are performed using TSMC 180 nm CMOS technology represent a good agreement between theory and simulation.

A soil yeast count monitor that includes a soil yeast sensor and converter was developed for plant growing applications. The monitor can linearly transform soil yeast count into a frequency output. Moreover, the monitor’s adjustable sensitivity control circuits can increase sensitivity when low-nutrient soil is used. During measurements, the input voltage of the proposed converter was 0 to 2.2 V, and the sensitivity was controllably adjusted by 2.217, 2.952, 3.651, 4.388, and 5.118 MHz/V. The range of soil yeast count was 0 to $7\times10$ 8 colony forming units (CFU), and the adjustable sensitivities were 0.654, 0.871, 1.091, 1.311, and 1.529 MHz/108 CFU. The maximum linear error of the complete system was −0.66%, and the chip size was $1.49\times1.49$ mm2. The system was experimentally tested on two types of soil: fluvisol and paddy soil. Through measurements and experiments, the soil yeast count monitor was proven functionally.

A novel approach to interface resistive sensors directly to a Field Programmable Gate Array (FPGA) is presented in this paper. The circuit is based on Direct Interface Circuits (DICs), which make the sensor reading through a magnitude-to-time-to-digital conversion using just a few passive elements and a programmable digital device. Specifically, the system uses two calibration resistors of known value, two capacitors, and a new equation to estimate the sensor resistance in order to obtain an improved estimation in both the high and low parts of the resistance range. Furthermore, the new method can be used for reading resistive force sensors, with the advantage that the equations can be adapted for the output to directly provide the force exerted, thus avoiding the need for a resistance-to-force conversion. The circuit has been implemented using an FPGA as the programmable digital device to characterize the system, which allows both the reading of discrete resistors and those of a commercial force sensor. When discrete resistors are measured, estimation error in the low part of the range (a few hundred ohms) is reduced between twofold and fivefold compared to the results provided by other DICs. Moreover, the most significant errors produced by the new method when reading a force sensor come in the high part of the range (several tens of Newtons), standing at just 0.88%, compared to errors between 1.94% and 5.23% of other methods proposed in the literature.

OBJECT. When developing DC test voltage sources to assess the insulation quality of high-voltage equipment, the task is to measure the leakage current flowing through the test object. METHODS. When solving the problem the authors proposed a technical solution for measuring the current flowing through the test when testing insulation with rectified voltage, which uses a precision resistor, an isolating amplifier, a 2-channel operational amplifier with a unipolar power supply, zero voltage drift, and an ADC of a microcontroller.RESULTS. The article in the course of the study of the stand of the circuit for measuring the leakage current flowing through the tested object when testing the insulation with rectified voltage, an experimental industrial sample was created, which makes it possible to measure the leakage current value in the range from 10 μA to 1000 μA. The use of the developed circuit for measuring the current flowing through the test object when testing the insulation with rectified voltage makes it possible to calculate the DC component of the voltage signal from the alternating signal and in real time, and, therefore, to quickly monitor the current in high-voltage circuits for continuous monitoring. CONCLUSION. So the introduction of this sample will make it possible, on its basis, to create a number of digital measuring microammeters that make it possible to measure the leak-age current in high-voltage test installations for testing the insulation of objects from 15 nF to 200 nF, in the leakage current measurement range from 10 μA to 1000 μA. The results obtained can be used in high voltage technology to study circuits for measuring the leakage current flowing through the test object when testing insulation with rectified voltage.

A dual-polarization frequency-selective structure with a tunable passband and two absorptive bands is presented. Based on an equivalent circuit model (ECM), the working principle is investigated first. The values of components in the ECM are derived from the required performances and are mapped to the structure of an initial design, which is designed by cascading of an absorptive frequency-selective surface (FSS) realized with dipole-like elements and a lossless bandpass FSS achieved with square ring slot. For tuning the passband, varactors and biasing networks are added into the initial design. The adding of the varactors and biasing networks significantly affects the performance, and brings about the emergence of singular resonances. The approaches for mitigating the effects and the techniques for suppressing the singular resonances are proposed. Simulated results show that, between two absorptive bands, a passband is tuned from 3.33 to 5.13 GHz if the capacitances are decreased from 0.5 to 0.15 pF. A prototype is fabricated and measured. Measured results show that the passband is altered from 3.56 to 4.35 GHz as the reverse bias voltage of the used varactors is increased from 6 to 18 V.

The function of time-resolved fuel regression measurement is integrated into additively manufactured hybrid rocket fuels and conceptually demonstrated through the comparison with time-resolved optical fuel regression measurements during burns. This function is enabled by multi-material additive manufacturing of mainly thermoplastic solid fuels with a ladder-shaped resistor made of a conductive thermoplastic. This functionalization has many advantages, as indicated by its wide range of applicability, including solid fuel grains with emerging complex geometries, cost-effectiveness, ease of implementation, and minimal influence on the original propulsive performance and fuel regression behavior. Fuel regression is detected by a step change in the voltage applied to the ladder-shaped resistor, indicating the breakage of its top fuel surface rung during a burn. For ignited cases, all the rung breaks were detected, while the fuel regression was also optically measured using high-speed video. Errors were observed between the fuel regression time-histories measured using the two methods; however, most of these errors could be explained by the distribution of the fuel regression in the camera direction and the camera resolution and the melted fuel layer thickness. Considering these uncertainties, the remaining errors that could not be explained by these factors were less than ± 0.15 mm, corresponding to ± 1 layer of additive manufacturing applied to the prototyping of the solid fuels.