556 results on '"Platzner, Marco"'
Search Results
102. Evolution of application-specific cache mappings
103. A Hybrid Synthesis Methodology for Approximate Circuits
104. Proof-Carrying Approximate Circuits
105. DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep Learning on Embedded Platforms
106. An adaption mechanism for the error threshold of XCSF
107. Enabling XCSF to cope with dynamic environments via an adaptive error threshold
108. Dynamic Reliability Management for FPGA-Based Systems
109. MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes
110. A specialized computer architecture for QSim
111. A Runtime Environment for Reconfigurable Hardware Operating Systems
112. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices
113. Virtualizing Hardware with Multi-context Reconfigurable Arrays
114. Communication Synthesis for Reconfigurable Embedded Systems
115. Jump Search
116. An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware
117. An MCTS-based Framework for Synthesis of Approximate Circuits
118. Reconfigurable accelerators for combinatorial problems
119. Dynamically Reconfigurable Architectures
120. A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes
121. R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints
122. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor
123. Proof-Carrying Hardware via Inductive Invariants
124. Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches
125. reMinMin: A novel static energy-centric list scheduling approach based on real measurements
126. Computational self-awareness as design approach for visual sensor nodes
127. Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
128. The First 25 Years of the FPL Conference
129. Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor
130. A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller
131. Thread shadowing: On the effectiveness of error detection at the hardware thread level
132. On-the-fly computing
133. An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip
134. Adaptive playouts for online learning of policies during Monte Carlo Tree Search
135. Monte-Carlo simulation balancing revisited
136. Boolean Difference Based Reliability Evaluation of Fault-Tolerant Circuit Structures on FPGAs
137. Programming models for reconfigurable manycore systems
138. Verifying worst-case completion times for reconfigurable hardware modules using proof-carrying hardware
139. Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center
140. New Co-design Methodology for Real-time Embedded Systems
141. Distributed Monte Carlo Tree Search: A Novel Technique and its Application to Computer Go
142. FPGA-based acceleration of high density myoelectric signal processing
143. Comparison of thread signatures for error detection in hybrid multi-cores
144. Performance Estimation for the Exploration of CPU-Accelerator Architectures
145. Memory security in reconfigurable computers: Combining formal verification with monitoring
146. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure
147. Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA
148. An FPGA-Based Reconfigurable Mesh Many-Core
149. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
150. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center.
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