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Effects of irradiation and annealing temperature on radiation-induced charge trapping are explored for MOS transistors. Transistors were irradiated with 10-keV x rays at temperatures from -25 to 100/spl deg/C and annealed at 100/spl deg/C for times up to 3.6/spl times/10/sup 6/ s. Transistor data were analyzed for the contributions of radiation-induced charge due to oxide traps, border traps, and interface traps. Increased irradiation temperature resulted in increased interface-trap and border-trap buildup and decreased oxide-trapped charge buildup during irradiation. Interface-trap buildup immediately following irradiation for transistors irradiated at 100/spl deg/C was equivalent to the buildup of interface traps in transistors irradiated at 27/spl deg/C and annealed for one week at 100/spl deg/C (standard rebound test). For the p-channel transistors, a one-to-one correlation was observed between the increase in interface-trap charge and the decrease in oxide-trapped charge during irradiation. This may imply a link between increased interface-trap buildup and the annealing of oxide-trapped charge in these devices. The observed data can be explained in terms of increased hydrogen ion transport rates to the Si/SiO/sub 2/ interface during elevated temperature irradiations. These results have implications on hardness assurance testing and potentially may be used to reduce costs associated with rebound qualification.

Identifying aging effects that impact radiation hardness of microelectronics is becoming increasingly important as military weapon systems are kept in the stockpile for times beyond their originally intended use period. In this work, burn-in effects are used to demonstrate the potential impact of thermally-activated aging effects on integrated circuit radiation hardness. Static random access memories (SRAMs) from three different commercial technologies were irradiated with different pre-irradiation stress conditions. A reduction in the total dose functional failure level was observed for SRAMs from two of the technologies subjected to pre-irradiation elevated temperature stresses. This is the first time the burn-in effect has been shown to degrade the radiation-induced functional failure level of an IC. SRAM data also show no indication that the burn-in effect will saturate, at least for the conditions examined in this work. These data indicate that long-term aging can result in more device degradation than is accounted for by present hardness assurance test guidelines, potentially causing device and/or system failure during the aging period. While only a few technologies have been examined to date, we suspect other technologies may exhibit similar long-term aging effects. Technique for including aging effects within a hardness assurance test program is outlined.

A low-voltage, radiation-tolerant, nonvolatile field effect transistor (NVFET) memory involving proton motion in SiO/sub 2/ is illustrated in both bulk Si and silicon-on-insulator devices. We discuss a mechanism by which the protons are created in the oxide layer by a forming gas anneal. At low temperature (T

Charge collection and SEU from angled ion strikes are studied using three-dimensional simulation. The physics of charge collection in unloaded diodes and transistors is explored, as is the angular dependence of upset threshold in CMOS SRAMs. The simulation results are compared to analytical models for charge collection. Modeling fundamental transport in SRAMs, the true effective LET relationship is computed and used to analyze experimental heavy-ion data. Impacts on SEU test methodology are discussed.

The effects of ionizing radiation and displacement damage on TaO x memristors are evaluated. Devices show little response to 10 keV x-rays up to 10 Mrad(Si). Co60 gamma rays and 4.5 MeV protons did not change the resistances significantly at levels up to 2.5 Mrad(Si) and 5 Mrad(Si) respectively. 105 MeV and 480 MeV protons cause switching of the memristors from high to low resistance states in some cases, but do not exhibit a consistent degradation. 800 keV silicon ions are observed to cause resistance degradation, with an inverse dependence of resistance on oxygen vacancy density. Variation between different devices appears to be a key factor in determining the electrical response resulting from irradiation. The proposed degradation mechanism likely involves the creation of oxygen vacancies, but a better fundamental understanding of switching is needed before a definitive understanding of radiation degradation can be achieved.

We investigate proton-induced upsets in state-of-the-art NAND Flash memories, down to the 25-nm node. The most striking result is the opposite behavior of Multi-Level Cell (MLC) and Single-Level Cell (SLC) devices, in terms of floating gate error cross section as a function of proton energy. In fact, the cross section increases with proton energy in SLC whereas it decreases in MLC. The reason for this behavior is studied through comparison of heavy-ion data and device simulations. The main factors that determine proton energy dependence are discussed, such as the energy dependence of nuclear cross section between protons and chip materials, the LET, energy, and angular distributions of the generated secondaries, but also the heavy-ion and total dose response of the studied devices. Proton irradiation effects in the control circuitry of NAND Flash memories are shown as well.

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation, to the development of a 0.5-/spl mu/m radiation-hardened CMOS SRAM is presented.

A dual-dielectric pMOS dosimeter (RADFET) has been recently designed at Sandia. The RADFET consists of a thermally grown oxide and a CVD deposited nitride. With a negatively applied bias, holes are generated in the SiO/sub 2/ transport and are trapped at the SiO/sub 2//Si/sub 3/N/sub 4/ interface producing a measurable threshold-voltage shift. Because holes are trapped away from the Si/SiO/sub 2/ interface, hole neutralization by tunneling and interface-trap buildup are minimized resulting in little fade or annealing of the RADFET output response. RADFETs were irradiated at dose rates from 0.002 to 50 rad(Si)/s with biases from -5 to -20 V. RADFETs were also annealed for times up to 10/sup 7/ s at temperatures up to 100/spl deg/C. Within experimental uncertainty, no difference in RADFET output response at a given bias was observed over the dose rate range examined and for 25/spl deg/C anneals. At an anneal temperature of 100/spl deg/C only a 20% decrease in RADFET output response was observed. These results show that Sandia's RADFETs exhibit little or no fade of their output characteristics and are ideal for low dose rate space applications.

We find that annealing oxides in a H/sub 2/ containing ambient creates positive charge in the dielectric of Si/SiO/sub 2//Si structures. The H-induced positive oxide charge is shown to be very different from radiation-induced oxygen vacancy hole traps (E' centers) in SiO/sub 2/. We find that three factors strongly influence the ability to create H-induced positive charge: temperature, hydrogen concentration in the ambient, and the density of hydrogen cracking centers. We suggest that over-coordinated O centers are responsible for this charge. The proposed over-coordinated oxygen centers may also account for the equivocal nature of several forms of positive charge that have escaped detection by electron paramagnetic resonance, such as the fixed oxide charge that forms during the thermal oxidation of Si.

Threshold-voltage and charge-pumping measurements are combined to estimate densities of radiation induced bulk-oxide, interface, and border traps in transistors with soft 45-nm oxides. Immediately after irradiation, nearly all effects usually attributed to interface traps are actually due to border traps in these devices. During positive-bias anneal at 80/spl deg/C, the interface-trap density grows by more than a factor of 10, and the border-trap density changes by less than 30%. The increase in interface-trap density is matched by a decrease in bulk-oxide-trap charge. This raises the possibility that slowly transporting or trapped protons in the oxide may be responsible for this effect. An alternate explanation is offered by H-cracking models. Latent "interface-trap" growth in harder 27.7-nm oxides is associated with (true) interface traps, not border traps. Switched-bias annealing of the soft 45-nm oxides reveals fast and slow border traps with different annealing responses. Trivalent Si defects associated with O vacancies in SiO/sub 2/, the E/sub /spl gamma//' center and the O/sub 3-x/Si/sub x/Si/spl middot/ family, are excellent candidates for slow and fast border traps, respectively. For O/sub 3-x/Si/sub x/Si, x=0 is the E/sub s/' defect; x=3 is the D center; and x=1 or 2 have been proposed as candidates for the "P/sub b1/" defect on (100) Si. A hydrogen-related complex (e.g. OH/sup -/) may also be a border trap. The practical significance of these results is discussed for (1) bias-temperature instabilities in thin oxides, (2) effects of burn-in on MOS radiation response, and (3) enhanced bipolar gain degradation at low dose rates.

Defect centers in chemical-mechanical polished MOS oxides generated by either X-ray irradiation or high-field stress have been characterized using electron paramagnetic resonance and C-V analysis. In X-ray irradiated samples equivalent densities of both oxide trap E' and interface-trap P/sub b0/ centers were detected in unpolished and polished oxides. In addition, significantly larger (6 times) densities of P/sub b1/ centers were observed in irradiated chemical-mechanical polished oxides as opposed to unpolished oxides. This suggests that the polishing process alters the SiO/sub 2//Si interface. However, the P/sub b1/ centers detected in these samples do not respond electrically like conventional interface traps or border traps. This raises questions concerning the electrical and physical nature of P/sub b1/ centers in these oxides. The high-field stress data showed no difference in the density of defect centers induced in polished and unpolished oxides P/sub b1/ centers were not observed in either oxide following high-field stress.

The effect of displacement and ionizing dose damage on ion-beam-induced-charge-collection (IBICC) and single-event-upset (SEU) imaging are explored. IBICC imaging is not affected by ionizing dose damage, and its dependence on displacement damage is a complex function of the structure of the samples used in this study. Degradation of the IBICC signal is controlled by displacement damage that occurs at different rates in the heavily doped substrate and lightly doped epitaxial silicon layer, leading to a non-linear dependence of inverse degradation versus ion fluence. The effect of ion exposure on the electrical performance of complementary metal-oxide-semiconductor (CMOS) static random access memories (SRAMs) is solely related to ionizing dose effects in the transistor oxides. With SEU imaging, we found that an additional region became sensitive to upset with ion fluence probably as a result of ionizing dose effects on the restoring transistors. Finally, SEU during IBICC imaging resulted in charge collection from both p-drains of a memory cell. Implications of damage on the use of these microbeam techniques are discussed.

An electron paramagnetic resonance, thermally stimulated current, and capacitance-voltage study has been carried out on phosphorus (PSG), boron (BSG), and boron and phosphorus (BPSG) co-doped oxide films on Si. The principal spin-active defects are the phosphorus-oxygen-bole-center (POHC) and the boron-oxygen-hole-center (BOHC), which are unpaired electrons on oxygen atoms with P or B in the near vicinity. The centers are activated by hole capture. We find that holes are trapped in the PSG, BSG, and BPSG dielectrics; however, hole trapping is most effective in the PSG and BPSG dielectrics. We find that electrons are trapped to differing extents in the doped films. The BPSG films are the most efficient in trapping electrons the PSG films are the least efficient. The electrical data can be explained by assuming that the precursor to the BOHC is negatively charged and the precursor to the POHC is electrically neutral. Last, the charge trapping properties of PSG, BSG, and BPSG dielectrics are compared and contrasted with those observed in thermally grown oxides.

The 1 f noise and radiation response of MOS transistors have been compared. A strong correlation is found between the pre- and post-irradiation noise of the transistors and their threshold-voltage shifts due to radiation-induced oxide-trap charge. It is inferred that the noise is caused by a subset of the oxide traps, which is referred to as ‘border traps’. These defects are near-interfacial oxide traps which can communicate with the Si on the timescales of the measurements, and have been mistaken for interface traps in some previous work on 1 f noise and/or radiation effects on MOS devices. Comparisons of electron-paramagnetic-resonance and radiation-effects studies offer compelling evidence that radiation-induced oxide-trap charge is associated with oxygen-deficient centers (oxygen vacancies and vacancy complexes) near the Si SiO 2 interface. It is concluded that these same defects also enhance the 1 f noise of MOS transistors, which should help to resolve the long-standing debate on the origin of MOS noise. Independent estimates of radiation-induced border-trap charge densities using a dual-transistor technique that combines threshold-voltage and charge-pumping measurements agree well with 1 f noise estimates.

We have performed an extensive study of the effects of border traps (near-interfacial oxide traps that can communicate with the underlying Si over a wide range of time scales) on the response of metal-oxide-semiconductor (MOS) devices to ionizing radiation. Estimates of border-trap densities for several types of MOS devices are obtained by capacitance-voltage (CV) hysteresis, 1 f noise, and combined CV/thermally-stimulated-current methods. A new “dual-transistor border-trap” (DTBT) technique is described in detail which combines conventional threshold-voltage and 1-MHz charge-pumping measurements on n- and p- channel MOS transistors to estimate radiation-induced oxide-, interface-, and border-trap charge densities. Estimates of border-trap charge densities obtained via the DTBT technique agree well with trap densities inferred from other techniques. In some devices, border-trap charge densities (which can be greater than 1012 cm−2 following ionizing radiation exposure) can approach or exceed interface-trap charge densities, emphasizing the need to distinguish border-trap effects from interface-trap effects in models of MOS radiation response and long-term reliability. This appears to be especially critical for MOS devices with ultrathin (less than ∼6 nm) oxides, in which border traps and interface traps likely will be the dominant defect types. Effects of border traps on MOS scattering rates, cryogenic applications, and long-term reliability assessment are also discussed.

The radiation hardness of commercial floating gate 256 K E/sup 2/PROMs from a single diffusion lot was observed to vary between 5 to 25 krad(Si) when irradiated at a low dose rate of 64 mrad(Si)/s. Additional variations in EEPROM hardness were found to depend on bias condition and failure mode (i.e., inability to read or write the memory), as well as the foundry at which the part was manufactured. This variability is related to system requirements, and it is shown that hardness level and variability affect the allowable mode of operation for EEPROMs in space applications. The radiation hardness of commercial 1-Mbit CMOS SRAMs from Micron, Hitachi, and Sony irradiated at 147 rad(Si)/s was approximately 12, 13, and 19 krad(Si), respectively. These failure levels appear to be related to increases in leakage current during irradiation. Hardness of SRAMs from each manufacturer varied by less than 20%, but differences between manufacturers are significant. The qualified manufacturer's list approach to radiation hardness assurance is suggested as a way to reduce variability and to improve the hardness level of commercial technologies. >

A wide range of advanced III-V components suitable for use in high-speed satellite communication systems were evaluated for displacement damage and single-event effects in high-energy, high-fluence proton environments. Transistors and integrated circuits (both digital and MMIC) were irradiated with protons at energies from 41 to 197 MeV and at fluences from 10/sup 10/ to 2/spl times/10/sup 14/ protons/cm/sup 2/. Large soft-error rates were measured for digital GaAs MESFET (3/spl times/10/sup -5/ errors/bit-day) and heterojunction bipolar circuits (10/sup -5/ errors/bit-day). No transient signals were detected from MMIC circuits. The largest degradation in transistor response caused by displacement damage was observed for 1.0-/spl mu/m depletion- and enhancement-mode MESFET transistors. Shorter gate length MESFET transistors and HEMT transistors exhibited less displacement-induced damage. These results show that memory-intensive GaAs digital circuits may result in significant system degradation due to single-event upset in natural and man-made space environments. However, displacement damage effects should not be a limiting factor for fluence levels up to 10/sup 14/ protons/cm/sup 2/ [equivalent to total doses in excess of 10 Mrad(GaAs)]. >

We show that enhanced hole-, electron-, interface-, and border-trap generation in irradiated Si/SiO/sub 2//Si systems that have received a high-temperature anneal during device fabrication is related either directly, or indirectly, to the presence of anneal-created oxygen vacancies. The high-temperature anneal results are shown to be relevant to understanding defect creation in zone-melt-recrystallized silicon on insulator materials. We observe the electron paramagnetic resonance (EPR) of trap-assisted hole transfer between two different oxygen vacancy-type defects (E'/sub /spl delta///spl rarr/3 E'/sub /spl gamma// precursor) in hole injected thermal SiO/sub 2/ films. Upon annealing the hole injected Si/SiO/sub 2/ structures at room temperature, the E'/sub /spl delta// center transfers its hole to a previously neutral oxygen vacancy (O/sub 3//spl equiv/Si-Si/spl equiv/O/sub 3/) site forming an E'/sub /spl gamma// center. This process, also monitored electrically, shows a concomitant increase in the border-trap density that mimics the growth kinetics of the transfer-activated E'/sub /spl gamma// centers. This suggests that both effects are correlated and that some of the transfer-created E'/sub /spl gamma// centers are the entities responsible for the border traps in these devices. One implication of these results is that delayed defect growth processes can occur via slow trap-assisted hole motion in SiO/sub 2/. >

This paper demonstrates use of the Qualified Manufacturers List (QML) methodology to qualify commercial and military microelectronics for use in space applications. QML "builds in" the hardness of the product through statistical process control (SPC) of technology parameters relevant to the radiation response, test structure to integrated circuit (IC) correlations, and techniques for extrapolating laboratory test results to low-dose-rate space scenarios. Each of these elements is demonstrated and shown to be a cost-effective alternative to expensive end-of-line IC testing. Several examples of test structure-to-IC correlations are provided and recent work on complications arising from transistor scaling and geometry is discussed. The use of a 10-keV X-ray wafer-level test system to support SPC and establish "process capability" is illustrated and a comparison of 10-keV X-ray and Co/sup 60/ gamma irradiations is provided for a wide range of CMOS technologies. The X-ray tester is shown to be cost-effective and its use in lot acceptance/qualification is recommended. Finally, a comparison is provided between MIL-STD-883, Test Method 1019.4, which governs the testing of packaged semiconductor microcircuits in the DoD, and ESA/SCC Basic Specification No. 22900, Europe's Total Dose Steady-State Irradiation Test Method. Test Method 1019.4 focuses on conservative estimates of MOS hardness for space and tactical applications, while Basic Specification 22900 focuses on improved simulation of low-dose-rate space environments. >

Si/SiO2/Si structures have been subjected to 6 h anneals at 1320°C and defects generated by the annealing process revealed by ultra-violet and X ray irradiation and by hole injection. Two types of oxygen-vacancy related defects have been detected in the oxide by electron spin resonance, one involving Si interstitials. They are both observed to be located within 100 nm of each of the Si/SiO2 interfaces. It is reasoned that the high temperature annealing process getters oxygen from the oxide into the over and underlying Si.

Electron paramagnetic resonance (EPR) and capacitance-voltage measurements have been combined to identify the chemical nature and charge state of defects in BESOI (bonded and etchback silicon-on-insulator) and SIMOX (separation by implantation of oxygen) materials. The four types of defect centers observed, charged oxygen vacancies, delocalized hole centers, amorphous-Si centers, and oxygen-related donors, are strikingly similar. In the BESOI materials, the radiation-induced EPR centers are located at or near the bonded interface. Therefore, the bonded interface is a potential hole trap site and may lead to radiation-induced back-channel leakage. In SIMOX materials, it is found that all of the defects in the buried oxide are due to excess Si. The results using poly-Si/thermal oxide/Si structures strongly suggest that it is the postimplantation, high-temperature anneal processing step in SIMOX that leads to their existence. The anneal leads to the out-diffusion of oxygen from the buried oxide, creating excess-Si related defects in the oxide and O-related donors in the underlying Si substrates. A relatively new class of defects in SiO/sub 2/, delocalized spin centers, are found to be hole traps in both SIMOX and BESOI materials. >

Charge-pumping, dual-transistor, and midgap estimates of radiation-induced interface-trap density are compared for a large number of transistors fabricated using a wide range of processing technologies. Comparisons are shown for single-transistor midgap and charge-pumping measurements and dual-transistor-mobility measurements. When conventional analysis methods are used to determine threshold voltages, there can be as much as a factor-of-two-difference in the density of interface traps measured by charge pumping and the dual-transistor-mobility and midgap techniques. Using the voltage that corresponds to twice the bulk potential as the threshold voltage, better agreement between the three techniques is obtained. In addition, the authors present a technique that combines n- and p-channel transistor charge-pumping and threshold-voltage measurements to accurately determine the threshold-voltage shifts due to interface-and oxide-trap charge. Called the dual-transistor charge-pumping technique, it contains no adjustable parameters and includes a physically based self-consistency check. >

We have identified several features of the 1/f noise and radiation response of metal‐oxide‐semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ‘‘oxide traps’’ are simply defects in the SiO2 layer of the MOS structure, and ‘‘interface traps’’ are defects at the Si/SiO2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ‘‘fixed states’’ are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ‘‘switching states’’ can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface tr...

Charge collection measurements reveal that the presence of high-Z materials increases proton-induced charge collection cross sections for high charge collection events. The mechanism for this effect is proton-induced fission events as shown through validated Monte Carlo simulations. These fission fragments are emitted isotropically in contrast to high-LET secondary particles from proton-silicon interactions which tend to be forward directed.

A series of experiments on the MEDUSA linear accelerator radiation test facility were performed to evaluate the difference in dose measured using different methods. Significant differences in dosimeter-measured radiation dose were observed for the different dosimeter types for the same radiation environments, and the results are compared and discussed in this report.

An analytical model with no free parameters has been developed which accurately describes thermally-stimulated-current (TSC) measurements spanning more than a factor of 50 in average heating rate. The model incorporates Schottky electric-field-induced barrier lowering and a temperature-dependent 'attempt-to-escape frequency' equal to approximately 10/sup 14/ Hz at 300 degrees C. Applying this model to TSC measurements provides significantly improved estimates of the energy distribution of trapped holes in irradiated SiO/sub 2/. All devices examined, including soft and (wet and dry) hard oxides from five process technologies, show similar energy distributions, with a minor peak at approximately 1.2 eV and a broad major peak centered approximately 1.7-2.0 eV above the SiO/sub 2/ valance band. It is found that the trapped-electron density in irradiated SiO/sub 2/ is proportional to the trapped-hole density over a wide range of irradiation conditions. >

International audience; We characterize by different spectroscopic techniques the radiation effects on ytterbium-(Yb) and ytterbium/erbium (Yb/Er)-doped optical fibers. Their vulnerability to the environment of outer space is evaluated through passive radiation-induced attenuation (RIA) measurements during and after exposure to 10 keV X-rays, 1 MeV gamma-rays, and 105 MeV protons. These fibers present higher levels of RIA (1000 x) than telecommunication-type fibers. Measured RIA is comparable for gamma-rays and protons and is on the order of 1 dB/m at 1.55 mu m after a few tenths of a kilorad. Their host matrix codoped with aluminum (Al) and/or phosphorus (P) is mainly responsible for their enhanced radiation sensitivity. Thanks to the major improvements of the Er-doped glass spectroscopic properties in case of Yb-codoping, Yb/Er-doped fibers appear as very promising candidates for outer space applications. In the infrared part of the spectrum, losses in P-codoped Yb-doped fibers are due to the P-1 center that absorbs around 1.6 mu m and are very detrimental for the operation of Er-codoped devices in a harsh environment. The negative impact of this defect seems reduced in the case of Al and P-codoping.

A 1 GeV/u 56Fe ion beam allows for true 90° tilt irradiations of various microelectronic components and reveals relevant upset trends for an abundant element at the GCR flux energy peak.

The radiation response of MOS devices exposed to /sup 60/Co and low-energy ( approximately 10 keV) X-ray irradiation is evaluated as a function of electric field during exposure. Improved charge yield estimates are obtained for /sup 60/Co irradiations at fields below 1 MV/cm by matching voltage shifts due to oxide-trap and interface-trap charge to an E/sup -0.55/ electric field dependence. Combining these improved charge yield estimates and calculated dose enhancement factors, the relative response of X-ray to /sup 60/Co irradiations is accurately predicted for oxide electric fields from 0.03 MV/cm to 5.0 MV/cm. The ability to predict the relative response to X-ray to /sup 60/Co irradiations-should speed acceptance of X-ray testers as a hardness assurance tool. >

The SEU tolerance of the SA3300 microprocessor with feedback resistors is presented and compared to the SA3300 without feedback resistors and to the commercial version (NS32016). Upset threshold at room temperature increased from 23 MeV-cm/sup 2//mg with no feedback resistors to 60 MeV-cm/sup 2//mg and 180 MeV-cm/sup 2//mg with feedback resistors of 50 k Omega and 160 k Omega , respectively. The performance goal of 10 MHz over the full temperature range of -55 degrees C to +125 degrees C is exceeded for feedback resistors of 160 k Omega and less. Error rate calculations for this design predict that the error rate is less than once every 100 years when 50 k Omega feedback resistors are used in the D-latch design. Analysis of the SEU response using a lumped-parameter circuit simulator imply a charge collection depth of 4.5 mu m. This is much deeper than what one would expect for prompt collection in the epi and funnel regions and has been explained in terms of diffusion current in the heavily doped substrate. >

The 1/f noise of n- and p-channel MOS transistors was investigated through irradiation and biased anneals. While the increase in noise during irradiation is similar for both types of devices, the noise differs significantly in response to biased anneals. In particular, the noise decreases with decreasing Delta V/sub ot/ during positive-bias anneals in nMOS transistors but increases during positive-bias anneals for pMOS transistors. Conversely, negative bias anneals increase the noise in nMOS devices but decrease the noise in pMOS devices. These results are explained in terms of majority carrier trapping and detrapping at oxide defects near the Si/SiO/sub 2/ interface. Under normal operating bias conditions (positive bias for nMOS and negative bias for pMOS), the 1/f noise of both n- and p-channel transistors decreases through postirradiation annealing. >

We report scanning capacitance microscopy (SCM) images of a working p-channel metal–oxide–semiconductor field-effect transistor (P-MOSFET) during device operation. Independent bias voltages were applied to the source/gate/drain/well regions of the MOSFET during SCM imaging, and the effect of these voltages on the SCM images is discussed.

The US government has proposed a qualified manufacturers list (QML) methodology to qualify integrated circuits for high reliability and radiation hardness. An approach to implementing QML for single-event upset (SEU) immunity on 16k SRAMs that involves relating values of feedback resistance to system error rates is demonstrated. It is seen that the process capability indices, C/sub p/ and C/sub pk/, for the manufacture of 400-k Omega feedback resistors required to provide SEU tolerance do not conform to 6 sigma quality standards. For total-dose, interface trap charge, Delta V/sub it/, shifts measured on transistors are correlated with circuit response in the space environment. Statistical process control (SPC) is illustrated for Delta V/sub it/, and violations of SPC rules are interpreted in terms of continuous improvement. Design validation for SEU and quality conformance inspections for total-dose are identified as major obstacles to cost-effective QML implementation. Techniques and tools that will help QML provide real cost savings are identified as physical models, 3-D device-plus-circuit codes, and improved design simulators. >

Proton SEU cross sections of 1-Mbit commercial SRAMs and deposited dose in thermoluminescent dosimeters are used to explore the effectiveness of tungsten-filled silicone composite shielding materials for improving the radiation tolerance of commercial electronics in proton environments.

The chemical kinetics of mobile-proton reactions in the SiO2 film of Si/SiO2/Si structures were analyzed as a function of forming-gas anneal parameters in the 300–600 °C temperature range. Our data show that the initial buildup of mobile protons is limited by the rate of lateral hydrogen diffusion into the SiO2 films. The final density of mobile protons is determined by the cooling rate which terminates the annealing process and, in the case of subsequent anneals, by the temperature of the final anneal. To explain the observations, we propose a dynamical equilibrium model which assumes a reversible interfacial reaction with a temperature-dependent balance.

著者人数：13名, 資料番号: SA1000560000

The silicon/silicon-dioxide system provides the cornerstone of integrated-circuit technology1. Since the introduction of devices based on this system, the (largely deleterious) effects on device operation of mobile and trapped charges in the oxide layer have been studied in great detail. Contamination by alkali ions, for example, was a major concern in the early days of metal-oxide-semiconductor device fabrication2. But not all SiO2 impurities are undesirable: the addition of hydrogen, for example, has the beneficial property of rendering charge traps inactive1. Here we show that mobile H+ ions introduced by annealing into the buried oxide layer of Si/SiO2/Si structures, rather than being detrimental, can form the basis of a non-volatile memory device. These mobile protons are confined to the oxide layer, and their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Memory devices based on this effect are expected to be competitive with current state-of-the-art Si-based memories, with the additional advantage of simplicity—only a few standard processing steps are required.

The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25/spl deg/ and 85/spl deg/C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEL, the heavy-ion SEL threshold LET was as high as 25MeV-cm/sup 2//mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs /spl ges/40 MeV-cm/sup 2//mg.

A BESOI 4K SRAM was characterized in transient and total dose radiation environments. Transient upset level was explored as a function of radiation pulse width. A total dose experiment was performed to determine the level at which read or write failures occurred. In addition the total dose level at which imprinting occurred was determined. It was shown that devices fabricated in bonded and etchback (BESOI) technology should exhibit high dose-rate upset levels (above 10/sup 10/ rad(Si)/s) but may not be applicable for high total dose uses, especially if total dose imprinting is detrimental to the system. Total dose failures were observed above 4.3/spl times/10/sup 5/ rad(SiO/sub 2/) and imprinting occurred between 4 and 6/spl times/10/sup 4/ rad(SiO/sub 2/).

Charge-induced failure is recognized as the primary reliability issue in RF MEMS capacitive switches. In this paper, we present a simplified method for quantifying the effects of process-induced charging of PECVD dielectrics commonly used in the fabrication of these devices. Using this method, based on capacitance-voltage (C-V) measurements of MIS (metal-insulator-semiconductor) devices, we examined the charge behavior of PECVD silicon dioxide, nitride, and oxynitride films deposited at substrate temperatures of 250-350/spl deg/C. The results show that these PECVD dielectrics contain sufficient incorporated charge in their as-deposited state to inhibit reliable switch operation. Post-deposition, plasma-induced and electrical stresses were also found to negatively impact the charge behavior of these films. However, after an initial period of instability, chemical analysis showed film composition to be highly consistent, both across deposition runs and with post-deposition stress. We conclude by presenting potential techniques for mitigation of the incorporated charge observed in these PECVD dielectrics.

This work presents high and low dose rate test results for LM124 operational amplifiers that were fabricated with six passivation layer types. Consistent with previous data, these results confirm that passivation layers play a significant role in determining ELDRS response. SIMS analysis suggests that an influential factor in determining the high and low dose rate response may be the location and concentration of hydrogen at the Si-SiO/sub 2/ interface and in the passivation layers.

Trivalent silicon Pb0 and Pb1 defects were identified at both the top Si(100)/buried‐SiO2 and buried‐SiO2/bottom‐Si(100) interfaces in high‐temperature (1320 °C) annealed Si/SiO2/Si struc‐ tures. The paramagnetic defects are generated by annealing in a flow of pure nitrogen (N2) or forming gas [N2H2; 95:5 (by volume)] at 550 °C. In addition, the forming‐gas anneal also generated positive charge in the buried oxides; significant lateral nonuniformities in the buried oxide charge density were observed following this anneal. These macroscopic inhomogeneities may be linked to previous reports of homogeneity related problems involving the SIMOX buried oxide, such as early breakdown and etch pits, suggesting that these types of measurements may be useful as nondestructive screens of SIMOX wafer quality.

Improvements have been made at TRIUMF to permit higher proton intensities of up to 10/sup 10/ cm/sup -2/s/sup -1/ over the energy range 20-500 MeV. This improved capability enables the study of displacement damage effects that require higher fluence irradiations. In addition, a high energy neutron irradiation capability has been developed for terrestrial cosmic ray soft error rate (SER) characterization of integrated circuits. The neutron beam characteristics of this facility are similar to those currently available at the Los Alamos National Laboratory WNR test facility. SER data measured on several SRAMs using the TRIUMF neutron beam are in good agreement with the results obtained on the same devices using the WNR facility. The TRIUMF neutron beam also contains thermal neutrons that can be easily removed by a sheet of cadmium. The ability to choose whether thermal neurons are present is a useful attribute not possible at the WNR.

An electron paramagnetic resonance study has been carried out on B‐ and P‐doped oxide films on Si. The principal defects are the boron‐oxygen‐hole‐center (BOHC) and phosphorus‐ oxygen‐hole‐center (POHC), which are unpaired electrons on oxygen atoms with B or P in the near vicinity. Our results demonstrate that the centers are activated by hole capture. We find that holes are trapped very efficiently in both B‐ and P‐doped dielectrics; however, electrons are more efficiently trapped in the B‐doped dielectrics. We find that the electrical data can be explained by assuming that the precursor to the BOHC is negatively charged and the precursor to the POHC is electrically neutral.

Neutron-induced single-event latchup has been studied in SRAMs manufactured by several different vendors. These SRAMs span different cell designs (six-transistor and four-transistor cells), technology generations (0.25 /spl mu/m to 0.14 /spl mu/m) and power supplies (5 V to 1.5 V). While some technologies appear to be latchup-free in neutron environments, others have neutron-induced latchup failure-in-time (FIT) rates as high as 300 FIT/Mbit at room temperature and maximum rated voltage. Latchup FIT rates increase dramatically with temperature. The observed latchup rates can lead to very high failure rates in systems with large amounts of memory, and cannot be circumvented using error correction.

Transmission electron microscopy (TEM) [1] and scanning capacitance microscopy (SCM) [2] have become common failure analysis tools at Sandia for new product development, process validation, and yield enhancement. These two techniques provide information that cannot be obtained with other analytical techniques. The information provided by these two techniques has been instrumental in identifying the root causes of several yield-limiting defects in CMOS IC technologies at Sandia. This paper describes an example of how TEM and SCM have been used to identify the root causes of SOI device failures. The corrective actions taken to reduce defects and improve yield are also described.