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Discovery of wideband gap semiconductor materials has boosted the field of power electronics. Fabrication of HEMT has overcome the drawback of lower mobility and ON‐state current of wide bandgap materials. However, due to lower ON‐state current earlier proposed devices suffer from poor ON‐state resistance; hence, in this work dual gate technique has been proposed. To further switch the device characteristics from Normally‐ON to Normally‐OFF state, recessed gate technique is used. Device physics, analog parameters of Normally‐OFF dual‐recessed gate metal insulator semiconductor AlGaN/GaN HEMT (DRG‐MIS‐HEMT) are analyzed and compared with conventional DG‐MIS‐HEMT. To solidify the analysis, width of recessed gate has been varied from 2 nm to 28 nm. At recessed gate width (=28 nm), proposed device resulted RON = 1.98 Ω‐cm2, threshold voltage 1.25 V, IDS of 1100 mA/mm, ION/IOFF = 1014 and ft = 10 GHz. Proposed device also resulted in improved linearity characteristics over single gate structure. In future, the proposed device can be used for RF applications. [ABSTRACT FROM AUTHOR]

The instability of THz plasma waves propagating along a channel of field-effect transistors opens up a new mechanism of emission of THz waves. In this work, we investigate the instability of THz plasma waves in field-effect transistors in the presence of quantum effects and nonideal boundary condition at the source and the drain by using the quantum hydrodynamic model. The results show that the THz plasma waves will be unstable when the gate–source capacitances are larger than gate–drain capacitances and the instability increment can be increased by increasing gate–source capacitances or decreasing gate–drain capacitances. The results of this work give nano-field-effect transistors an advantage in achieving real THz oscillations. [ABSTRACT FROM AUTHOR]

This paper presents a novel device called Field Effect Photodiode (FEPD) to overcome the inherent drawbacks of PIN Photodiode (PIN-PD) and control the output photocurrent. Also, the proposed PIN-PD can be applied as a fast optical switch that provides a desired ION/IOFF ratio for optical applications in the nanoscale regime. The proposed device combines a Metal Semiconductor Field Effect Transistor (MESFET) and a regular PIN-PD device that can convert the incident light with photon energy greater than the semiconductor's bandgap to the regulated photocurrent by changing the gates bias which mounted over the absorption region. The significant parameters such: responsivity, output current in both the ON and OFF states, dark current, and ION/IOFF ratio that play key roles in the optical applications have been extracted. To extract and illustrate the electrical and optical results of both the regular PIN-PD and the proposed FEPD in this work, we have used TCAD tools as a semiconductor simulator. [ABSTRACT FROM AUTHOR]

We fabricated AlN metal semiconductor field effect transistors (MESFETs) with an epitaxially grown n-type AlN channel layer and characterized the temperature dependence of their device properties. As the temperature was varied from room temperature to 500°C, maximum drain current increased from 0.42 to 45 mA/mm and maximum transconductance increased from 0.05 to 4.5 mS/mm. This enhanced device performance with increasing temperature is attributed to increased carrier concentration in n-type AlN due to the large ionization energy of Si donors. Owing to a large Schottky barrier height of 2.08 eV for the Ni gate electrode/n-type AlN interface, reverse leakage current is less than $10^{-{10}}$ A/mm at temperatures ranging from room temperature to 500°C. Off-state breakdown voltage is as high as 1720 V for gate-drain spacing of 16 ${\mu }\text{m}$. These results indicate that AlN MESFETs are promising for high-voltage electronic devices operating at high temperature. [ABSTRACT FROM AUTHOR]

This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance RON, breakdown voltage VBR, threshold voltage VTH, and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance RDSon, where a 14 % increase was observed after 6 · 107 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I -- V curves was observed with considerable impact on the RON where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance CDG and input capacitance Cin was observed in all three types of analysed structures. DLTS was used to verify the generation/ activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO2 and on interfaces were detected on stressed samples. [ABSTRACT FROM AUTHOR]

In this article, an improved parasitic-aware design technology co-optimization (DTCO) for gate-all-around nanosheet field effect transistor (GAA-NSFET) at 3 nm node is proposed. The presented DTCO flow owns two distinct features. First, a novel de-embedding strategy is designed to avoid the repeated calculation of gate–source/drain contact capacitance. Second, the parasitic resistance of the middle-end-of-line (MEOL) and back-end-of-line (BEOL) is accurately extracted, combing the front-end-of-line (FEOL) simulation and the calculation of MEOL/BEOL equivalent interconnect length. The power, performance, and area (PPA) of the benchmark circuit [15-stage ring oscillator (RO)] are collaboratively optimized. Considering the limitation of contacted gate pitch (CGP) and the process effects, the compromise of structure parameters is studied. GAA-NSFET architecture with 48% reduction in power consumption, 26% increase in speed, and 46% reduction in area is achieved, satisfying the scaling requirement from 5 to 3 nm node. All data here provide an optimization and design foundation for GAA-NSFET in future 3 nm technology node. [ABSTRACT FROM AUTHOR]

Unexpected threshold voltage (${V}_{\text {TH}}$) behaviors are experimentally observed in gallium nitride (GaN)-on-Si metal-oxide-semiconductor-channel high electron mobility transistors (MOSc-HEMTs) with fully recessed gate and back-barrier (BB): 1) ${V}_{\text {TH}}$ increases with decreasing gate length (${L}_{G}$) (${V}_{\text {TH}}$ roll-up); 2) discrepancies between ${V}_{\text {TH}}$ values extracted from drain current characteristics ${I}_{\text {D}}$ (${V}_{\text {G}}$) (${V}_{\text {TH}\_\text{IV}}$) and from gate-to-channel capacitance characteristics ${C}_{\text {GC}}{(}{V}_{\text {G}}$) (${V}_{\text {TH}\_\text{CV}}$); and 3) significant dependence of ${V}_{\text {TH}\_\text{CV}}$ with frequency. Using TCAD simulations and experimental measurements, it is demonstrated that conduction band confinement, especially at gate corners, is responsible for these peculiar ${V}_{\text {TH}}$ behaviors. This band confinement is strengthened by the fully recessed gate configuration coupled with the proximity of a BB. It depends on recessed gate topology and BB efficiency. [ABSTRACT FROM AUTHOR]

In recent years, the use of memristors in circuits design has rapidly increased and attracted research interest. Advances have been made to both the size and the complexity of memristor designs. Therefore, computer aided design tools are required to handle memristor‐based large‐scale designs. A comprehensive automatic framework for the design and synthesis of large‐scale memristor‐complementary metal‐oxide‐semiconductor (CMOS) circuits is described herein. This framework provides a synthesis approach that can be applied to all memristor‐based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor‐based logic cells to generate a standard cell library file for large‐scale simulation. The proposed architecture is based on RRAM and ReRAM redox‐based devices and the memristor ratioed logic design approach. The proposed framework is implemented in the Cadence Virtuoso schematic‐level environment and was verified with Verilog‐XL, MATLAB, and the electronic design automation synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. Nevertheless, it is perfectly suitable for signal processing applications that require MATLAB functions to produce text files with hex values in order to overcome the limitations of the simulation environment. A framework is deployed herein for design of the memristor‐based parallel 8‐bit adder/subtractor and a 2D memristive‐based median filter. Both proposed designs memristor‐based adder/subtractor and memristive median filter have significant power reductions of 66% and 16% respectively, when compared to the same designs using CMOS technology. [ABSTRACT FROM AUTHOR]

Discharge in dielectric liquid is an active field of research involved in many technological applications. Such multiple discharges are often applied during an experiment and that the electrode and liquid are altered by these stochastically behaving discharges. Therefore, it is important to address the variation of discharge characteristics as a function of discharge occurrence. In this study we analyze the electrical characteristics of multiple discharges run at low repetition rate (5 Hz) in a liquid of known initial composition using an electrode with a specific geometry. The discharges are run continuously until they fail to occur due to the increase in gap distance, and the recorded voltage and current waveforms are processed using an algorithm in order to determine the probability of discharge occurrence, breakdown voltage, discharge current, and discharge delay. The injected charge and energy of each discharge are also calculated. Furthermore, the effects of applied voltage, pulse width, electrode configuration, and liquid composition on the characteristics of the discharge are investigated. The obtained results demonstrate that the highest and lowest numbers of occurred discharges are achieved using the plate-to-plate and pin-to-pin configurations, respectively. Moreover, the composition of the liquid has an appreciable effect on the discharge current, as well as on electrode erosion. For discharges in water and cyclohexane, we measured the lowest and highest current, respectively. As for the erosion rate, it was comparable for the three liquid hydrocarbons but relatively smaller than that in water. The plot of breakdown voltage as a function of discharge current varies depending on the discharge parameters and displays regions that may be linked to the ignition mechanisms. The original data reported herein is of great significance for various applications that utilize repetitive discharges in liquid. [ABSTRACT FROM AUTHOR]

We report high-performance amorphous Indium-Gallium-Zinc-Oxide nanowire field-effect transistors ($\alpha $ -IGZO NW-FETs) featuring an ultrascaled nanowire width (${W}_{{\mathrm {NW}}}$) down to ~20 nm. The device with 100 nm channel length (${L}_{{\mathrm {CH}}}$) and ~25 nm ${W}_{{\mathrm {NW}}}$ achieves a decent subthreshold swing (SS) of 80 mV/dec as well as high peak extrinsic transconductance (${G}_{m,{\mathrm {ext}}}$) of $612~\mu S/\mu \text{m}$ at a drain–source voltage (${V}_{{\mathrm {DS}}}$) = 2 V ($456~\mu S/\mu \text{m}$ at ${V}_{{\mathrm {DS}}}$ = 1 V). The good electrical properties are enabled by using an ultrascaled 5 nm high- ${k}$ HfO2 as the gate dielectric, a water-free ozone-based atomic layer deposition (ALD) process, and a novel digital etch (DE) technique developed for indium-gallium-zinc-oxide (IGZO) material. By using low-power BCl3-based plasma treatment and isopropyl alcohol (IPA) rinse in an alternating way, the DE process is able to realize a cycle-by-cycle etch with an etching rate of ~1.5 nm/cycle. The scaling effects on device performance have been analyzed as well. It shows that the downscaling of ${W}_{{\mathrm {NW}}}$ improves the SS notably without sacrificing ON-state performance, and the shrinking of ${L}_{{\mathrm {CH}}}$ boosts the ${G}_{m,{\mathrm {ext}}}$. The ultrascaled $\alpha $ -IGZO NW-FETs could play an important role in applications where high performance and high density are highly desired. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) are widely used as amplifying transducers of biological signals due to their high transconductance and biocompatibility. For implantable applications that penetrate into tissue, OECTs need to be integrated onto narrow probes. The scarcity of real estate necessitates the use of small local gate electrodes and narrow interconnects. This work shows that both of these factors lead to a decrease in the maximum transconductance and an increase in gate voltage required to attain this maximum. This work further shows that coating the gate electrode with a thick conducting polymer improves performance. These findings help guide the development of efficient OECTs on implantable probes. [ABSTRACT FROM AUTHOR]

This work presents a comparative study on the thermal and selfheating effects of ion-implanted MESFETs based on different compound semiconductors. The impact of self-heating effect on the drain current of the device is studied critically for different biasing arrangements. Two parameters defined as differential drain conductance (ΔGm) and degradation factor (DF) have been introduced and their values are calculated considering self-heating effect for devices based on different materials. Morever, the impact of selfheating effect on the cut-off frequency and maximum operating frequency of the device is studied. In addition, the impact of ambient temperature on the threshold voltage of the device is presented for different channel materials. [ABSTRACT FROM AUTHOR]

The use of active phased antenna arrays (APAAs) makes it possible to redistribute the information capacity of the communication system by scanning independent beams with electronic control. The process of creating APAAs is a solution to a multifactorial problem under the conditions of a significant number of requirements and restrictions imposed on onboard APAAs as part of a spacecraft. In this study the options for constructing multibeam receiving antenna systems based on APAAs are considered. The criteria for choosing radiators for antennas of various ranges and purposes are presented. The estimates of the energy characteristics of the APAA Ka-, C-, and S-bands are given. Recommendations for ensuring the electromagnetic compatibility of communication systems are given. It is shown that the use of phase shifters based on gallium arsenide field-effect transistors with a Schottky gate in a passive connection makes it possible to reduce the power consumption in control circuits without harming the technical parameters. [ABSTRACT FROM AUTHOR]

Temperature sensor is one of the primarily developed and most proverbially utilized sensors. Owing to the limitations of their characteristics (stability, thermal conductivity, and thermal contact area), traditional temperature sensors may exhibit drawbacks of high production cost and large volume. In this paper, a three-dimensional (3D) buried-gate graphene field effect transistors (GFETs) are proposed as a novel sensor for temperature detection, which possess a 3D microtube structure by self-rolled-up technology. Compared to conventional two-dimensional (2D) devices, the 3D devices would have tinier area and higher integration. Two main reasons that would affect the resistance of the graphene are the graphene electro-phonon coupling and the thermal expansion effect. In addition, by applying the COMSOL Multiphysics software, it has been demonstrated that the microtube would deform to a certain extent when the temperature increases. And the strain on the 3D devices is proved to be greater than that of the 2D devices. Experimental results show that 3D GFETs could realize temperature detection between 30 °C and 150 °C, and its resistance increases with temperature rising. Furthermore, the maximum achieved temperature coefficient of resistance (TCR) is 0.41% °C−1 and the hysteresis error is only 3.85%. By virtue of the 3D microtube, not only more superior temperature detection could be achieved, but also more devices are integrated in unit area. The 3D temperature sensor possesses superior sensitivity, repeatability and stability, which contributes a new approach to develop the high-performance temperature sensor. [ABSTRACT FROM AUTHOR]

A small signal equivalent model of surrounding gate MOSFET incorporating fringing capacitances has been proposed and detailed in this paper. Detail modeling of the fringing (outer and inner both) capacitances of surrounding gate MOSFETs are considered here. Considering fringing capacitance, also the gate to drain/source and effective gate capacitances have been calculated for the proposed model. Low frequency Y-parameters (admittance parameters) of the SRG MOSFET are derived from the proposed model and expressed using real/imaginary function for different biasing condition. RF/analog performance parameters like Gate input capacitance (CGG), transport time delay (τ), input resistance (Rin), trans-conductance (gm), channel conductance (gds) etc have been evaluated. Figure of Merit (FOM) parameters like cut off frequency, gmRo, maximum oscillation frequency etc of the proposed model has been evaluated to study the effect of parasitic capacitances on the RF performances in depth. Extensive simulations using Silvaco ATLAS have been done to verify the proposed models. Matching of the simulated results with the model data demonstrate the correctness of the proposed model. It has been observed that the fringing capacitances can deteriorate the ac characteristics of the nano dimensional surrounding/cylindrical gate MOSFET. [ABSTRACT FROM AUTHOR]

A model for the peak frequency in the imaginary part of ${Y}_{{22}}$ (Im(${Y}_{{22}}{))}$ based on the bias for gallium nitride (GaN) high electron mobility transistors (HEMTs) is investigated while considering both self-heating (SH) and Poole–Frenkel (PF) (electric field) effects. The peak frequency of Im(${Y}_{{22}}{)}$ corresponds to the emission time constant of the trap in the GaN layer. In this study, ${Y}_{{22}}$ for GaN HEMTs were measured for low frequencies at which the traps respond by significantly changing not only drain voltage (${V}_{\text {DS}}{)}$ but also gate voltage (${V}_{\text {GS}}{)}$. Because the vector network analyzer used ac with an extremely small power of −20 dBm as a signal for sensing the trap, the trap properties can be measured at a fixed dc bias. In this model, the SH effect is introduced to replace the ambient temperature in the conventional Arrhenius equation by simulating the lattice temperature. The PF effect introduces the apparent activation energy, based on the simulated electric field at the channel under the gate field edge of the drain side. The electric field is related to the voltage between the gate and drain. This model is consistent with the experimental data for a wide range of transistor biases, i.e., from the ${V}_{\text {GS}}$ near the pinch-off voltage to the ON-state condition, and the ${V}_{\text {DS}}$ in the saturation region at ambient temperatures between 23 °C and 160 °C. Furthermore, using this model, we confirmed that the PF effect dominates at a low ${V}_{\text {GS}}$ of −2 V near the pinch-off. [ABSTRACT FROM AUTHOR]

In this work, a novel n-InxGa1-xN/N-gallium nitride (GaN) homotype heterostructure is proposed instead of P-GaN/N-GaN homostructure to produce impact-ionization-avalanche-transit-time (IMPATT) diode. Conventional GaN IMPATT device will lose its working ability due to the immature p-type GaN, so this work predicts that the n-InxGa1-x N/N-GaN IMPATT diode can be an alternative to the GaN p-n IMPATT diode; thus, the difficulty of the p-type doping process is avoided. The dc and RF large-signal output characteristics with different compositions are investigated in detail. The simulation results show that the power and efficiency of the novel structure device increase when the In composition increases. When the In composition is greater than 0.4, the performance of the homotype heterojunction IMPATT is better than that of p-n IMPATT. Moreover, homotype heterojunction IMPATT is better in frequency bandwidth, and it can hold greater bias current density than p-n IMPATT. Meanwhile, the performance of homotype heterojunction IMPATT does not depend on the thickness of the InGaN layer, but it decreases as the thickness of the p-type region in p-n IMPATT increases. As it has greater potential in the application, this work brings a reference for the design and manufacture of IMPATT devices based on wide bandgap semiconductor materials, especially GaN materials. [ABSTRACT FROM AUTHOR]

The article focuses on dangling bond–free surface makes it extremely difficult to deposit gate dielectrics with high-quality interface in metal-oxide-semiconductor (MOS) field-effect transistors (FETs). It mentions ultrathin two-dimensional (2D) semiconductors are regarded as a potential channel material for low-power transistors with small subthreshold swing and low leakage current. It also mentions transferred metal gate (TMG) and back gate enable logic functions.

The discovery of ferroelectricity in the fluorite structure based hafnium oxide (HfO2) material sparked major efforts for reviving the ferroelectric field effect transistor (FeFET) memory concept. A Novel metal-ferroelectric-metal-ferroelectric-insulator-semiconductor (MFMFIS) FeFET memory is reported based on dual ferroelectric integration as an MFM and MFIS in a single gate stack using Si-doped Hafnium oxide (HSO) ferroelectric (FE) material. The MFMFIS top and bottom electrode contacts, dual HSO based ferroelectric layers, and tailored MFM to MFIS area ratio (AR-TB) provide a flexible stack structure tuning for improving the FeFET performance. The AR-TB tuning shows a tradeoff between the MFM voltage increase and the weaker FET Si channel inversion, particularly notable in the drain saturation current ID(sat) when the AR-TB ratio decreases. Dual HSO ferroelectric layer integration enables a maximized memory window (MW) and dynamic control of its size by tuning the MFM to MFIS switching contribution through the AR-TB change. The stack structure control via the AR-TB tuning shows further merits in terms of a low voltage switching for a saturated MW size, an extremely linear at wide dynamic range of the current update, as well as high symmetry in the long term synaptic potentiation and depression. The MFMFIS stack reliability is reported in terms of the switching variability, temperature dependence, endurance, and retention. The MFMFIS concept is thoroughly discussed revealing profound insights on the optimal MFMFIS stack structure control for enhancing the FeFET memory performance. [ABSTRACT FROM AUTHOR]

In this paper, the analysis of SiGe source-based heterojunction Tunnel FET device is reported. The parameters like transconductance (gm), device efficiency (gm/ID), gate-source capacitance (CGS), gate-drain capacitance (CGD), cut-off frequency (fT), and gain-bandwidth product (GBP) are studied. DC, as well as AC simulations, have been performed on the proposed device. We have achieved an ON current of 0.537 mA/µm and an OFF current of 13 fA/µm, thus achieving ION/IOFF ratio as 3.72 × 1010. The values obtained for the transconductance are 0.68 milliSiemens, cut-off frequency is 446 GHz, gate-source capacitance is 0.387 femto Farads, and gate drain capacitance is 0.694 femtoFarads. The lower values of parasitic capacitances enable the device to be helpful for the low power and analog/RF applications even at high frequencies. The device has also been investigated for the temperature analysis concerning the drain current and the capacitance calculations. It was observed that the OFF currents are strongly dependent on the temperature in the drain current characteristics of the device. All the simulations have been performed on Visual TCAD (licensed version 1.9.2–3). [ABSTRACT FROM AUTHOR]

A low Schottky barrier height (SBH) at source/drain contact is essential for achieving high drive current in atomic layer MoS2-channel-based field effect transistors. Approaches such as choosing metals with appropriate work functions and chemical doping are employed previously to improve the carrier injection from the contact electrodes to the channel and to mitigate the SBH between the MoS2 and metal. Recent experiments demonstrate significant SBH reduction when graphene layer is inserted between metal slab (Ti and Ni) and MoS2. However, the physical or chemical origin of this phenomenon is not yet clearly understood. In this work, density functional theory simulations are performed, employing pseudopotentials with very high basis sets to get insights of the charge transfer between metal and monolayer MoS2 through the inserted graphene layer. Our atomistic simulations on 16 different interfaces involving five different metals (Ti, Ag, Ru, Au, and Pt) reveal that (i) such a decrease in SBH is not consistent among various metals, rather an increase in SBH is observed in case of Au and Pt; (ii) unlike MoS2-metal interface, the projected dispersion of MoS2 remains preserved in any MoS2-graphene-metal system with shift in the bands on the energy axis. (iii) A proper choice of metal (e.g., Ru) may exhibit ohmic nature in a graphene-inserted MoS2-metal contact. These understandings would provide a direction in developing high-performance transistors involving heteroatomic layers as contact electrodes. [ABSTRACT FROM AUTHOR]

A comprehensive study on top- and bottom-illuminated Al0.5Ga0.5N/AlN metal-semiconductor-metal (MSM) photodetectors having different AlGaN absorber layer thickness is presented. The measured external quantum efficiency (EQE) shows pronounced threshold and saturation behavior as a function of applied bias voltage up to 50V reaching about 50% for 0.1 lm and 67% for 0.5 μm thick absorber layers under bottom illumination. All experimental findings are in very good accordance with two-dimensional drift-diffusion modeling results. By taking into account macroscopic polarization effects in the hexagonal metal-polar +c-plane AlGaN/AlN heterostructures, new insights into the general device functionality of AlGaN-based MSM photodetectors are obtained. The observed threshold/saturation behavior is caused by a bias-dependent extraction of photoexcited holes from the Al0.5Ga0.5N/AlN interface. While present under bottom illumination for any AlGaN layer thickness, under top illumination this mechanism influences the EQE-bias characteristics only for thin layers. [ABSTRACT FROM AUTHOR]

With the development of semiconductor technology, the size of traditional metal oxide semiconductor field effect transistor devices continues to decrease, but it cannot meet the requirements of high performance and low power consumption. Low power tunneling field effect transistor (TFET) has gradually become the focus of researchers. This paper proposes a novel T-shaped gate TFET based on the silicon with the negative capacitance (NC-TGTFET). On the basis of TGTFET, ferroelectric material (HZO) is used as gate dielectric. The simulation results show that, compared with the traditional TGTFET, the opening order and sensitivity of the two tunneling junctions are different. The influences of thickness and the doping concentration of pocket and ferroelectric material properties on the characteristics of NC-TGTFET is also discussed by Sentaurus simulation tool. Furthermore, the negative capacitance of ferroelectric material makes NC-TGTFET have a very steep subthreshold swing (18.32 mV/dec) at the range of drain current from 1 × 10−15 to 1 × 10−7 A μm−1. And the on-state current (Vg = 0.5 V, Vd = 0.5 V) is 1.52 × 10−6 A μm−1. [ABSTRACT FROM AUTHOR]

In this paper, the influence of electron irradiation on DC and RF characteristics of InP-based HEMTs with different gate widths were studied by irradiation experiment. The results show that the value of channel current (IDS) and transconductance (gm) are decreased for device with different gate width after electron irradiation, which is mainly due to the reduction of mobility in the channel by the irradiation-induced defects. However, the carrier concentration in the channel has a little change. Compared with the device with 100 μm gate width, IDS and gm of the device with 40 μm gate width were decreased by 1.5% and 3%. Meanwhile, the forward gate current decreased due to the increase of series resistance of gate contact caused by electron irradiation. The interface defects induced by electron irradiation induced the increase of the reverse gate current. Additionally, the current gain cut-off frequency (fT) and maximum oscillation frequency (fmax) were reduced by 19.8% and 10.9% for device with 40 μm gate width, and the fT and fmax were only reduced by 7.1% and 8.2% for device with 100 μm gate width. The experimental results indicate that designing a reasonable structure is an effective method to enhance the radiation resistance in InP-based HEMTs, and this method can also be utilized in other semiconductor devices. [ABSTRACT FROM AUTHOR]

In this paper, a novel silicon carbide (SiC) trench metal oxide semiconductor field effect transistor (MOSFET) with improved reverse recovery charge and switching energy loss is proposed and investigated utilising ISE‐TCAD simulations. The proposed structure features an integrated Schottky barrier diode on one side‐wall of the trench below the P‐base region, and an inserted thicker oxide layer between the polysilicon gate and source metal on one side‐wall of the trench. The simulation results show that compared with Infineon's CoolSiC™ Trench MOSFET, the proposed device decreases the gate charge Qg by 29.2%, leading to significantly improved figures of merit (Ron,sp × Qg). The reverse recovery charge Qrr and peak reverse recovery current (IRRM) are reduced by 64.1% and 66.0%, respectively. Meanwhile, the total switching energy loss decreases 36.7% for the dynamic performance. [ABSTRACT FROM AUTHOR]

In0.71Ga0.29As/InP (12/2 nm) quantum well MOSFETs using sacrificial amorphous silicon (a:Si) spacers to achieve low parasitic capacitance are fabricated. Radio frequency characterization of 73 devices is used to study the intrinsic and extrinsic capacitances. The total gate intrinsic parasitic capacitance of 0.55 fF/ $\mu \text{m}$ is achieved with an intrinsic gate capacitance of $0.39~\mu \text{F}$ /cm2. The various parasitic capacitances are modeled using finite element electrostatic simulations, and semi-analytical expressions are provided. A device with a gate length ${L}_{g}=80$ nm has SS $_{\text {min}}=168$ mV/dec, dc transconductance ${g}_{\textit {m,e}} =1.0$ mS/ $\mu \text{m}$ at ${V}_{\text {DS}}=0.5$ V, and exhibits a peak cutoff frequency $\it f_{\!{T}} $ of 243 GHz, and a maximum oscillation frequency $\it f_{\text {max}}$ of 147 GHz at ${V}_{\text {GS}}=0.25$ V, ${V}_{\text {DS}}= {1}$ V. [ABSTRACT FROM AUTHOR]

In AlGaN/AlN/GaN heterostructures, as a result of spontaneous and piezoelectric polarization with the occurrence of donor surface states, a triangular potential well is formed on the interface, filled with two-dimensional electron gas with a concentration of 1013 cm-2 and a mobility of 2000 cm²/(V s). An increase of the potential in the channel of an AlGaN/AlN/GaN high electron mobility transistor, caused by the flow of the drain current, results in: a decrease of the two-dimensional electron gas concentration, an increase of electric field and an increased drift velocity of electrons. At the drainage end of the gate, the electrons reach their maximum drift velocity which is correlated with the material limitations. Consequently, a rapid nonlinear increase of the channel potential, a decay of the twodimensional electron gas channel, and pushing of the electrons towards the buffer occurs. The vertical current component starts to increase then while the horizontal current component decreases. Moreover, between the gate and the drain electrodes the two-dimensional electron gas channel is gradually rebuilt due to the presence of a low electric field. The Advanced Physical Models of Semiconductor Devices software was used to simulate these phenomena in the structure of an AlGaN/AlN/GaN high electron mobility transistor. [ABSTRACT FROM AUTHOR]

In this Letter, the p-GaN high electron mobility transistor (HEMT) with hybrid drain of recessed Schottky (RS) and p-GaN isolation blocks' drain (HSP drain) is proposed and fabricated for good reverse blocking capability. The related operation mechanism has been investigated and revealed. The proposed device features a drain terminal consisting of the array-distributed recessed Schottky and p-GaN isolation blocks. Based on the features, the reverse leakage current (5 × 10−9 A/mm at VDS = −100 V) is obviously reduced by two orders of magnitude compared with that (5 × 10−7 A/mm) of p-GaN HEMTs only with recessed Schottky (RS) drain, which is the lowest leakage current among the reported GaN-on-Si reverse blocking transistors. The introduction of these p-GaN isolation blocks has a negligible impact on Von (Von = 0.63 V). Therefore, a good improvement in the trade-off between the reverse leakage current and Von could be achieved because of the significant reduction in the reverse leakage current without sacrificing Von. In addition, the reverse breakdown voltage of −800 V at 1 μA/mm with a substrate grounded in the proposed device is evidently improved compared with the counterpart (−680 V), which is attributed to effective alleviation of the high electric field near the HSP drain. These results demonstrate the significance and potential of p-GaN HEMTs with HSP drain in reverse blocking applications. [ABSTRACT FROM AUTHOR]

ScAlN/GaN dielectric superjunction high-electron-mobility transistors (HEMTs) with high-k passivation layer Bi1.5Zn1.0Nb1.5O7 (BZN) are demonstrated for enhancement of breakdown voltage. The BZN thin film deposited by RF magnetron sputtering has a dielectric constant of 192 after postdeposition annealing at 400 °C for 10 min. The HEMT with Lg = 200 nm and Lsd = 2.0 μ m has a maximum current density of 1.98 A/mm, a maximum transconductance of 0.52 S/mm, and a threshold voltage of Vth = −3 V. With the use of SiN/BZN/SiN sandwiched passivation layer, the average value of breakdown voltage is improved from 68.9 to 121.5 V, due to the reduction of the peak electrical field between the gate and the drain. The device has a cutoff frequency (ƒT) and maximum oscillation frequency (ƒmax) of 59 and 69 GHz, respectively. Overall, the devices exhibit a significantly higher breakdown voltage with essentially the same ƒT and ƒmax values. Pulse measurements suggest that SiN/BZN/SiN has a similar passivation effect in comparison with devices passivated by a SiN-only layer. This work demonstrates that high current and high breakdown voltage can be achieved simultaneously on semiconductor heterostructures with a high sheet charge density by integration of high-k dielectrics. [ABSTRACT FROM AUTHOR]

This paper proposes a reasonable radiation-resistant composite channel structure for InP HEMTs. The simulation results show that the composite channel structure has excellent electrical properties due to increased modulation doping efficiency and carrier confinement. Moreover, the direct current (DC) and radio frequency (RF) characteristics and their reliability between the single channel structure and the composite channel structure after 75-keV proton irradiation are compared in detail. The results show that the composite channel structure has excellent radiation tolerance. Mechanism analysis demonstrates that the composite channel structure weakens the carrier removal effect. This phenomenon can account for the increase of native carrier and the decrease of defect capture rate. [ABSTRACT FROM AUTHOR]

In order to develop a method to extract the parameters of the two inherent Schottky contacts from a single current-voltage (I-V) characteristic curve, the I-V characteristics of metal-semiconductor-metal (MSM) diodes with asymmetric Schottky barrier heights are theoretically investigated using the thermionic emission model. The MSM diode structure is commonly used because an additional MS interface is required for the electrical characterization of MS diodes. A finite charge-injection barrier is generally formed at the additional interface. When a local maximum was detected in the first-order derivative of the measured I-V characteristics for a MSM diode, the parameters for the Schottky contacts, the zero-bias barrier heights of both MS interfaces, the series resistance of the MSM diode, and the effective ideality factor for the MS diode with a higher barrier could be extracted using this method. [ABSTRACT FROM AUTHOR]

High-performance AlGaN/GaN lateral Schottky barrier diodes (SBDs) with recess structure and dual metal nitride anodes were demonstrated. With high work-function and nonrecess structure, a NiN anode enhances the breakdown voltage (BV), while a TiN anode reduces the turn-on voltage (VON) due to its low work-function and contact to the two-dimensional electron gas (2DEG) layer directly on a recess structure. As the length of the NiN anode (Lr) on the nonrecess region decreases from 75 to 3 μm, VON is reduced from 0.56 to 0.30 V, while the reverse leakage current slightly increases from 3 × 10−4 to 2 × 10−3 A/cm2 at the bias of −10 V. The lateral AlGaN/GaN SBD with a Lr of 3 μm at a distance of cathode–anode (LAC) of 20 μm achieves a high BV of 1.62 kV, an ultralow VON of 0.30 V and a small capacitance of 6.0 pF at zero bias with little degradation on ON-resistance, indicating superior potential application in high-frequency and high-power devices. [ABSTRACT FROM AUTHOR]

Atomic layer etching (ALE), a cyclic process of surface modification and removal of the modified layer, is an emerging damage-less etching technology for semiconductor fabrication with a feature size of less than 10 nm. Among the plasma sources, inductively coupled plasma (ICP) can be a candidate for ALE, but there is a lack of research linking discharge physics to the ALE process. In this study, we comprehensively investigated the discharge physics of ICPs with a radio frequency (RF) bias and Ar/C4F6 mixture to be considered for the ALE process. Detailed studies on the discharge physics were conducted in each step of ALE (i.e., modification step, removal step) as well as the whole cycle as follows: (1) In the general ALE cycle, plasma properties dependent on the chamber geometry and the discharge mode of the ICP were analyzed; (2) in the modification step, a plasma instability with molecular gas was observed. The timescale for molecular gas removal was also investigated; (3) in the removal step, changes in plasma characteristics with the RF bias power were studied. Based on measurements of these plasma physical parameters, the discharge condition for ALE was optimized. ALE was performed on various thin films, including a-Si, poly c-Si, SiO2, and Si3N4. For each thin film, thicknesses of 0.5–2.0 nm were etched per cycle, as in quasi-ALE. Finally, ALE was performed on a patterned wafer, and the etch thickness of 0.6 nm per cycle and fine etch profile were obtained. [ABSTRACT FROM AUTHOR]

In this paper, we report the performance of a novel circular double-gate (CDGT) silicon-on-insulator metal oxide semiconductor field effect transistor (MOSFET). We explore a variety of device configurations that are possible by making changes in the pad height in terms of a raised top, bottom, or top and bottom (both). The results demonstrate that the best device configuration is a raised both CDGT with an internal pad as a drain. For the above configuration, the impact of a junctionless mode is further analyzed and the optimum performance is obtained with a doping level of 1 × 1018 cm−3. The device exhibits good electrical characteristics, with an ON/OFF current ratio of 3.73 × 105, a near-ideal subthreshold slope of 66.9 mV dec−1, and a small drain-induced barrier lowering of ∼35 mV V−1. Among various circular MOSFETs, the CDGT device exhibits an optimum delay performance of 2 ps based on a two-stage inverter analysis. [ABSTRACT FROM AUTHOR]

In this letter, we propose a comprehensive benchmarking method to simultaneously address mobility enhancement and density-of-states bottleneck in advanced field-effect-transistors (FETs) with novel high-mobility (high- $\mu$) channel materials, where we focused on conventional covalent bonding semiconductors with pure and partially ionic character. This method relies only on the measured extrinsic transconductance of a long-channel FET in the saturation regime together with the source resistance, yielding the product of the effective mobility ($\mu _{{eff}}$) and effective gate capacitance (${C}_{g\_{}{{eff}}}$). We tested this method in InxGa1–xAs quantum-well high-electron-mobility transistors (HEMTs) with various indium mole fractions, such as 0.53, 0.7, 0.8 and 1, as well as in Si n-FETs. We found that the InxGa1–xAs HEMTs with $\mu _{{eff}}$ over 10,000 cm2/ $\text{V}\cdot \text{s}$ at 300 K provided more than 20 times greater $\mu _{{eff}} \times {C}_{g\_{}{{eff}}}$ than Si n-FETs. More specifically, the product initially improved as ${x}$ increased, then showed a peak value of $10,300\,\,\mu \text{F}\cdot \text{V}^{-1}\cdot \text{s}^{-1}$ at ${x}$ of around 0.8, and degraded slightly beyond that composition. To verify the validness of the proposed method, we separately measured and analyzed ${C}_{g\_{}{{eff}}}$ and $\mu _{{eff}}$ using the split-CV technique, showing excellent agreement with the ones from the proposed method. [ABSTRACT FROM AUTHOR]

Maintaining high average fields between the gate and drain is imperative in achieving near theoretical performance in ultra-wide band gap semiconductors like $\beta $ -Ga2O3. In this letter we report on a field management strategy to reduce the peak electric field at the drain side corner of the gate by using a composite dielectric layer consisting of an extreme permittivity dielectric like BaTiO3 and a low- $\kappa $ dielectric like SiO2 overlapped over the gate electrode. Using this strategy in $\beta $ -(Al0.18Ga0.82)2O3/ Ga2O3 double heterojunction field effect transistor, we achieved a record average breakdown field of 5.5 MV/cm at a gate-drain spacing of $1.15~\mu \text{m}$ along with an improved power figure of merit of 408 MW/cm2. The reported works shows the effectiveness of integrating extreme dielectric materials with ultra-wide band gap semiconductors in significantly improving breakdown performance. [ABSTRACT FROM AUTHOR]

This paper studies a composite device composed of ferroelectric random access memory (FeRAM) and metal-oxide-semiconductor field effect transistor. The relationship between the hysteresis characteristics and VG is reported, and the on/off ratios under different writing voltages are presented. The gm–VG curve of the forward and reverse sweeping shows that under forward sweep a very clear instability appears while voltage increases. The reasons for this can be explained according to the voltage divider rule, the ID formula, and gm formula of transistors, which show that there is polarization of the ferroelectric material. Accordingly, a method is proposed to determine the critical point of the ferroelectric capacitor polarization in this 1T1C structure, which is advantageous because it identifies the appropriate reading voltage necessary for an effective program state of the 1T1C device. This method was shown in three 1T1C and three FeRAMs devices with different ferroelectric areas. Finally, this method was verified by the P–V loop of FeRAMs. [ABSTRACT FROM AUTHOR]

Gallium trioxide, β‐Ga2O3, has been recently studied due to its promising semiconducting properties as active material in transistors or Schottky diodes. Transistors with β‐Ga2O3 channels are mostly metal oxide field effect transistors (MOSFET), and they show very negative threshold voltages (Vth) in general. Metal semiconductor field effect transistors (MESFETs) with top gate are also reported with less negative Vth. Still, β‐Ga2O3 MESFETs are only a few. Here, bottom gate architecture β‐Ga2O3 MESFETs using transition metal dichalcogenide (TMD) NbS2 and TaS2 are reported. Due to the large work functions of those metallic TMDs, the MESFETs display minimum subthreshold swing of 61 mV dec−1, small Vth of −1.2 V, minimum OFF ID of ≈100 fA, and maximum ON/OFF current ratio of ≈108. Both β‐Ga2O3 Schottky diodes with TaS2 and NbS2 display good junction stability even after 300 °C measurements in 10 mTorr vacuum. When the β‐Ga2O3 MESFET with TaS2 gate is integrated as a switching FET into an organic light emitting diode (OLED) circuit, it demonstrates long‐term leakage endurance performance, maintaining an OLED brightness higher than 58% of the initial intensity after 100 s passes since the ON‐switching point, which is even superior to the performance of conventional a‐IGZO MOSFET switch. [ABSTRACT FROM AUTHOR]

In this work, flexible ferroelectric films of P(VDF‐TrFE) softened by a plasticizer are elaborated. Morphology, piezoelectric, mechanical, thermal, and crystalline properties of the films are studied. We show that the elastic constant is reduced up to 30% while increasing the remanent polarization and the piezoelectric coefficient thanks to the lubricant property of the plasticizer, helping the orientation of the crystallites. Plus, the decrease of the coercive field from 46 to 32 V/μm after an annealing at 138°C for a plasticizer content ranging between 20 and 50 wt% is observed and an explanation by based on a polymer/plasticizer demixing is provided. It leads to an easier polarization process with a significant saving in time and applied electric field reducing the breakdown voltage. Both effects could be interesting for an industrial production. Finally, a first sensor is elaborated and characterized electrically with homemade test bench. We show that the softening of the P(VDF‐TrFE) offers to the device a larger amplitude range of deformations. The combination of the flexibility with high ferroelectric properties of the plasticized P(VDF‐TrFE) make it a very promising material for biomedical sensor applications. [ABSTRACT FROM AUTHOR]

Gallium trioxide, β‐Ga2O3, has been recently studied due to its promising semiconducting properties as active material in transistors or Schottky diodes. Transistors with β‐Ga2O3 channels are mostly metal oxide field effect transistors (MOSFET), and they show very negative threshold voltages (Vth) in general. Metal semiconductor field effect transistors (MESFETs) with top gate are also reported with less negative Vth. Still, β‐Ga2O3 MESFETs are only a few. Here, bottom gate architecture β‐Ga2O3 MESFETs using transition metal dichalcogenide (TMD) NbS2 and TaS2 are reported. Due to the large work functions of those metallic TMDs, the MESFETs display minimum subthreshold swing of 61 mV dec−1, small Vth of −1.2 V, minimum OFF ID of ≈100 fA, and maximum ON/OFF current ratio of ≈108. Both β‐Ga2O3 Schottky diodes with TaS2 and NbS2 display good junction stability even after 300 °C measurements in 10 mTorr vacuum. When the β‐Ga2O3 MESFET with TaS2 gate is integrated as a switching FET into an organic light emitting diode (OLED) circuit, it demonstrates long‐term leakage endurance performance, maintaining an OLED brightness higher than 58% of the initial intensity after 100 s passes since the ON‐switching point, which is even superior to the performance of conventional a‐IGZO MOSFET switch. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) have exhibited promising performance as transducers and amplifiers of low potentials due to their exceptional transconductance, enabled by the volumetric charging of organic mixed ionic/electronic conductors (OMIECs) employed as the channel material. OECT performance in aqueous electrolytes as well as the OMIECs' redox activity has spurred a myriad of studies employing OECTs as chemical transducers. However, the OECT's large (potentiometrically derived) transconductance is not fully leveraged in common approaches that directly conduct chemical reactions amperometrically within the OECT electrolyte with direct charge transfer between the analyte and the OMIEC, which results in sub‐unity transduction of gate to drain current. Hence, amperometric OECTs do not truly display current gains in the traditional sense, falling short of the expected transistor performance. This study demonstrates an alternative device architecture that separates chemical transduction and amplification processes on two different electrochemical cells. This approach fully utilizes the OECT's large transconductance to achieve current gains of 103 and current modulations of four orders of magnitude. This transduction mechanism represents a general approach enabling high‐gain chemical OECT transducers. [ABSTRACT FROM AUTHOR]

In this article, we report a new capacitance–voltage technique C (V) to investigate the interface proprieties of MOS devices. This technique is based on surface potential modulation using time varying (ac) magnetic field. It is experimentally validated on vertical double diffusion MOSFET (VDMOSFET). Data show that the surface potential is modulated using external ac magnetic field. In fact, applying an ac magnetic field with dc voltage sweeping of VDMOSFET gate (VG), we have been able, for the first time, to modulate the surface potential and measure the gate–source (CGS) and gate–drain (CGD) capacitances as a function of gate voltage (VG) for P- and N-type transistors. Therefore, it offers a powerful tool to characterize different regions of the transistor and extract their technological and electrical parameters. [ABSTRACT FROM AUTHOR]

In this work, physical parameter‐based modeling of small signal parameters for a metal‐semiconductor field‐effect transistor (MESFET) has been carried out as continuous functions of drain voltage, gate voltage, frequency, and gate width. For this purpose, a device simulator has been used to generate a big dataset of which the physical device parameters included material type, doping concentration and profile, contact type, gate length, gate width, and work function. Five state‐of‐the‐art algorithms: multi‐layer perceptron (MLP), IBk, K*, Bagging, and REPTree have been used for creating a regression model. The symbolic regression algorithm has been used to obtain analytical expressions of the real and imaginary parts of the Scattering (S) parameters using the physics‐based generated dataset. The regression performances of all the benchmarks and the symbolic regression have been compared to references from the device simulator results. The results of the derived equations and the best algorithms have been then compared to the device simulator results, with case studies for validation. The DC performance characteristics of the MESFET have been also obtained. The proposed model can be used to predict the small signal parameters of new devices prior to development, and allows for both the device and circuit to be optimized for specific applications. [ABSTRACT FROM AUTHOR]

The gate-all-around (GAA) nanosheet (NS) junctionless transistor (JLT) is an attractive candidate for advanced technology nodes in CMOS scaling. Here, the channel width-dependent transconductance (gm) degradation and threshold voltage (Vth) shift of GAA NS JLTs were investigated via numerical simulation. Compared to bulk neutral channels, a pronounced surface accumulation channel limited the overall electrical characteristics of GAA NS JLTs at narrow widths. Additionally, the variation in Vth of GAA NS JLTs was much smaller than that in tri-gate JLTs. Quantum mechanical effects in GAA NS JLTs with a very narrow width were also investigated. [ABSTRACT FROM AUTHOR]

Operational Transconductance Amplifiers (OTAs) are the most pivotal blocks in analog circuits and systems. With the emersion of catastrophic short channel effects for Complementary Metal Oxide Semiconductor (CMOS) transistors at deep nanometric regime, the microelectronics scientists have focused on designing ultra-miniature OTAs based on non-silicon materials. During the last few years, Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA-CNTFETs) with astonishing electrical and physical properties have drawn extensive attention of nanoelectronics researchers as a potential platform to represent high-performance nanoscale OTAs. In this regard, this work aims to propose an ultra-miniature ultra-wideband OTA based on the 10 nm GAA-CNTFET technology node. The proposed OTA benefits from the ballistic transport operation of the GAA-CNTFET transistors at ultra-scaled dimensions which provide a superior bandwidth (2.88 GHz) along with suitable power consumption (44.8 μ W). The proposed OTA shows a 64.5 dB open-loop gain and a 59 dB common-mode rejection ratio at a 1 V supply voltage. Moreover, due to the utilization of the indirect feedback compensation method, the proposed GAA-CNTFET-based OTA presents an appropriate phase margin (61 ∘ ) with a smaller compensator capacitor. With the mentioned performance metrics and occupying only 0.198 μ m 2 physical area, the proposed GAA-CNTFET OTA has the potential to be considered as a replacement for nanoscale CMOS-based OTAs. [ABSTRACT FROM AUTHOR]

In this work, the impact of SiO2 dielectric channel modulation along with metalloid T-shaped source-drain on the analog-RF characteristics of gate-all-around Junctionless Nanowire Transistor (JNT) has been analysed. Metalloid T-shaped source-drain contacts create the charge plasma therefore it is also referred as Charge Plasma Transistor (CPT). Impact of different source/drain materials on band gap energy, drain current, transconductance etc. is studied. Ambipolarity, Non-linear behavior and impact of high temperature on novel CPT-JNT device have also been analysed. A dielectric modulated CPT-JNT is proposed. Results demonstrate that charge plasma technique resolve the degeneracy problem of semiconductor in junctionless transistor. Use of dielectric pocket completely reduces the ambipolar nature of CPT-JNT. Use of Charge plasma technique along with gate-all-around junctionless transistor tremendously increases transconductance, device gain (current and power). The device is well suitable for analog/RF applications. [ABSTRACT FROM AUTHOR]

This work describes the high-temperature performance and avalanche capability of normally-off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage (VTH) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance (RON) increases from 0.82 at 25 °C to 1.8 mΩ ⋅ cm2 at 200 °C. The thermal stability of VTH and RON are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below 100 μA at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage (BVAVA) with positive temperature coefficient is shown in both the quasi-static I – V sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a BVAVA over 1700 V and a critical avalanche energy (EAVA) of 7.44 J/cm2, with the EAVA comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications. [ABSTRACT FROM AUTHOR]

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and 2 μm, in an inverter circuit. At 2-μm gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors. [ABSTRACT FROM AUTHOR]