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This paper presents an energy-efficient oscillator for wireless sensor nodes (WSNs). It avoids short-circuit current by minimizing the time spent in the input voltage range from Vthn to [Vdd - \vert Vthp\vert]. A current-feeding scheme with gate voltage control enables the oscillator to operate over a wide frequency range. A test chip is fabricated in a 0.18\;\upmum CMOS process. The measurements show that the proposed oscillator achieves a constant energy-per-cycle (EpC) of 0.8 pJ/cycle over the 21–60 MHz frequency range and is more efficient than a conventional current-starved ring oscillator (CSRO) below 300 kHz at 1.8 V supply voltage. As an application example, the proposed oscillator is implemented in a switched-capacitor DC–DC converter. The converter is 11%–56% more efficient for load power values ranging from 583 pW to 2.9 nW than a converter using a conventional CSRO. [ABSTRACT FROM PUBLISHER]

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups. [ABSTRACT FROM AUTHOR]

To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology. [ABSTRACT FROM AUTHOR]

In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be configured for the computation of the DCT of any of the prescribed lengths such as 4, 8, 16, and 32. It is shown that matrix multiplication schemes involving fewer adders can be used to derive parallel architectures for 1D integer DCT of different lengths. A novel transposition buffer is designed to be used for the proposed 2D DCT architecture, which offers double the throughput without increasing the size of the transposition buffer. We determine the optimal pipeline locations in the proposed design through the precise estimation of propagation delays and the critical path so that the area-delay-product is optimized and all the output samples are obtained in the same cycle in spite of the recursive nature of the structure. Implementation results show that the proposed 2D integer DCT architectures provide significantly higher throughput per unit area than the existing designs for HEVC. [ABSTRACT FROM AUTHOR]

We lay the foundation for determining the microscopic spin interactions in two-dimensional (2D) ferromagnets by combining angle-dependent ferromagnetic resonance (FMR) experiments on high quality CrI3 single crystals with theoretical modeling based on symmetries. We discover that the Kitaev interaction is the strongest in this material with K∼-5.2  meV, 25 times larger than the Heisenberg exchange J∼-0.2  meV, and responsible for opening the ∼5  meV gap at the Dirac points in the spin-wave dispersion. Furthermore, we find that the symmetric off-diagonal anisotropy Γ∼-67.5  μeV, though small, is crucial for opening a ∼0.3  meV gap in the magnon spectrum at the zone center and stabilizing ferromagnetism in the 2D limit. The high resolution of the FMR data further reveals a μeV-scale quadrupolar contribution to the S=3/2 magnetism. Our identification of the underlying exchange anisotropies opens paths toward 2D ferromagnets with higher TC as well as magnetically frustrated quantum spin liquids based on Kitaev physics. [ABSTRACT FROM AUTHOR]

With the rapid advancement of computer graphics and three-dimensional modeling technology, the processing and optimization of three-dimensional (3D) models have become contentious research topics. In the context of mobile devices or web applications, situations may arise where it becomes necessary to load a 3D model with a substantial memory footprint in real-time or dynamically adjust the level of detail of a model based on the scene's proximity. In such cases, it is imperative to optimize the original model to ensure smoothness and responsiveness. Due to the simplicity of their algorithm, quadric error metrics (QEMs) can deliver excellent results in simplifying 3D models while maintaining high efficiency. Therefore, QEM is widely employed in engineering applications within the realm of computer graphics development. Moreover, in the pursuit of enhanced quality and efficiency, numerous scholars have improved it based on QEM algorithms. This study aims to provide a systematic review and summary of the principles and applications of current research on QEM algorithms. First, we conducted a bibliometric analysis of 128 studies in related fields spanning from 1998 to 2022 using CiteSpace. This allowed us to sort QEM algorithms and gain insights into their development status and emerging trends. Second, we delve into the fundamental principles and optimizations of the QEM algorithms to provide a deeper understanding of their implementation process. Following that, we explore the advantages and limitations of the QEM algorithms in practical applications and analyze their potential in various domains, including virtual reality and game development. Finally, this study outlines future research directions, which encompass the development of more efficient error metric calculation methods, the exploration of adaptive simplification strategies, and the investigation of potential synergies with deep learning technologies. Current research primarily centers on enhancing QEM algorithms by incorporating additional geometric constraints to better differentiate between flat and irregular areas. This enables a more accurate determination of the areas that should be prioritized for folding. Nevertheless, it is important to note that these improvements may come at the cost of reduced computational efficiency. Therefore, future research directions could involve exploring parallel computing techniques and utilizing GPUs to enhance computational efficiency. [ABSTRACT FROM AUTHOR]