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This paper reviews key memory technologies for sub-40 nm node. Physical challenges to shrink the technology are addressed for DRAM, NAND Flash, and PRAM, and potential solutions are discussed in terms of materials, processes and device structures. It is believed that DRAM can scale down to at least 30 nm node with the aid of novel capacitor materials and 3-dimentional cell transistors, and NAND Flash can scale down to at least 30 nm node with the help of high-k dielectrics and novel cell structures. PRAM will create a new market with its new functionality in near future.

The purpose of this paper is to attempt to find a plausible solution for a high density FRAM (Ferroelectric Random Access Memory). To complete this, firstly, we give a very brief but an important review of how FRAM technologies have been evolved during the past many years. Secondly, not only are a few examples demonstrated in terms of how a FRAM-embedded system is advantageous when adopted in a system but it is also put forward how FRAM can play an essential role in a fusion memory. Finally, several process technologies for integrating a reliable high-density FRAM are mentioned, accordingly resulting in very reliable cell-charge populations after full integration, along with wafer-level reliabilities.

In this study, the authors derive measures of the redistributive effect of taxes and welfare expenditures for the United States using Current Population Survey data for the years 1994, 1999, and 2004. The authors find that while income inequality increased, the redistributive effect of taxes and public transfers together reduced market income inequality by approximately 30 percent. In 2004, 88 percent of the net redistributive effect resulted from public transfers and 12 percent from taxes. The total redistributive effect would have improved by 35 percent in 2004 if horizontal inequities in taxes and public transfers could have been eliminated.

We evaluated the limit of scaling bottom electrode contact (BEC) heater size and high resistivity heater to reduce writing current. It was found that the resistivity of heater should be increased for reducing writing current below the heater size of about 50 nm without any undesirable increase of resistance of the crystalline state (SET state, Rset). It was shown in the numerical simulations that the dissipated heat loss through BEC during melting GST was decreased in the increase of resistivity of heater. In addition, we analyzed the resistance components contributing to the total set resistance. It was observed that the undesired sharp increase of Rset as the BEC size decreases below 50 nm was attributed to the resistance component of GST–BEC interface. In the case of high resistivity heater, the contributions of both incomplete crystallization and heater itself were enhanced.

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.

4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay. Ronmiddot tuning further improves the voltage and time margin by adding a user-supplied offset to auto-calibrated Ronmiddot. In addition, a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs. Measured results show that DBI DC coding reduces the peak-to-peak jitter from 65.5 ps to 44.5 ps and the voltage fluctuation from 183 mV to 115 mV at the data rate of 4 Gb/s with the 2 V.

A NAND flash memory device for sub-40-nm-node technology and beyond utilizing an asymmetric source/drain (S/D) structure to suppress short-channel effects and improve the th distribution is presented in this paper. The asymmetric S/D structure consists of a diffused junction and inversion layer which is induced by the fringe field of the gate bias voltage during NAND operation. To reduce the area overhead caused by the select transistors, a 64-cell NAND string, which is twice the number of cells used in conventional NAND devices, is also evaluated. The proposed NAND memory device is demonstrated by a 32-Mb test chip which is fabricated using a 60-nm NAND flash technology. It exhibits subthreshold slope characteristics that improved by 37% and a programmed th distribution width that improved by 35% while almost maintaining multiple-level-cell NAND flash performance requirements.

A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are proposed. The 512 Mb PRAM has achieved read throughput of 266 MB/s through the proposed schemes. The write throughput was 0.54 MB/s in internal x2 write mode, and increased to 4.64 MB/s with x16 accelerated write mode at 1.8 V supply.

This article deals with future memory technologies in the next mobile era. First concern is about whether NAND flash memory and DRAM will succeed to evolve beyond 50 nm technologies. Now, technological needs in both memories play a driving engine in pushing further for scaling of a device dimension. Secondly, entirely different types of non-volatile memories can start to penetrate main memory markets as an alternative of NAND flash memory or DRAM in the not-too-distant future. Along with 3-D access transistors, it is widely accepted that 3-D MIM capacitors with ultra high-K dielectrics and noble electrodes will extend silicon technology down to a technology node between 20 to 30 nm. With charge-trap-flash technology, NAND flash memory will extend its technology node down to 20 - 30 nm. Among the candidates for the next generation, PRAM and FRAM begin to burgeon in mass-production. Beyond a 50 nm technology node, scaling of PRAM could be successful by the development of new material and new cell structure. 3-D ferroelectric-capacitor technology is critical for FRAM to enter a 90 nm technology node and beyond.

A deep trench isolation (DTI) process with a 4 µm deep trench has been developed and successfully applied to 5-megapixel complementary metal oxide silicon (CMOS) image sensors with a 1.7 µm pixel pitch. It was found that from the results of simulations and experiments, DTI is very effective for reducing electrical crosstalk without degrading other pixel characteristics, such as full well capacity, sensitivity, and white spot density. Therefore, DTI could be a solution for obtaining a high performance for CMOS image sensors with a small pixel size of sub-2.0 µm.

We successfully developed 256Mb Phase Change Random Access Memory (PRAM) based on 0.10μ m-CMOS technologies using ring type contact. The writing current with uniform CD process variation of Bottom Electrode Contact (BEC) was achieved by improving CMP process and developing core dielectric material. Also, the ring type contact scheme provided strong reliability such as the cycling endurance and data retention time for 256 Mb high density PRAM.

We developed a 1.6 V FRAM embedded device by successfully implementing a 100 nm MOCVD-PZT capacitor with a SrRuO3 electrode and a novel additional top electrode (ATE). ATE was used for preventing hydrogen-reduction damage or metal substance damage, arising from direct application of Al or W to top electrode. In spite of excellent reliability and wide sensing window of the memory, we found that there was a problem of lift-off of the ATE layer after full integration, leading to bit failure of the product. In order to eliminate the lift-off, we developed a new ATE scheme not only by using a compressive capping- oxide layer but by improving conformal deposition of ATE. The failed bits that appear as a tail of charge distribution were cleared even under a reliability test, a bake for 100 hours at 150°C. As a result, yield loss of the device was greatly reduced.

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal times2 write and can be increased to ~2.67 MB/s with times16 write. Endurance and retention characteristics are measured to be 107 cycles and ten years at 99 degC

Activation of the extensive cross-talk among the receptor tyrosine kinases (RTKs), particularly ErbB family-Met cross-talk, has emerged as a likely source of drug resistance. Notwithstanding brilliant successes were attained while using small-molecule inhibitors or antibody therapeutics against specific RTKs in multiple cancers over recent decades, a high recurrence rate remains unsolved in patients treated with these targeted inhibitors. It is well aligned with multifaceted properties of cancer and cross-talk and convergence of signaling pathways of RTKs. Thereby many therapeutic interventions have been actively developed to overcome inherent or acquired resistance. To date, no bispecific antibody (BsAb) showed complete depletion of dual RTKs from the plasma membrane and efficient dual degradation. In this manuscript, we report the first findings of a target-specific dual internalization and degradation of membrane RTKs induced by designed BsAbs based on the internalizing monoclonal antibodies and the therapeutic values of these BsAbs. Leveraging the anti-Met mAb able to internalize and degrade by a unique mechanism, we generated the BsAbs for Met/epidermal growth factor receptor (EGFR) and Met/HER2 to induce an efficient EGFR or HER2 internalization and degradation in the presence of Met that is frequently overexpressed in the invasive tumors and involved in the resistance against EGFR- or HER2-targeted therapies. We found that Met/EGFR BsAb ME22S induces dissociation of the Met-EGFR complex from Hsp90, followed by significant degradation of Met and EGFR. By employing patient-derived tumor models we demonstrate therapeutic potential of the BsAb-mediated dual degradation in various cancers.

The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters

FRAM whose cell structure and operation is almost identical to DRAM, can ideally realize cell size and performance of DRAM. However, the density and performance of current FRAM still fall far behind those of DRAM. In this paper, innovative 1T1C FRAM technologies for ultra high reliable mega density FRAMs and future high density FRAMs are discussed. A novel electrode technology has been proved to guarantee 175°C, 10 years retention lifetime and more than 1E13 endurance lifetime of mega density 1T1C, COB FRAM with the cell size of 15F2 at 250 nm technology node. Furthermore, a cell size of 12F2 at 150 nm technology node has successfully been realized by developing innovative 200 nm thick capacitor stack technologies and novel capacitor etching technologies. Finally, critical issues of 3-D capacitor arising from 3-dimensional deposition, such as step coverage and film uniformity have been greatly improved by the modification of the MOCVD PZT feeding source and a newly introduced noble metal atomic l...

In this study we present an MOCVD-PZT-based 1.6 V operational 1T1C COB FRAM for embedded smart card applications. The extension of FRAM operation to low voltage requires reduction of PZT thickness to 100 nm which is accompanied by a degradation of saturation polarization as well as reliability properties. It will be shown that the application of a seeding layer offers a solution to the reliability problem. The sensing margin of the device is enhanced by a careful optimization of the Ti/(Zr+Ti) ratio of the PZT film.

For ferroelectric random access memory (FRAM) to be beneficial in future mobile devices, high-density FRAM with nm scaled cell should be developed. We have succeeded in scaling further the cell size of one-pass transistor and one-storage capacitor (1T1C) FRAM down to 0.27 µm2 at 150 nm technology node. Owing to new SrRuO3 (SRO) electrode technology along with ultrathin PbZrTiO3 (PZT) using metal organic chemical vapor deposition (MOCVD) technology, two-dimensional (2-D) metal–insulator–metal (MIM) ferroelectric capacitor was successfully scaled down vertically to 200 nm. By the application of a new double hard mask capacitor etching technology, 0.11-µm2-area 200-nm-thick 2-D PZT capacitor was successfully isolated with 180 nm spacing. As a result, a high remanent polarization of 40 µC/cm2 was obtained at 1.6 V on a 0.11 µm2 ferroelectric storage capacitor of the 0.27 µm2 cell 1T1C FRAM. Great advances in three-dimensional (3-D) ferroelectric capacitor, which is essential for 6–8 F2 cell 1T1C FRAM at nm scaled technology node, have been made by introducing a new atomic layer deposition (ALD) method for 3-D electrode and a novel MOCVD PZT deposition for 3-D PZT. As a result, for the first time, robust hysteresis was obtained from a 3-D PZT capacitor.

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

An advanced bottom electrode contact (BEC) was successfully developed for reliable high-density 256 Mb phase-change random access memory (PRAM) using a ring-type contact scheme. This advanced ring-type BEC was prepared by depositing very thin TiN films inside a contact hole, after which core dielectrics were uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce reset current while maintaining a low set resistance and a uniform cell distribution. Thus, it has been clearly demonstrated that the use of the ring-type contact technology is very feasible for high-density PRAM beyond 256 Mb.

In this paper,the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs (bulk FinFETs). A cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects. A static noise margin of 280 mV was obtained at V/sub CC/ of 1.2 V by applying bulk FinFETs, and compared with those of typical optimized control devices and nanoscale planar channel MOSFETs. The characteristics of the bulk FinFETs were compared with those of nanoscale planar channel MOSFETs, and analyzed in detail by changing nanoscale active width (or fin width). Fabrication process issues for the bulk FinFETs were explained in terms of poly-Si gate over-etching and silicidation on nanoscale fin bodies. Also, input and output characteristics of the individual and parallel arrayed transistors were shown and analyzed.

The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-/spl mu/m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.

We have measured the switching in ferroelectric capacitors of lead zirconate titanate (PZT) over three orders of magnitude in lateral area, from A = 166 to 0.19 µm2 (the latter being the size of the smallest ferroelectric random access memory (FRAM) cells in production), and over three orders of magnitude in ramp rate of applied voltage (d E(t)/d t = 107–1010 V cm−1 s−1). In accord with the model of Scott (1998 Ferroelectr. Rev. 1 1), the submicron cells follow a different dependence to the larger cells: for A\gg 1~\micmu {\mathrm {m}}^{2} , the data fit a theory due to Landauer et al (the LYD model), which neglects nucleation; whereas the nanoscale devices satisfy the functional dependence predicted by Pulvari and Kuebler (the PK model), albeit with a modified coefficient. This crossover behaviour has implications for Gbit FRAM device performance at high speed. Fringing field effects measured agree with a simple model from Feynman.

Highly reliable 32 Mb FRAM was successfully developed by double annealing technique and CVD deposition technique. The highly (1 1 1) oriented ferroelectric films were fabricated by the optimized annealing method, which generates large remnant polarization. In addition to the double annealing process for sol–gel derived ferroelectric films, advanced capacitor technology of CVD process was developed for achieving strong retention properties. The CVD technique provides strong interface between electrode and ferroelectric films, giving rise to minimal integration degradation and large sensing margin. After baking test at 150 °C for 100 h, a wide sensing window of 350 mV was achieved to guarantee strong retention properties for high density FRAM products.

For the first time, we developed 70nm DRAM technology applicable to a manufacturing level. This technology is aimed at DDR-3 application, which requires low-voltage operation and high speed performance. Fully working 70nm DRAMs were realized combining W-gate dual poly process, recess-channel-array-transistors (RCATs), and MIM cell capacitor module. In this paper, we present performance of 70nm node DRAMs which qualifies DDR-3 application requirement.

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer patterning method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices. � 2004 Elsevier Ltd. All rights reserved.

The retention properties were improved by optimizing capacitor process and developing advanced integration process. The retention trends of ferroelectric capacitors before integration were systematically investigated as a function of critical process parameters such as baking temperature and annealing temperature and time. It was found that the ferroelectric capacitors show best retention properties by double annealing process with high baking temperature of 330°C. The optimized ferroelectric capacitors were integrated into 32 Mb FRAM with 0.44 μm2 cell size and 0.25 μm design rule, and evaluated for their retention behavior. Since the retention properties of real cell size capacitors were closely correlated with sensing window, it was focused on enhancing the sensing window by high etching slope and chemical mechanical planarization (CMP) process. It was demonstrated that the retention properties were greatly improved by using optimal capacitor process and advanced integration process.

Current high density FRAM devices have been fabricated by developing several novel integration technologies such as capacitor technology and process technology. The process technology minimizes the integration degradation using stable BC scheme, encapsulating barrier layer (EBL), and effective etching curing process. The capacitor technology generates robust ferroelectric capacitors to be immune to any integration damage by taking advantage of new ferroelectric films and CVD deposition technique. Future FRAM technology will be focused on etchless scheme, nano-scale ferroelectric films, and three-dimensional capacitor scheme using CVD deposition techniques for noble metal electrode with excellent step coverage, which will produces high density 256 Mb FRAM and beyond.

We evaluate different switching behaviors of lead zirconate titanate (PZT) thin film capacitors with two different geometries: one, a square 100×100 μm; the second, a ribbon (1.6 μm width but with approximately the same total area), as a function of temperature T, and applied electric field E. The ribbon capacitor shows a stronger dependence (by ca. 70%) of activation field on T and E. This is interpreted as a chemical reduction of edge material in the long-perimeter ribbons due to plasma etching. In order to understand and model the different domain switching of these two types of PZT capacitor, we also investigate impedance spectra at various temperatures from 27 to 470 °C. From ac conductance spectra, both square- and ribbon-type capacitors have similar trap levels, 0.38±0.02 eV. From analysis of conductivity spectra, we find that the ribbon capacitor contains an additional 0.19±0.02 eV trap level attributed to H–O dipoles due to hydrogen reduction; the latter trap results in domain pinning, which is i...

It is revealed that the interface trap generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow-trench isolation (STI)-isolated NAND flash cells shrinks. Furthermore, we argue that the interface trap annihilation phenomenon during retention mode becomes a major failure mechanism of the data retention characteristics of sub-100-nm cells in addition to the conventional charge loss mechanism. A new interface trap analysis method using the hysteresis of the I/sub d/--V/sub g/ curve is proposed and shows that the interface traps consist of fast traps and slow traps.

In order to fabricate nonvolatile 4 Mb ferroelectric random access memory (FRAM) for the application to portable electronic devices, we proposed two noble techniques; (1) shared sense amplifier arrangement structure for reducing a chip size, active current, and power consumption, and (2) address transition detection (ATD) control scheme for asynchronous operation and limited address skew-free. We successfully developed 4 Mb FRAM with the address access time of 90 ns, read/write cycle time of 100 ns, and limited address skew-free of 20 ns at 2.7 V and 85 °C.

We report on the measurements of reliability of 0.25 μ m 15F2 cell FRAM using novel MOCVD PZT technology. The MOCVD PZT capacitors were prepared using a pre-purging process and successfully integrated into the 32 Mb FRAM process with double EBL technology and optimal ILD/IMD scheme. After full integration, the 0.44 μ m2 MOCVD PZT capacitors with a 2Pr value of 35 μ C/cm2 at an applied voltage of 2.7 V show superior retention properties. The MOCVD PZT cells have large sensing windows of 420 mV at an operation voltage of 2.7 V. The sensing windows show only a slight decrease during 100 hours of baking at a temperature of 150°C, after which not a single cells is observed to fail. Therefore, it is clearly demonstrated that using the novel MOCVD PZT capacitors, high reliability of 0.25 μ m 15 F2 cell FRAM can be achieved.

We discuss the correlation between intermetallic dielectric (IMD) processes and electrical properties of fully integrated ferroelectric cells. The best IMD scheme for higher density FRAM devices is proposed regarding gap-filling properties of narrow metal pitches and electrical characteristics. The used oxides were i)HDP, ii)HDP/POX, and iii)PSG/SOG/USG. HDP possesses good gap-filling characteristics due to the simultaneous application of deposition and etching. However it generates large plasma loads to the wafer, resulting in an undesired degradation of the 2Pr values. The HDP/POX stacks employ an additional POX oxide buffer layer in order to minimize damage due to the HDP deposition process, but the application of the double stack structure shows the same degradation as the HDP-only scheme. However, PSG/SOG/USG stack showed good gap-filling characteristics as well as lower 2Pr degradation. In the triple stack, PSG and USG act as a main IMD layer and as an oxide buffer for SOG coating, respectively. In ...

New type of nonvolatile memories like FRAM, PRAM, MRAM which are capable of fast and unlimited write can ideally perform next generation high level mobile functions and are being focused as candidates for next generation mobile memory. Among new memory candidates, MRAM has the fastest speed, FRAM has the lowest power consumption and PRAM has excellent cell scalability. Such unique feature of each new memory candidate will be effectively utilized in next generation mobile electronics where memory function will be very diversified and specified as well as unified. In this paper, new memory technologies will be viewed in respect of current technology status, technical challenges encountered, and the solution for technology barriers.

We have demonstrated a novel three-dimensional multibridge-channel metal-oxide-semiconductor field-effect transistor (MBCFET). This transistor was successfully fabricated using a conventional complementary metal-oxide-semiconductor process. We introduce the fabrication technologies and electrical characteristics of MBCFET in comparison with a conventional planar MOSFET. The MBCFET has more benefits than a conventional MOSFET. It shows 4.6 times larger current drivability than a planar MOSFET. This is due to the vertically stacked multibridge channels. The subthreshold swing of MBCFET is 61 mV/dec, which is almost an ideal value due to the thin body surrounded by gate. Based on a simulation result, we show that the MBCFET will have a large on-off state current ratio at short channel transistors.

Since current 32 Mb high-density ferroelectric random access memory (FRAM) shows very narrow sensing window, it is strongly desired to improve the sensing widow for generating a reliable high yield. In this paper, we propose a TiAlN oxygen stopping layer for enhancing the diffusion barrier layer, which makes it possible to reduce the bottom stack height from 180 nm to 90 nm, resulting in the increase of effective cell area and cell charge. In addition to the enhanced diffusion barrier, we developed a stable PE-SiN etch stopper for replacing Ir noble metal etch stopper that has strong stress variation and eventually deteriorates the cell charge distribution. By using TiAlN oxygen stopping layer and PE-SiN etch stopper, the 32 Mb FRAM device shows very wide sensing window of 100 fC, which guarantees a reliable high yield.

In order to manufacture high-density ferroelectric random access memory (FRAM) device, it is required to develop one mask capacitor etching technology, because it can provide greatly reduced cell size. However, as the capacitor size shrinks further, the influence of etching damage on the ferroelectric properties becomes much serious due to the high ratio of perimeter/area for patterned capacitor. Since undesired polymeric etch byproducts were formed on sidewall of the edge cell capacitors in 32 Mb FRAM with 0.25 μm design rule, we developed novel post-etch curing technology using O2 plasma treatment with wet cleaning process. After the post-etch curing treatment, the hysteresis loops of block edge cells were almost identical to those of block center cells, which results in improving the relative 2Pr value as ratio of edge cells/center cells from 33% to 98%. In conclusion, novel curing technology was successfully developed for one mask etching damaged ferroelectric capacitor using O2 plasma treatment with ...

In the 0.25 μm FRAM technology generation, it is extremely difficult to define the hole-type cell via on very small top electrode area, because there is no process margin for the hole type cell via. Therefore, a runner via technology based on line-type cell via with Ir etch stopper is developed for 0.25 μm FRAM technology generation. However, it was found that the severe charge degradation occurred during the runner cell via process. It was found that the stress of Ir film plays a dominant role in degrading the capacitor value. Since the Ir film shows severe severe stress variation from compressive to tensile during heating and cooling, the ferroelectric capacitors using the Ir etch stopper show the charge degradation during integration. Therefore, we developed a common cell via scheme and stable PE-SiN etch stopper which possess compressive stress and high etching selectivity against PSG film for replacing Ir etch stopper. The polarization value of ferrolectric capacitor was not degraded after etch-stopp...

High performance cell transistor was proposed for long data retention time in mass-produced 512 Mb dynamic random access memory (DRAM) with 0.12 µm design rule. Since process-induced trap density and electric field at the storage node junction should be reduced to improve data retention time, we designed a cell transistor using localized channel and field implantation (LOCFI) scheme. Using LOCFI scheme, the data retention time was nearly doubled by virtue of reduced cell leakage current resulting from the suppressed ion implantation damage and the reduced electric field at the storage node simultaneously. In addition, it was found that the hydrogen annealing after trench etching, the double gate spacer consisting of CVD oxide and Si3N4 layer, and the chemical downstream Si treatment after storage node contact etching significantly improved the data retention time. These proposed approaches for longer data retention time can be applied to future high density DRAMs with feature size down to 0.1 µm range.

Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25-/spl mu/m design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique.

The scaling of the 8F/sup 2/ COB stack DRAM cell down to 70-nm technology node is described. Issues and possible solutions regarding critical points, such as the difficulty in achieving sufficient memory cell capacitance, degraded cell transistor performance, and increased junction leakage current at storage node are investigated. Although its unit cell size is bigger than those of open bit line cell architectures, the 8F/sup 2/ COB stack cell can be the most suitable technology for 70-mn DRAM technology node due to its excellent noise immunity and large capacitor area.

Since the space margin between capacitors has been greatly reduced in 32 Mb high-density ferroelectric random access memory (FRAM) with a 0.25 µm design rule, considering the limitation of current etching technology, the stack height of ferroelectric capacitors should be minimized for stable node separation. In this paper, novel capacitors with a total thickness of 4000 A were prepared using a seeding layer, low temperature processing, and optimal top electrode annealing. The 1000 A Pb(Zr1-xTix)O3 (PZT) films showed excellent structural and ferroelectric properties such as strong (111) orientation and large remanent polarization of 40 µC/cm2. The low stack capacitors were then implemented into 0.6 µm and prototype 0.25 µm FRAM. Compared to a conventional capacitor stack, the ferroelectric capacitors exhibited adequate sensing margin of 250 fC, thus giving rise to a fully working die of 4 Mb FRAM. Therefore, it was clearly demonstrated that the novel capacitors can enable the realization of a high-density 32 Mb FRAM device with a 0.25 µm design rule.

Current and future FRAM technologies are reviewed and discussed for developing high density FRAM devices as stand-alone memory application. In order to enter into mainstream of memory devices, FRAM devices should achieve such small cell size factor of ∼8F 2 , strong reliability, and design optimization. The low cell size factor can be realized by using etchless capacitor technology, ultra thin capacitor technology, and runner via technology. The reliability can be acquired by Pt-inserting technology. Finally, high density FRAM device can be accomplished by design optimization.

Ferroelectric capacitors are severely degraded by integrating interlayer dielectrics (ILD) and intermetallic dielectrics (IMD) due to their undesired hydrogen attack and stress effect. In this paper, it was found that the dielectrics film stress plays more dominant role in degrading submicron 32Mb ferroelectric capacitors (0.48 2 0.92 w m 2 ) than hydrogen attack due to the Ir ATE electrode, which works for blocking hydrogen attack, but generates sever stress variation. Since the Ir film shows severe stress variation from compressive to tensile during heating and cooling cycles, it is desired to prepare compressive ILD and IMD films for compensating the tensile stress. Using P-OX films with compressive stress, the 32Mb ferroelectric capacitors show excellent hysteresis loops with the P r value of 15 w C/cm 2 after completing full integration, which is comparable to 18 w C/cm 2 before the integration. The submicron ferroelectric capacitor prepared by compressive P-OX ILD and IMD materials was successfully ...

As the capacitor size greatly decreases from 1.44 in 4Mb to 0.44 w m 2 in 32Mb FRAM, the hydrogen-damage is severely increased, thus giving rise to the difficulty in protecting the ferroelectric capacitor from the hydrogen attack by using conventional encapsulating barrier layers (EBL). Therefore, it is strongly required to reduce the hydrogen-induced degradation of very small ferroelectric capacitor during the backend integration process. In this paper, we developed double EBL technology by covering whole ferroelectric capacitors again after the Cap-EBL process. The Al 2 O 3 ILD-EBL layer was prepared again after depositing inter-layer dielectrics (ILD) layer, thus eliminating further hydrogen damage during inter-metal dielectrics (IMD) process. Using the double EBL technology, the fully integrated ferroelectric capacitor for 32Mb FRAM exhibits excellent ferroelectric properties such as remnent polarization of 15 w C/cm 2 at 3V. As a result, novel hydrogen-damage free 0.25 w m 15F 2 32Mb FRAM was success...

A timely progress monitoring is essential for the success of a large-scale construction project. It enables a site manager to properly prepare resources and make plans for the remaining part of the construction activities. Recently, mobile computing and image processing have been investigated as a means of automating progress monitoring. Mobile computing is advantageous in wireless data recording, retrieval, and transfer whereas image processing is able to analyze the site images to extract progress information. However, their potential applications in construction monitoring were rather separately studied; synergistic effect of both techniques has not yet been fully materialized. This paper presents an interactive mobile progress monitoring system to enhance the existing progress monitoring practices. The system utilizes the interactive feature of tablet computer to combine the strength of image processing and mobile computing. When a user selects an object on a construction site image in a mobile computing environment, the system provides a list of attributes for the object of interest. In this interactive environment, the user can easily match the object to the right attributes such as location, material type, and relation with other objects. This initial matching can then allow for automatic matching of other objects on the site to the right attributes of their own. The method can raise accuracy of image processing and significantly reduce the effort required to do the pre-processing for progress monitoring. A cable-stayed bridge construction project, a case study, is used to validate the proposed system.